On Thu, Nov 26, 2020 at 4:11 PM Uros Bizjak wrote:
>
> > Hi:
> > This patch is about to delete dead code in
> > ix86_expand_special_args_builtin.
> >
> > Bootstrap and regression test are ok.
> >
> > gcc/ChangeLog:
> > * config/i386/i386-expand.c
> >
Hi:
This patch is about to delete dead code in ix86_expand_special_args_builtin.
Bootstrap and regression test are ok.
gcc/ChangeLog:
* config/i386/i386-expand.c
(ix86_expand_special_args_builtin): Delete last_arg_constant.
From 948756dae8f67bf766714d9ecc064b4eea9952cd Mon
On Wed, Nov 25, 2020 at 7:37 PM Jakub Jelinek wrote:
>
> On Wed, Nov 25, 2020 at 07:32:44PM +0800, Hongtao Liu wrote:
> > Update patch:
> > 1. ix86_expand_special_args_builtin is used for expanding mask load
> > intrinsics, this function will always convert the co
Thanks for the review.
BTW, the patch is already installed because uros helped to review this
patch in another thread
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/558682.html
On Thu, Nov 26, 2020 at 3:15 AM Jeff Law wrote:
>
>
>
> On 11/11/20 1:03 AM, Hongtao Liu via Gcc-p
On Tue, Nov 24, 2020 at 9:00 PM Jakub Jelinek wrote:
>
> On Tue, Nov 24, 2020 at 10:36:49AM +0800, Hongtao Liu via Gcc-patches wrote:
> > > > * gcc.target/i386/pr97642-2.c: New test.
> > > So in the BZ Jakub asked for the all-ones mask case to be specially
>
On Mon, Nov 23, 2020 at 11:54 PM Richard Biener wrote:
>
> On Mon, 23 Nov 2020, Tamar Christina wrote:
>
> > Hi All,
> >
> > This patch adds support for
> >
> > * Complex Addition with rotation of 90 and 270.
> >
> > Addition with rotation of the second argument around the Argand plane.
> >
Hi:
I'm learning about this patch, and I see one place that might be
slighted improved.
+ poly_int64 size = (top - bot);
+
+ /* Assert the edge of each variable is aligned to the HWASAN tag granule
+size. */
+ gcc_assert (multiple_p (top, HWASAN_TAG_GRANULE_SIZE));
+
On Tue, Nov 24, 2020 at 4:27 AM Jeff Law wrote:
>
>
>
> On 11/4/20 2:19 AM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > When programmers explicitly use mask loaded intrinsics, don't
> > transform the instruction to vpblend{b,w,d,q} since If mem_addr points
&g
On Tue, Nov 17, 2020 at 8:05 AM Jeff Law wrote:
>
>
> On 9/2/20 3:34 AM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > Add define_peephole2 to eliminate potential redundant conversion
> > from mask to vector.
> > Bootstrap is ok, regression test is ok
On Fri, Nov 13, 2020 at 3:32 AM Gerald Pfeifer wrote:
>
> Per our discussion on the list (plus a grammer improvement in a
> section above).
>
> One question: why are the ISA extension lists not alphabetically
> sorted? Wouldn't that be beneficial for users? Easier to find
> something and also
Got it.
On Fri, Nov 13, 2020 at 3:26 AM Gerald Pfeifer wrote:
>
> On Wed, 11 Nov 2020, Hongtao Liu via Gcc-patches wrote:
> > + New ISA extension support for Intel AVX-VNNI was added to GCC.
>
> More for the future (i.e., no need to change that now): I suggest
> to skip &
On Thu, Nov 12, 2020 at 5:15 PM Hongtao Liu wrote:
>
> On Thu, Nov 12, 2020 at 5:12 PM Hongtao Liu wrote:
> >
> > On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote:
> > >
> > > On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote:
> > >
> > >
On Thu, Nov 12, 2020 at 5:12 PM Hongtao Liu wrote:
>
> On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote:
> >
> > On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote:
> >
> > > > > gcc/ChangeLog:
> > > > >
> > > > > PR target/97
On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote:
>
> On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote:
>
> > > > gcc/ChangeLog:
> > > >
> > > > PR target/97194
> > > > * config/i386/i386-expand.c (ix86_expand_vector_se
On Wed, Nov 11, 2020 at 4:45 PM Uros Bizjak wrote:
>
> > gcc/ChangeLog:
> >
> > PR target/97194
> > * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function.
> > * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl.
> > * config/i386/predicates.md (vec_setm_operand):
[GCC-11] Mention Intel AVX-VNNI and add it to ALDERLAKE and SAPPIRERAPIDS,
also add HRESET to ALDERLAKE.
diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html
index d7a3a1f9..fc4c74f4 100644
--- a/htdocs/gcc-11/changes.html
+++ b/htdocs/gcc-11/changes.html
@@ -267,15 +267,20 @@ a
ping ^3
Rebase patch on latest trunk.
On Tue, Oct 27, 2020 at 3:51 PM Hongtao Liu wrote:
>
> ping^1
>
> On Tue, Oct 20, 2020 at 3:36 PM Richard Biener
> wrote:
> >
> > On Tue, Oct 20, 2020 at 4:35 AM Hongtao Liu wrote:
> > >
> > > On Mon, Oct 19
On Tue, Nov 10, 2020 at 4:17 PM Hongtao Liu wrote:
>
> On Tue, Nov 10, 2020 at 3:22 AM Jason Merrill via Gcc-patches
> wrote:
> >
> > This patch was also applied to the GCC 9 and 10 branches and breaks those
> > builds, because PTA_CLDEMOTE is not defined.
>
On Tue, Nov 10, 2020 at 3:22 AM Jason Merrill via Gcc-patches
wrote:
>
> This patch was also applied to the GCC 9 and 10 branches and breaks those
> builds, because PTA_CLDEMOTE is not defined.
>
Mine, let me fix it, sorry for that.
--
BR,
Hongtao
On Mon, Nov 9, 2020 at 8:26 PM Uros Bizjak wrote:
>
> On Mon, Nov 9, 2020 at 11:31 AM Hongtao Liu wrote:
> >
> > >
> > > + /* Support unified builtin. */
> > > + || (mask2 == OPTION_MASK_ISA2_AVXVNNI)
> > >
> > > I don't t
ON_MASK_ISA2_AVX2_UNSET;
> }
>return true;
>
Yes.
> No review for the sse.md and for testcases.
>
> Uros.
Update the patch based on latest trunk.
--
BR,
Hongtao
From 881868b8c9f5925c63a953454f45f5e0a3c8ea4f Mon Sep 17 00:00:00 2001
From: liuhongt
Date: Tue, 13 Oct
Hi:
When programmers explicitly use mask loaded intrinsics, don't
transform the instruction to vpblend{b,w,d,q} since If mem_addr points
to a memory region with less than whole vector size of accessible
memory, the mask would prevent reading the inaccessible bytes which
could avoid fault.
On Tue, Nov 3, 2020 at 9:51 PM Richard Sandiford
wrote:
>
> Vladimir Makarov via Gcc-patches writes:
> > On 2020-10-27 2:53 a.m., Hongtao Liu wrote:
> >> Hi:
> >>For inline asm, there could be an operand like (not (mem:)), it's
> >> not a val
rnal/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf
> >
> > Bootstrap ok, regression test on i386/x86 backend is ok.
> >
> > OK for master?
> >
> > 2020-10-13 Hongtao Liu
> > Hongyu Wang
> >
> > gcc/
>
On Fri, Oct 30, 2020 at 1:00 AM Richard Sandiford
wrote:
>
> I guess my main objection is that we have a special memory constraint
> that isn't in fact matching a MEM (at least not directly). That seems
> odd and feels like it's going to come back to bite us.
>
> From an RTL perspective, the MEM
On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > For inline asm, there could be an operand like (not (mem:)), it's
> > not a valid operand for normal memory constraint.
> > Bootstrap is ok, regres
On Wed, Oct 28, 2020 at 8:24 PM Uros Bizjak wrote:
>
> On Wed, Oct 28, 2020 at 10:54 AM Hongyu Wang wrote:
> >
> > Hi Uros,
> >
> > Thanks for the example. We've update the patterns with new expanders
> > and predicates like vzeroall.
> > Now the generated insn for "encodekey128u32" is like
> >
On Thu, Oct 29, 2020 at 2:46 AM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > Hi:
> >> > For i
On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > For inline asm, there could be an operand like (not (mem:)), it's
> > not a valid operand for normal memory constraint.
> > Bootstrap is ok, regres
ping^1
On Tue, Oct 20, 2020 at 3:36 PM Richard Biener
wrote:
>
> On Tue, Oct 20, 2020 at 4:35 AM Hongtao Liu wrote:
> >
> > On Mon, Oct 19, 2020 at 5:55 PM Richard Biener
> > wrote:
> > >
> > > On Mon, Oct 19, 2020 at 11:37 AM Hongtao Liu wrote:
>
Hi:
Sorry for Incomplete test for my last patch at
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555948.html.
This patch should fix invalid address introduced by special memory constraint.
Bootstrap is ok, regression test is ok for make check
Hi:
For inline asm, there could be an operand like (not (mem:)), it's
not a valid operand for normal memory constraint.
Bootstrap is ok, regression test is ok for make check
RUNTESTFLAGS="--target_board='unix{-m32,}'"
gcc/ChangeLog
PR target/97540
* ira.c: (ira_setup_alts):
On Thu, Oct 22, 2020 at 12:36 AM Segher Boessenkool
wrote:
>
> On Wed, Oct 21, 2020 at 04:43:29PM +0100, Richard Sandiford wrote:
> > Hongtao Liu writes:
> > > + poly_uint64 nunits
> > > + = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0)));
>
On Wed, Oct 21, 2020 at 11:04 PM Vladimir Makarov wrote:
>
>
> On 2020-10-20 10:11 p.m., Hongtao Liu wrote:
> >
> > Changed, and it passed the i386/x86-64 regression test.
> >
> > Update patch.
> >
> Thank you, Hongtao. This patch is ok for the tr
On Wed, Oct 21, 2020 at 5:07 PM Jakub Jelinek wrote:
>
> On Wed, Oct 21, 2020 at 02:29:07PM +0800, Hongtao Liu via Gcc-patches wrote:
> > gcc/ChangeLog:
> >
> > PR target/97506
> > * config/i386/i386-expand.c (ix86_expand_sse_movcc): Move
> >
Hi:
Bootstrap is ok, so is i386/x86-64 regression test.
gcc/ChangeLog:
PR target/97506
* config/i386/i386-expand.c (ix86_expand_sse_movcc): Move
op_true to dest directly When op_true equals op_false,
gcc/testsuite/ChangeLog:
PR target/97506
*
On Wed, Oct 21, 2020 at 5:07 AM Segher Boessenkool
wrote:
>
> On Tue, Oct 20, 2020 at 11:20:48AM +0800, Hongtao Liu wrote:
> > + unsigned HOST_WIDE_INT subreg_offset = 0;
> > + if (GET_CODE (trueop0) == SUBREG
> > +
On Wed, Oct 21, 2020 at 12:42 AM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> >> > + && (GET_MODE_NUNITS (mode)).is_constant ()
> >> > + && (GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0
> >> > +
On Tue, Oct 20, 2020 at 10:57 PM Vladimir Makarov wrote:
>
>
> On 2020-10-20 1:33 a.m., Hongtao Liu wrote:
> > On Mon, Oct 19, 2020 at 11:38 PM Vladimir Makarov
> > wrote:
> >>
> >> On 2020-10-11 8:58 p.m., Hongtao Liu wrote:
> >>> Hi:
>
On Mon, Oct 19, 2020 at 11:38 PM Vladimir Makarov wrote:
>
>
> On 2020-10-11 8:58 p.m., Hongtao Liu wrote:
> > Hi:
> >This is done in 2 steps:
> >1. Extend special memory constraint to handle non MEM_P cases, i.e.
> > (vec_duplicate:V4SF (mem:SF (addr)))
On Mon, Oct 19, 2020 at 11:31 PM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Thu, Oct 15, 2020 at 8:38 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > + /* Simplify vec_s
On Mon, Oct 19, 2020 at 5:55 PM Richard Biener
wrote:
>
> On Mon, Oct 19, 2020 at 11:37 AM Hongtao Liu wrote:
> >
> > On Mon, Oct 19, 2020 at 5:07 PM Richard Biener
> > wrote:
> > >
> > > On Mon, Oct 19, 2020 at 10:21 AM Hongtao Liu wrote:
>
On Mon, Oct 19, 2020 at 5:07 PM Richard Biener
wrote:
>
> On Mon, Oct 19, 2020 at 10:21 AM Hongtao Liu wrote:
> >
> > Hi:
> > It's implemented as below:
> > V setg (V v, int idx, T val)
> >
> > {
> > V idxv = (V){idx, idx, idx, idx, idx, idx,
Hi:
It's implemented as below:
V setg (V v, int idx, T val)
{
V idxv = (V){idx, idx, idx, idx, idx, idx, idx, idx};
V valv = (V){val, val, val, val, val, val, val, val};
V mask = ((V){0, 1, 2, 3, 4, 5, 6, 7} == idxv);
v = (v & ~mask) | (valv & mask);
return v;
}
Bootstrap is fine,
On Thu, Oct 15, 2020 at 8:38 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > + /* Simplify vec_select of a subreg of X to just a vec_select of X
> > + when X has same component mode as vec_select. */
> > + int l2;
> >
On Thu, Oct 15, 2020 at 4:14 PM Hongtao Liu wrote:
>
> On Thu, Oct 15, 2020 at 1:37 AM Segher Boessenkool
> wrote:
> >
> > Hi!
> >
> > On Wed, Oct 14, 2020 at 01:43:45PM +0800, Hongtao Liu wrote:
> > > On Wed, Oct 14, 2020 at 4:01 AM Segher Boessenkool
On Thu, Oct 15, 2020 at 1:37 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Wed, Oct 14, 2020 at 01:43:45PM +0800, Hongtao Liu wrote:
> > On Wed, Oct 14, 2020 at 4:01 AM Segher Boessenkool
> > wrote:
> > > On Tue, Oct 13, 2020 at 04:40:53PM +0800, Hongtao
On Wed, Oct 14, 2020 at 5:21 PM Uros Bizjak wrote:
>
> On Wed, Oct 14, 2020 at 11:04 AM Hongyu Wang wrote:
> >
> >
> >
> > Uros Bizjak 于2020年10月14日周三 下午4:42写道：
> >>
> >> On Wed, Oct 14, 2020 at 10:34 AM Hongyu Wang
> >> wrote:
> >> >
> >> > >
> >> > > Please also add -muintr to
On Wed, Oct 14, 2020 at 4:01 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Tue, Oct 13, 2020 at 04:40:53PM +0800, Hongtao Liu wrote:
> > For rtx like
> > (vec_select:V2SI (subreg:V4SI (inner:V2SI) 0)
> >(parallel [(const_int 0) (const_int 1)]
Hi:
For rtx like
(vec_select:V2SI (subreg:V4SI (inner:V2SI) 0)
(parallel [(const_int 0) (const_int 1)]))
it could be simplified as inner.
Bootstrap is ok, regression test on i386 backend is ok.
gcc/ChangeLog
PR rtl-optimization/97249
* simplify-rtx.c
Add new predicate bcst_mem_operand and corresponding constraint "Br"
to merge "$(pattern)_bcst{_1,_2,_3}" into "$(pattern)", also delete
those separate "*_bcst{_1,_2,_3}" patterns.
gcc/ChangeLog:
PR target/87767
* config/i386/constraints.md ("Br"): New special memory
Hi:
This is done in 2 steps:
1. Extend special memory constraint to handle non MEM_P cases, i.e.
(vec_duplicate:V4SF (mem:SF (addr)))
2. Refactor implementation of *_bcst{_1,_2,_3} patterns. Add new
predicate bcst_mem_operand and corresponding constraint "Br" to merge
On Thu, Sep 17, 2020 at 12:10 PM Jeff Law wrote:
>
>
> On 9/15/20 9:20 PM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > Rtx cost of sse_to_integer would be used by pass_stv as a
> > measurement for the scalar-to-vector transformation. As
> > https://gcc.g
Thanks!
On Wed, Sep 16, 2020 at 8:57 PM Uros Bizjak wrote:
>
> > gcc/ChangeLog
> >
> > * common/config/i386/i386-common.c
> > (OPTION_MASK_ISA_AVX_UNSET): Remove OPTION_MASK_ISA_XSAVE_UNSET.
> > (OPTION_MASK_ISA_XSAVE_UNSET): Add OPTION_MASK_ISA_AVX_UNSET.
> >
> >
Thanks.
On Wed, Sep 16, 2020 at 8:54 PM Uros Bizjak wrote:
>
> > gcc/ChangeLog
> >
> > PR target/96861
> > * config/i386/x86-tune-costs.h (skylake_cost): increase rtx
> > cost of sse_to_integer from 2 to 6.
> >
> > gcc/testsuite
> >
> > *
Hi:
If -mavx implies -mxsave, then -mno-xsave should imply -mno-avx.
Current status is -mno-avx implies -mno-xsave which should be wrong.
Bootstrap is ok, Regression test is ok for i386/x86 backend.
Ok for trunk?
gcc/ChangeLog
* common/config/i386/i386-common.c
Hi:
Rtx cost of sse_to_integer would be used by pass_stv as a
measurement for the scalar-to-vector transformation. As
https://gcc.gnu.org/pipermail/gcc-patches/2019-August/528839.html
indicates, movement between sse regs and gprs should be much expensive
than movement inside gprs(which is 2 as
Hi:
This patch would avoid spill gprs to mask registers for non-AVX512
micro-architecture and fix regression in PR96744.
Bootstrap is ok, regression test for i386/x86-64 backend is ok.
No big performance impact on SPEC2017.
gcc/ChangeLog:
PR taregt/96744
*
On Mon, Sep 14, 2020 at 3:51 PM Richard Biener via Gcc-patches
wrote:
>
> On Fri, Sep 11, 2020 at 11:19 PM Nathan Sidwell wrote:
> >
> > I noticed a compiler warning about out-of-bound access. Fixed thusly.
> >
> > gcc/
> > * config/i386/sse.md (mov): Fix operand indices.
> >
On Wed, Sep 9, 2020 at 2:35 PM Jakub Jelinek wrote:
>
> On Wed, Sep 09, 2020 at 10:30:46AM +0800, Hongtao Liu wrote:
> > From 400418fadce46e7db7bd37be45ef5ff5beb08d19 Mon Sep 17 00:00:00 2001
> > From: liuhongt
> > Date: Tue, 8 Sep 2020 15:44:58 +0800
> &
On Tue, Sep 8, 2020 at 4:52 PM Jakub Jelinek wrote:
>
> On Tue, Sep 08, 2020 at 04:14:52PM +0800, Hongtao Liu wrote:
> > Hi:
> > We have "*load_tp_" in i386.md for load of thread pointer in
> > i386.md, so this patch merely adds the expander for
> > __bui
Hi:
We have "*load_tp_" in i386.md for load of thread pointer in
i386.md, so this patch merely adds the expander for
__builtin_thread_pointer.
Bootstrap is ok, regression test is ok for i386/x86-64 backend.
Ok for trunk?
gcc/ChangeLog:
PR target/96955
* config/i386/i386.md
On Mon, Aug 31, 2020 at 8:35 PM H.J. Lu via Gcc-patches
wrote:
>
> On Mon, Aug 31, 2020 at 12:25 AM Richard Biener wrote:
> >
> > On Sat, 29 Aug 2020, sunil.k.pandey wrote:
> >
> > > On Linux/x86_64,
> > >
> > > dccbf1e2a6e544f71b4a5795f0c79015db019fc3 is the first bad commit
> > > commit
Hi:
Add define_peephole2 to perform optimization like bellow:
+/* Optimize for TARGET_AVX512F
+ vpsubusw op1, op2, dst1;
+ vxorps xmm, xmm, dst2; > vpcmpleuw op1, op2, dst3
+ vpcmpeqw dst1, dst2, dst3 */
and
+/* Optimize for target above TARGET_SSE4_1
+ vpsubusw op1, op2, dst1;
On Wed, Sep 2, 2020 at 5:58 PM Jakub Jelinek wrote:
>
> On Wed, Sep 02, 2020 at 09:57:08AM +0800, Hongtao Liu via Gcc-patches wrote:
> > +
> > + first = XVECEXP (constant, 0, 0);
> > + /* There could be some rtx like
> > + (mem/u/c:
On Mon, Aug 31, 2020 at 2:19 PM Hongtao Liu wrote:
>
> Hi:
> This patch is to adjust testcases which failed the regression test
> when gcc is built with -march=skylake-avx512.
> Also add runtime check for AVX512 tests.
>
> gcc/testsuite/ChangeLog:
> PR target/9
Hi:
Add define_peephole2 to eliminate potential redundant conversion
from mask to vector.
Bootstrap is ok, regression test is ok for i386/x86-64 backend.
Ok for trunk?
gcc/ChangeLog:
PR target/96891
* config/i386/sse.md (VI_128_256): New mode iterator.
On Tue, Sep 1, 2020 at 6:11 PM Jakub Jelinek wrote:
>
> On Tue, Sep 01, 2020 at 05:55:18PM +0800, Hongtao Liu wrote:
> > I tried define_split, but there's too many of them(considering usage
> > of define_subst for mask).
> > Also for new added instructions which su
On Thu, Aug 27, 2020 at 8:24 PM Jakub Jelinek wrote:
>
> On Thu, Jul 09, 2020 at 04:33:46PM +0800, Hongtao Liu via Gcc-patches wrote:
> > +static void
> > +replace_constant_pool_with_broadcast (rtx_insn* insn)
> > +{
> > + subrtx_ptr_iterator::array_type array;
&g
Hi:
This patch is to adjust testcases which failed the regression test
when gcc is built with -march=skylake-avx512.
Also add runtime check for AVX512 tests.
gcc/testsuite/ChangeLog:
PR target/96246
PR target/96855
PR target/96856
PR target/96857
*
ping ^2
On Wed, Aug 19, 2020 at 7:37 PM Hongtao Liu wrote:
>
> ping^1
>
> On Tue, Aug 11, 2020 at 5:43 PM Hongtao Liu wrote:
> >
> > Hi:
> > The issue is described in the bugzilla.
> > Bootstrap is ok, regression test for i386/x86-64 backend is ok.
On Thu, Aug 27, 2020 at 8:24 PM Jakub Jelinek wrote:
>
> On Thu, Jul 09, 2020 at 04:33:46PM +0800, Hongtao Liu via Gcc-patches wrote:
> > +static void
> > +replace_constant_pool_with_broadcast (rtx_insn* insn)
> > +{
> > + subrtx_ptr_iterator::array_type array;
&g
Hi:
This patch is to fix a typo in my last patch [1].
[1] https://gcc.gnu.org/pipermail/gcc-patches/2020-August/551982.html
Bootstrap is ok, gcc regression test hosted on CLX for i386/x86-64
backend is ok.
Ok for trunk?
gcc/ChangeLog:
PR target/96755
* config/i386/sse.md:
On Sat, Aug 22, 2020 at 1:08 AM H.J. Lu wrote:
>
> On Fri, Aug 21, 2020 at 10:02 AM H.J. Lu wrote:
> >
> > On Fri, Aug 21, 2020 at 9:46 AM Hongtao Liu wrote:
> > >
> > > On Sat, Aug 22, 2020 at 12:36 AM H.J. Lu wrote:
> > > >
> >
On Sat, Aug 22, 2020 at 12:36 AM H.J. Lu wrote:
>
> On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
> >
> > On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> > >
> > > On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> > > >
> >
On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
>
> On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> >
> > On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
> > >
> > > > > > gcc/
> > > > > > PR target/88808
> &
On Fri, Aug 21, 2020 at 5:44 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > ping ^ 4, it's a very simple fix for ICE.
>
> OK, thanks. (Reviewing on the basis that I agree it's a simple rtx
> correctness fix.)
>
Thanks for the review.
> Richa
On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
>
> > > > gcc/
> > > > PR target/88808
> > > > * config/i386/i386.c (ix86_preferred_reload_class): Allow
> > > > QImode data go into mask registers.
> > > > * config/i386/i386.md: (*movhi_internal): Adjust
On Thu, Aug 20, 2020 at 3:40 PM Uros Bizjak wrote:
>
> On Thu, Aug 20, 2020 at 9:31 AM Hongtao Liu wrote:
> >
> > On Thu, Aug 20, 2020 at 3:24 PM Hongtao Liu wrote:
> > >
> > > On Wed, Aug 19, 2020 at 3:05 PM Uros Bizjak wrote:
> > > >
> >
On Wed, Aug 19, 2020 at 2:31 PM Uros Bizjak wrote:
>
> On Wed, Aug 19, 2020 at 4:17 AM Hongtao Liu wrote:
>
> OK, modulo:
>
> +/* { dg-final { scan-assembler-not "%xmm" } } */
>
> It is not clear to me what the testcase is testing here. The scan
> string i
On Thu, Aug 20, 2020 at 3:24 PM Hongtao Liu wrote:
>
> On Wed, Aug 19, 2020 at 3:05 PM Uros Bizjak wrote:
> >
> > On Wed, Aug 19, 2020 at 4:25 AM Hongtao Liu wrote:
> > >
> > > On Mon, Aug 17, 2020 at 6:08 PM Uros Bizjak wrote:
> > > >
>
On Wed, Aug 19, 2020 at 3:05 PM Uros Bizjak wrote:
>
> On Wed, Aug 19, 2020 at 4:25 AM Hongtao Liu wrote:
> >
> > On Mon, Aug 17, 2020 at 6:08 PM Uros Bizjak wrote:
> > >
> > > On Fri, Aug 14, 2020 at 10:26 AM Hongtao Liu wrote:
> > > >
>
ping^1
On Tue, Aug 11, 2020 at 5:43 PM Hongtao Liu wrote:
>
> Hi:
> The issue is described in the bugzilla.
> Bootstrap is ok, regression test for i386/x86-64 backend is ok.
> Ok for trunk?
>
> ChangeLog
> gcc/
> PR target/96551
>
ping ^ 4, it's a very simple fix for ICE.
On Mon, Aug 10, 2020 at 6:00 PM Hongtao Liu wrote:
>
> Ping^3
>
> On Tue, Aug 4, 2020 at 4:21 PM Hongtao Liu wrote:
> >
> > ping ^2
> >
> > On Mon, Jul 27, 2020 at 5:31 PM Hongtao Liu wrote:
> > >
> >
On Mon, Aug 17, 2020 at 6:08 PM Uros Bizjak wrote:
>
> On Fri, Aug 14, 2020 at 10:26 AM Hongtao Liu wrote:
> >
> > Enable operator or/xor/and/andn/not for mask register, kxnor is not
> > enabled since there's no corresponding instruction for general
> > register
On Mon, Aug 17, 2020 at 5:34 PM Uros Bizjak wrote:
>
> On Fri, Aug 14, 2020 at 10:24 AM Hongtao Liu wrote:
> >
> > Enable direct move between masks and gprs in pass_reload with
> > consideration of cost model.
> >
> > Changelog
>
On Wed, Aug 19, 2020 at 10:17 AM Hongtao Liu wrote:
>
> On Mon, Aug 17, 2020 at 5:34 PM Uros Bizjak wrote:
> >
> > On Fri, Aug 14, 2020 at 10:24 AM Hongtao Liu wrote:
> > >
> > > Enable direct move between masks and gprs in pass_reload wi
On Mon, Aug 17, 2020 at 5:20 PM Uros Bizjak wrote:
>
> On Fri, Aug 14, 2020 at 10:22 AM Hongtao Liu wrote:
> >
> > Hi:
> > First, since avx512 masks involve both vector isa and general part,
> > so i add both maintainers to the maillist.
> >
> > I'm
Hi:
Rewriting testcase with cpp source file, then compare operator could
be used directly for vector, this would avoid impact of vectorizer.
gcc/testsuite/ChangeLog:
PR target/96667
* gcc.target/i386/avx512bw-pr96246-1.c: Moved to...
*
On Fri, Aug 14, 2020 at 5:57 PM Uros Bizjak wrote:
>
> On Fri, Aug 14, 2020 at 8:03 AM Hongtao Liu wrote:
> >
> > Hi:
> > For struct initialization, when it fits in a TImode, gcc will use
> > pinsr insn which causes poor codegen described in PR93897 and PR96562.
Hi:
Since This testcase is used to check generation of AVX512 vector
comparison, scan-assembler for vmov instruction could be deleted, also
-mprefer-vector-width=512 is added to avoid impact of different
default arch/tune of GCC.
Sorry for the inaccuracy of the testcase.
ChangeLog
Enable operator or/xor/and/andn/not for mask register, kxnor is not
enabled since there's no corresponding instruction for general
registers.
gcc/
PR target/88808
* config/i386/i386.md: (*movsi_internal): Adjust constraints
for mask registers.
(*movhi_internal):
1. Set cost of movement inside mask registers a bit higher than gpr's.
2. Set cost of movement between mask register and gpr much higher than movement
inside gpr, but still less equal than load/store.
3. Set cost of mask register load/store a bit higher than gpr load/store.
--
BR,
Hongtao
Enable direct move between masks and gprs in pass_reload with
consideration of cost model.
Changelog
gcc/
* config/i386/i386.c (inline_secondary_memory_needed):
No memory is needed between mask regs and gpr.
(ix86_hard_regno_mode_ok): Add condition TARGET_AVX512F for
Hi:
First, since avx512 masks involve both vector isa and general part,
so i add both maintainers to the maillist.
I'm doing this in 4 steps:
1 - Add cost model for operation of mask registers.
2 - Introduce new cover class INT_MASK_REGS, this will enable direct
move between gpr and mask
Hi:
For struct initialization, when it fits in a TImode, gcc will use
pinsr insn which causes poor codegen described in PR93897 and PR96562.
Bootstrap is ok, regression test is ok for i386/x86-64 backend.
Ok for trunk?
ChangeLog
gcc/
PR target/96562
PR target/93897
On Tue, Aug 11, 2020 at 5:56 PM Uros Bizjak wrote:
>
> On Tue, Aug 11, 2020 at 11:36 AM Hongtao Liu wrote:
> >
> > On Tue, Aug 11, 2020 at 4:38 PM Uros Bizjak wrote:
> > >
> > > On Tue, Aug 11, 2020 at 5:30 AM Hongtao Liu wrote:
> > > &
Hi:
The issue is described in the bugzilla.
Bootstrap is ok, regression test for i386/x86-64 backend is ok.
Ok for trunk?
ChangeLog
gcc/
PR target/96551
* config/i386/sse.md (vec_unpacku_float_hi_v16si): For vector
compare to integer mask, don't use gen_rtx_LT , use
On Tue, Aug 11, 2020 at 4:38 PM Uros Bizjak wrote:
>
> On Tue, Aug 11, 2020 at 5:30 AM Hongtao Liu wrote:
> >
> > Hi:
> > The issue is described in the bugzilla.
> > Bootstrap is ok, regression test for i386/x86-64 backend is ok.
> > Ok for trunk?
>
Hi:
The issue is described in the bugzilla.
Bootstrap is ok, regression test for i386/x86-64 backend is ok.
Ok for trunk?
ChangeLog
gcc/
PR target/96350
* config/i386/i386.c (ix86_legitimate_constant_p): Return
false for ENDBR immediate.
1001 - 1100 of 1240 matches
Mail list logo
