;
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are
I see, it's operator== overloaded.
LGTM.
juzhe.zh...@rivai.ai
From: wangf...@eswincomputing.com
Date: 2024-06-21 17:03
To: juzhe.zhong; gcc-patches
CC: kito.cheng; jinma.contrib
Subject: Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
On 2024-06-21 12:24 juzhe.zhong
Since middle-end patch is approved, LGTM this patch.
Thanks for improving RVV vectorization.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-25 20:40
To: gcc-patches
CC: juzhe.zhong; kito.cheng; richard.guenther; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add testcases for
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 3
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 2
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 4
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 1
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-03 13:22
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
From: Pan Li
It seems that the asm check is incorrect for truncated after
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-07-03 17:39
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; Li, Pan2
Subject: [PATCH] RISC-V: Use tu policy for first-element vec_set [PR115725].
Hi,
this patch changes the tail policy for vmv.s.x
ook odd to me. Could you optimize it in a more straightforward way?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-05 09:23
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
From: Pan Li
+ if (double_mode == E_VOIDmode && quad_mode == E_VOIDmode)
Why we have VOID mode ? I still don't understand the codes.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-08 12:48
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v2] RISC
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-08 14:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
From: Pan Li
This patch would like to implement the .SAT_TRUNC for the RISC-V
return true;
- }
+ riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD);
+ return true;
+}
+
+ return false;
+}
I don't understand why you touch scalar part here ? It looks like formating ?
If yes, it should be another separate patch.
Otherwise, Ok from my
nds[2]))
-DONE;
- else if (riscv_expand_block_move (operands[0], operands[1], operands[2]))
+ if (riscv_expand_block_move (operands[0], operands[1], operands[2]))
DONE;
I think it should be an NFC patch in another separate patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-01
All regressions (zve64d/zvl128b/zvl256b/zvl512b/zvl1024b) passed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-01 08:51
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS regression
This patch fix 2 regression (one
DE (int_reg), dest)));
Use emit_move_insn
+ emit_insn (
+ gen_movdf (dest, gen_lowpart (GET_MODE (dest), int_reg)));
Use emit_move_insn
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-01 15:52
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-01 17:27
To: Roger Sayle; gcc-patches
CC: rdapp.gcc; juzhe.zh...@rivai.ai
Subject: Re: [RISC-V PATCH] Improve style to work around PR 60994 in host
compiler.
Yes, OK, thanks for that. CC'ing Juzhe as this is his pass.
Regards
Robin
One more comment:
+ unsigned int num = (smode == DImode || smode == DFmode)
+ && !TARGET_VECTOR_ELEN_64 ? 2 : 1;
change it into:
unsigned int num = known_eq (GET_MODE_SIZE (smode), 8) &&
!TARGET_VECTOR_ELEN_64 ? 2 : 1;
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-
patches as follows:
1. Add crypto march support (riscv-common.cc）
2. Add crypto machine descriptions (vector-cryptio.md)
3. Add crypto builtin.
4. Add testcases.
Thanks.
juzhe.zh...@rivai.ai
LGTM Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-04 16:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test case for bug PR112813
From: Pan Li
The bugzilla 112813 has been fixed recently, add below test
case for the bug
+ if (!TARGET_64BIT
+ && maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
I think if (maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
should be enough.
Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-05 16:22
To: gcc-pa
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-05 16:38
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution
test) on RV32
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-05 23:13
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add vec_init expander for masks [PR112854].
Hi,
PR112854 shows a problem on rv32 with zvl1024b. During the course
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-06 12:49
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Remove useless modes
From: xuli
gcc/ChangeLog:
* config/riscv/riscv.md: Remove.
---
gcc/config/riscv/riscv.md | 1 -
1 file changed, 1 deletion
cmp (instance.base_name, "vsha2ch") == 0
+ || strcmp (instance.base_name, "vsha2cl") == 0
+ || strcmp (instance.base_name, "vsm3me") == 0)
+ && overloaded_p))
+ b.append_name (operand_suffixes[instance.op_info->op]);
Split them into another s
roup
;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0,
v2, or v4 is not).
;; So the source operand should have LMUL >= 1.
Reference patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/638869.html
Currently, I don't have a soluti
gff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops)
change it into:
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops, true)
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-07 10:15
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; zhusonghe; panciy
perand"" i")
+ (match_operand 8 "const_int_operand"" i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (ashift:VWEXTI
+(zero_extend:VWEXTI
+ (match_operand: 3
I think you can send a single separate patch with adding unsigned int (*avail)
(void)
into current function_group_info first.
And test full coverage current rvv intrinsics.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-12-07 10:28
To: wangfeng; gcc-patches
CC: kito.cheng
Resend the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639728.html
with changelog changes.
No codes change.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-07 18:15
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC
-types.def \
$(RISCV_BUILTINS_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-vector-builtins.cc
in t-riscv file.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-07 20:17
To: gcc-patches
CC: kito.cheng; jeffreyalaw
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-08 16:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in
V_F2DI_CONVERT_BRIDGE
From: Pan Li
The mode attr V_F2DI_CONVERT_BRIDGE converts the floating
+ if (shuffle_series (d))
+ return true;
Could you rename it into shuffle_series_patterns ?
Just to make naming consistent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-09 21:18
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
dest operand always LMUL = 1 mode.
So, when -march=rv64gcv, the dest mode should be V4SI, if
-march=rv64gcv_zvl256b, the dest mode should be V8SI.
...etc. Different TARGET_MIN_VLEN, different M1 mode. It's going to be a big
change in RISC-V backend.
juzhe.zh...@rivai.ai
From: Robin Dapp
I think it's reasonable refactor reduction instruction pattern work around this
issue.
Going to send a patch to apply this solution.
So drop this patch. Sorry for bothering Richard S.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:01
To: Juzhe-Zhong; gcc-patches
CC: rdap
Oh. I just confirmed. V1SI make perfect sens since we never apply partial
vectorization for VLSmode.
Drop this patch and going to refactor reduction pattern to fix this issue.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:11
To: juzhe.zh...@rivai.ai; gcc-patches
CC
. */
+
+static bool
+select_appropriate_lmul (HOST_WIDE_INT length_in,
+HOST_WIDE_INT &lmul_out)
+{
I don't think we need this, you only need to use TARGET_MAX_LMUL
juzhe.zh...@rivai.ai
else if (partial_subreg_p (use->mode (), mode))
use->set_mode (mode);
}
use->record_reference (ref, false);
}
Is it reasonable to you ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 19:45
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; g
Thanks Richard.
Committed with V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640172.html
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 20:12
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; gcc-patches
Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for
lgtm.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-12 16:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
From: Pan Li
This patch would like to disable the avl propagation for the follow
reasons
disable multilib. */
#ifndef _RISCV_VECTOR_WRAP_H
#define _GCC_WRAP_STDINT_H
#include "stdint-gcc.h"
#include_next
#define _RISCV_VECTOR_WRAP_H
#endif
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-12 18:01
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.c
ot:
+ (match_operand: 4 "register_operand" " r, r, r, r")))
+ (match_operand:VI 2 "vector_merge_operand" "vu, vu, 0, 0")))]
+ "TARGET_ZVBB || TARGET_ZVKB"
+ "vandn.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "v
oups[i]);
+ }
I think it should be:
for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
if (avail)
builder.register_function_group (function_groups[i]);
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-13 17:12
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe
-intrinsic v0.11)?
Intrinsics stuff should be very safe.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-12-13 18:09
To: Feng Wang
CC: gcc-patches; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan
Subject: Re: [PATCH v2 1/4] RISC-V:Add crypto vector implied ISA info.
LGTM
On Wed, Dec 13, 2023 at 5
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-13 19:12
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.com
Subject: [PATCH v2] RISC-V: Fix dynamic lmul tests depended on abi
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or
_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
\
+ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO},
3. Recover all DEF_RVV_FUNCTION back to the original.
4. In the following vector crypto intrinsic, you should add like
DEF_RVV_CRYPTO_FUNCTION like aarch64 does
, my question is the COST should be 1 or 2.
It seems that COST = 1 is better for using SELECT_VL.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-13 18:17
To: Juzhe-Zhong
CC: gcc-patches; richard.sandiford; jeffreyalaw
Subject: Re: [PATCH] Middle-end: Adjust decrement IV sty
is better than COST=2.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-14 18:46
To: juzhe.zhong
CC: gcc-patches; richard.sandiford; jeffreyalaw
Subject: Re: [PATCH] Middle-end: Adjust decrement IV style partial
vectorization COST model
Am 14.12.2023 um 09:28 schrieb
Sorry.
This is middle-end patch, sending to wrong CC lists.
Forget about this patch.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 14:52
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] VECT: Support mask_len_strided_load
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-06 16:33
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Adjust FP rint round tests for RV32
From: Pan Li
The FP rint test cases for RV32 need some additional adjust
for types and data
Testcase already existed on the trunk, which is added by Li Pan added recently
when supporting rounding mode autovec.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635280.html
math-llrintf-run-0.c passed on RV64 but cause ICE on RV32.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date
Ping this simple optimization.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 11:34
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction
auto-vectorization
I notice we
e the fallbacks to VLS still
>> available when we prefer scalable vectors?
Yes. since it is -fno-vect-cost-model.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:23
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV
On 11/6/23
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-07 14:41
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP ceil to i/l/ll diff size autovec
From: Pan Li
This patch would like to support the FP below API auto vectorization
with
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:52
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix FAIL of SAD tests for RVV
On 11/6/23 20:36, Juzhe-Zhong wrote:
> RVV didn't ex
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:49
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV
On 11/6/23 20:30, juzhe.zh...@rivai.ai wrote
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:53
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix
FAIL of vect-sdiv-pow2-1.c for RVV#
On 11/6
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-11-07 15:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Fixed failed rvv combine testcases
Hi,
This patch fixed the fellowing failed testcases on
able
vect_pack_trunc test.
But I think we don't need it any more. Your fix looks more reasonable.
juzhe.zh...@rivai.ai
So, this patch not only fixes RVV FAIL, but also fixes GCN ?
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 18:09
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: jeffreya...@gmail.com; rguent...@suse.de
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 07:44
Could you try this ?
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {
xfail { { ! vect_hw_misalign } || { vect512 } } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" {
xfail { ! vect512 }
} } } } */
Could you try again ? If it works for you, I am gonna send V2 patch to Richi.
Thank you so much for help.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 19:21
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428
{
target { ! vect512 } } } } */
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-11-07 19:23
To: ams; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
Do you mean this ?
/* { dg-final { scan-tree-dump-times &qu
SLP" 4 "vect" {
target { vect512 } } } } */
Tested on RVV is OK.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 19:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 11:24, juzhe.zh...@rivai.a
It need command line to enable SIMD auto-vectorization (VLS mode in RVV).
It will enable VLS modes auto-vectorization by default if we didn't add RISCV
into vect_cmdline.
So adding it to disable VLS mode vectorization which will fix the FAILs like
other targets.
juzhe.zh...@rivai.ai
Thanks a lot ! I will send V2 for Richi to review.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 20:05
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 12:03, juzhe.zh...@rivai.ai wrote
Thanks. Committed.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-07 20:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
> It need command line to enable SIMD auto-vectorizat
Thanks Lehua.
Appreciate for supporting subreg liveness tracking with tons of work.
A nit comments, I think you should mention these following PRs:
106694
89967
106146
99161
No need send V2 now. You can send V2 after Richard and Vlad reviewed.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date
e32m1TU
bb 2:
...
vle
vle
vse
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:16
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]
I thought vsetvli insertion will try to merge them into one for
)
|
bb 3
I don't think we should do this on VSETVL PASS.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:16
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]
I thought vsetvli insertion wil
:
__riscv_vsetvl_ratio64
I am no proposing it since it has been used for a long time. Just raise my
concern.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:33
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Normalize user vsetvl
OK
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-08 17:09
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Eliminate unused parameter warning.
From: xuli
The parameter orig_fndecl is not used, use anonymous parameters instead.
../.././gcc/gcc/config
Sorry for wrong description on the log:
After this patch, the IR is:
_36 = .SELECT_VL (ivtmp_34, POLY_INT_CST [4, 4]);
_22 = (int) _36;
vect_cst__21 = [vec_duplicate_expr] _22;
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-08 18:53
To: gcc-patches
CC: richard.sandiford
OK。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-09 14:50
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges
From: Pan Li
This patch would like to fine the frm insn emit when we
meet abnormal edge
Bootstrap + regression on X86 passed.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-08 18:53
To: gcc-patches
CC: richard.sandiford; rguenther; kito.cheng; kito.cheng; Juzhe-Zhong
Subject: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV
PR: https
info)
|| !LOOP_VINFO_VECT_FACTOR (loop_vinfo).is_constant ()))
LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo) = true;
}
The problem is SELECT_VL may produce non-VF in non-final iteration, wheras
MIN_EXPR always has VF on non-final iteration.
Maybe add an assertion to assert non-slp if s
Yes. No regression. Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 07:56
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Move cond_copysign from combine pattern to autovec
pattern
On 11/9/23 16:33, Juzhe-Zhong wrote
it can fix the issue.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 07:58
To: 钟居哲; rdapp.gcc; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.
On 11/9/23 15:43, 钟居哲 wrote:
> Hi. Robin.
[ ... ]
You may need a development version of binutils to ge
How to fix it ? I am pretty noob on testing CI.
Can Robin fix that?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:11
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.
On 11/9/23 18:09, juzhe.zh
I am using --with-arch=rv32gcv --with-abi=ilp32d
I change dg-additional-option into dg-option of all those tests.
Issues gone.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:15
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V
Thanks Jeff. Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:26
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH V3] test: Fix FAIL of pr97428.c for RVV
On 11/7/23 08:18, Juzhe-Zhong wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/pr974
No test?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-10 16:14
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li
The internal-fn has support the FLOATN already. This patch
would like
Hi, Richard.
>> For nested_in_vect_loop we never have LOOP_VINFO_USING_SELECT_VL_P?
Could you give me an example of nested loop ?
For now, I can't produce a case.
Thanks a lot for the comments, I will try to refactor as you suggested.
juzhe.zh...@rivai.ai
From: Richard Biener
Da
ep_vectype,
> + LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo) ? &si : NULL);
again this makes the flow hard to follow. I suppose refactoring this
overall to
if (nested_in_vect_loop)
...
else if (LOOP_VINFO_USING_SELECT_VL_P (..))
...
else
...
and duplicate this tail into th
INFO_USING_SELECT_VL_P to be false if ncopies > 1. */
+ gcc_assert (!LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo));
If it is Ok for you. I am gonna testing it on X86 bootstrap + regtest.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-10 18:19
To: juzhe.zh...@riva
on RISC-V no regression.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 14:55
To: gcc-patches
CC: richard.sandiford; rguenther; Juzhe-Zhong
Subject: [PATCH V2] VECT: Support mask_len_strided_load/mask_len_strided_store
in loop vectorize
This patch adds strided load/store support on
no >= FIRST_PSEUDO_REGISTER;
+}
It depends on how targets configure REGMODE_NATURAL_SIZE target hook.
If we return QImode size, his patch is enable tracking bit ranges 7 bits subreg.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-11-12 19:53
To: 钟居哲
CC: Jeff Law; 丁乐华; gcc-patches; vm
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-12 21:47
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec
From: Pan Li
This patch would like to support the FP below API auto vectorization
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-13 11:10
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix RVV dynamic frm tests failure
From: Pan Li
The hancement of mode-switching performs some optimization when
emit the frm backup
Does this patch fixes exposed bugs in current tests?
Or could you add test for it ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:06
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.
Hi
I know the root cause is:
(reg:DI 15 a5 [orig:175 _103 ] [175])(reg:DI 15 a5 [orig:174 _100 ] [174])
is considered as true on rtx_equal_p.
I think return note1 == note2; will simplify your codes and fix this issue.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:12
To: juzhe.zh
Sorry. It should be return note1 && note2 && note1 == note2;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:12
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.
&
regression of such issue
even if I didn't build toolchain with "zbb".
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:12
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.
&g
lation terminated.
My compile option is : --with-arch=rv32gcv_zfh_zvfh --with-abi=ilp32d
I am using SPIKE but I don't think simulator cause such issue since it is
compile issue.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:52
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff
Also, I didn't enable multi-lib.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:52
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.
> FAIL: gcc.target/riscv/rvv/autovec/slp-mask-run-1.c -O3 -ftree-v
I just checked definition of REG_EQUAL and REG_EQUIV.
As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on
REG_EQUIV and skip REG_EQUAL.
Could you check whether it does fix your issues ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 17:25
To: juzhe.zh
Ok. Lehua is going to take care of this issue. He has reproduced it.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 17:31
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.
> I'm
a constant is loaded into a register that is never
assigned any other value, this kind of note is used.
I think REG_QEUIV is what I want. So I think you can test it to see if there is
regression on current tests.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 17:34
To: juzhe.zh...@riv
If there is a difference between them. I think we should fix riscv-common.cc.
Since I think "zvfh_zfh" should not be different with "zfh_zvfh"
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 18:17
To: Lehua Ding; juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.ch
Thanks for noticing it.
Will commit it with adjusting the testcase.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 18:05
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Optimize combine sequence by merge approach
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