Hi al,
the difference is noticeable. I started out with the Etch 2006 package
and ran in to all kind of pesty little problems. That all disappeared
when I ran the ISO disk compiling the whole shebang from scratch.
Now everything works fine, so yes in my opinion Hamisch should be
convinced to
Hi Peter,
before your post I already started with the ISO disk and an old PC from
scratch. A quick fresh Etch and a bucket load of additional libs ran
through with only minor glitches. The end result YES gEDA up and running.
Next step will be to transplant this installation on the productive
Hi Werner,
I took a look at the script myself and couldn't figure it out also, what
went wrong. But I had other problems too with the 2006 Etch version.
Now the ISO disk 2007 version is up and running, and you guessed it the
tragesym problem has disappeared miraciously :-)
Thanks for your
On Saturday 01 December 2007, Stuart Brorson wrote:
* If you use ngspice for simulation, you can use an Octave
plug-in to plot your results using Octave. (Octave is an
open-source MATLAB equivalent.) Here's a link:
http://ngspice.sourceforge.net/octavespice.html
If Gnucap exports .raw
On Saturday 01 December 2007, Werner Hoch wrote:
That's right, but the format still does not contain all
required informations to use the data.
This is easy.
* your loosing the headlines
can easily be added .. need a spec. could use the CaZM format,
which is already supported by gwave.
Hi Al, Stuart and all,
On Samstag, 1. Dezember 2007, al davis wrote:
On Saturday 01 December 2007, Stuart Brorson wrote:
* If you use ngspice for simulation, you can use an Octave
plug-in to plot your results using Octave. (Octave is an
open-source MATLAB equivalent.) Here's a link:
Hi Stephen and all,
On Montag, 26. November 2007, Stephen Williams wrote:
I've made a new release on the Icarus Verilog v0_8-branch git branch.
This is 0.8.6, which includes various safe fixes and updates to the
stable release. The source tarball and release notes are here:
On Saturday 01 December 2007, Stuart Brorson wrote:
* QUCS. This is really more of an entire simulation system
with options to perform various analog, RF, and maybe digital
simulations. I don't know how far along it is, or how easy it
is to use.
It is windoze-style, fully integrated,
Hi all,
On Mittwoch, 28. November 2007, Stuart Brorson wrote:
This is to announce the fourth release in the stable branch of
gerbv, 1.0.3.
Thanks for that work. The two bugs I've noticed on my box are gone.
(status message and window size).
I've updated the SuSE rpms to 1.0.3
More infos
Werner Hoch wrote:
It seems strange to me that when there is an obvious, easy to
read for humans, easy for a computer to read, easy to generate
format, that everything except Spice uses .. that Spice
doesn't change to that format.
Every Spice variant has its own raw format. They should
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
John,
Ok! Don't worry about this anymore. I finally made my own set of tools :)
They are programmed in Java as this is a bit more understandable for me
than Perl... I parse and write pcb files abstract tree and have a set of
tool to rotate, update,
Wow, incredible support!
Don't let anyone say you don't help out newbies.
I have the kids this weekend so I won't get a chance to work on this until
late Sunday est.
Thanks!
On Dec 1, 2007 11:12 AM, Dan McMahill [EMAIL PROTECTED] wrote:
Werner Hoch wrote:
It seems strange to me that when
How do I print only the solder layer mirrored? I don't need to print all
9/10 pages everytime.
tj
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How do I print only the solder layer mirrored? I don't need to print all
9/10 pages everytime.
The easiest way is to export to postscript, select the multiple
files option, and only print the solder layer file.
Me, I use ghostview, which lets me preview the pages and select which
ones I want
On Sat, 01 Dec 2007 11:12:52 -0500, Dan McMahill wrote:
How well to ascii output files scale when you want to write out 30,000
node voltages and be able to pick out one to plot without it taking a
long time? I don't know the answer, but it seems like a binary format
could have advantages
After a quick review, polygon isn't defined. How does it relate to
board', layer, drawing layer, outline, rectangle, etc...
I added polygon, and updated some of the related terms. Thanks!
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After further review, thermal is not defined.
Added. Thanks!
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Add keepout and courtyard, although not yet implemented.
Added.
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I want to label my layers such that you can look through the board and
read all the numbers, but the solder-side one insists on being mirrored,
and mirror buffer won't fix it.
--
Ben Jackson AD7GD
[EMAIL PROTECTED]
http://www.ben.com/
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The last sentence in the definition of annulus seems ambiguous:
I rewrote it to make it clearer, and added examples. I'll probably go
through and add illustrations to many of those also.
When the netlist and the board agree, the board is done.
The simplest thing to do is remove the
I want to label my layers such that you can look through the board
and read all the numbers, but the solder-side one insists on being
mirrored, and mirror buffer won't fix it.
There's a trick, yes. Put the text on the component side, and 'm'
move it to the solder side.
I don't really want to have my mounting holes labelled with silkscreen,
but neither do I want to simply delete their element names (in case I
ever need gsch2pcb to work again). Is there another way to hide those
names? I've considered just dragging them all outside the outline...
--
Ben
You could shrink the names and position them over the drill hole :-)
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I think you are looking for hide -- position the cursor over the
element, and hit 'h', and it will hide the refdes. That is exactly what
I do for hardware.
-dave
Ben Jackson wrote:
I don't really want to have my mounting holes labelled with silkscreen,
but neither do I want to simply
On Sat, 2007-12-01 at 13:20 -0500, tj wrote:
How do I print only the solder layer mirrored? I don't need to print all
9/10 pages everytime.
Not what you asked, I know, but for UV exposure / toner transfer, isn't
the solder side best printed un-mirrored? (And the component side
mirrored), such
[moved to -user]
On Sun, 2 Dec 2007, Stephen Williams wrote:
A couple things:
1) You don't want the -tfpga flag on your command line. That is
for synthesis, but you are trying to simulate.
OK, I did try it without but I was looking for various options that
might help :)
2) This looks like
PCB notices if you use 'move line to layer' on one segment of a trace
and creates vias as needed to keep that trace connected (at least at
the ends, it doesn't notice if you made a big 'x').
If you move a multi-line trace to another layer piece by piece, you end
up with unnecessary vias. I see
On Sat, 01 Dec 2007 20:57:08 -0800, Ben Jackson wrote:
PCB notices if you use 'move line to layer' on one segment of a trace
and creates vias as needed to keep that trace connected (at least at the
ends, it doesn't notice if you made a big 'x').
If you move a multi-line trace to another
On Sun, 2 Dec 2007, Kai-Martin Knaak wrote:
On Sat, 01 Dec 2007 20:57:08 -0800, Ben Jackson wrote:
3) As in (2), but the via-creation code is changed to set AUTOFLAG (so
the via is created by the autorouter) and only vias that were auto-
created in this was are removed (other rules same as
It might be good (if not too hard) to have hyperlinks in the text
when a definition uses one of the terms also defined in the
document. I found myself jumping back and forth between the
definitions, especially where a definition used a term further down
in the list that I had not read yet.
I posted the updated files:
http://www.delorie.com/pcb/docs/gs/
I started adding illustrations to the terminology section. Just a few
terms, those that *need* illustrations, have them.
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