Hi All,
We can all agree that the current gEDA(Gschem/Gnetlist) need to
accomodate more
than just the netname attribute attached to a net. In fact, I would
like to
see that gEDA can process ANY attributes attached to a net in similar
fashion as it process ANY attributes attached to a symbol
On Sat, 14 Aug 2010 09:53:55 +0800, Steven Michalske smichal...@gmail.com
wrote:
To make this point clear to get companies like IBM to support GPL V3
they had to put in clauses that excepted them from the IP rules.
[citation needed]. This is pure FUD.
Also see this clause
On Sat, 14 Aug 2010 00:23:10 +0200, Armin Faltl armin.fa...@aon.at wrote:
I want to contribute or give away what I want to and keep
my own what I want to keep and if this is not possible with a
GPL-license on my own library liked to my own app, I just won't use GPL!
If you want to distribute
On Fri, 13 Aug 2010 18:09:08 -0600, John Doty j...@noqsi.com wrote:
Unfortunately, some of our
developers take the attitude that dumbing down the (almost supernaturally
productive) UI is the way to attract more developers.
Who?
This is especially problematic at the guile
scripting
Paul Tan wrote:
Hi All,
We can all agree that the current gEDA(Gschem/Gnetlist) need to
accomodate more
than just the netname attribute attached to a net. In fact, I would
like to
see that gEDA can process ANY attributes attached to a net in similar
fashion as it process ANY attributes
Peter TB Brett wrote:
Um, sorry? Are you trying to argue that people who develop libraries and
release them under the GPL are trying to have their cake and eat it? I
don't see it -- I think you need to explain further.
I don't recall anyone holding a gun to your head and forcing you to use
On Aug 14, 2010, at 1:17 AM, Paul Tan wrote:
Hi All,
We can all agree that the current gEDA(Gschem/Gnetlist) need to accomodate
more
than just the netname attribute attached to a net. In fact, I would like to
see that gEDA can process ANY attributes attached to a net in similar
fashion
On Aug 14, 2010, at 4:05 AM, Armin Faltl wrote:
Maybe as long as I don't sell my non-free
code but just use it in house to compute results GPL doesn't bite,
but I don't want to be restricted in that way either.
GPL does not restrict your use of my code, but if you wish to distribute my GPL
On Sat, 14 Aug 2010 10:01:44 -0600, John Doty j...@noqsi.com wrote:
Not important. The quick fix (make the stack bigger) is known and should
be
incorporated in the distributed system-gnetlistrc. The problem is a
consequence of dropping a functional language into a procedural culture:
it
will
Oliver King-Smith wrote:
I am trying to get some rules programmed into my magic tech file. In
particular I want to require metal to encompass the vias by 2um if the
metal is wide metal (10um x 10um). Otherwise I only need to
encompass the vias by 0.8um. Does anyone know how to
On Sat, Aug 14, 2010 at 03:17:42AM -0400, Paul Tan wrote:
...In fact, I would like to see that gEDA can process ANY attributes
attached to a net in similar fashion as it process ANY attributes
attached to a symbol currently.
I agree, but I'm not sure this would be useful until we find a way
On Aug 14, 2010, at 10:51 AM, Peter TB Brett wrote:
On Sat, 14 Aug 2010 10:01:44 -0600, John Doty j...@noqsi.com wrote:
Not important. The quick fix (make the stack bigger) is known and should
be
incorporated in the distributed system-gnetlistrc. The problem is a
consequence of dropping a
On Aug 14, 2010, at 11:34 AM, Andrew Poelstra wrote:
On Sat, Aug 14, 2010 at 03:17:42AM -0400, Paul Tan wrote:
...In fact, I would like to see that gEDA can process ANY attributes
attached to a net in similar fashion as it process ANY attributes
attached to a symbol currently.
I agree,
What do folks use for ASIC layout here?
I do have gnetlist producing the .mag and .net files for magic. I
can't say I am wild about using guile. It would be nice to have the
option to use ruby or some other scripting language.
Oliver
On Sat, Aug 14, 2010 at 12:14:58PM -0600, John Doty wrote:
On Aug 14, 2010, at 11:34 AM, Andrew Poelstra wrote:
On Sat, Aug 14, 2010 at 03:17:42AM -0400, Paul Tan wrote:
...In fact, I would like to see that gEDA can process ANY attributes
attached to a net in similar fashion as it
On Saturday 14 August 2010, Armin Faltl wrote:
I think I have the following options then:
a) fix the bug myself and reinvent your convenience function
which is questionable
b) re-release my library under LGPL and ask you to resubmit
the patch with same license
c) open source or shred my
al davis wrote:
On Saturday 14 August 2010, Armin Faltl wrote:
I think I have the following options then:
a) fix the bug myself and reinvent your convenience function
which is questionable
b) re-release my library under LGPL and ask you to resubmit
the patch with same license
c) open
Hi John Doty,
On Aug 14, 2010; 08:49am, John Doty wrote:
Except that it's slightly broken in the symbol case. Symbols are
looked up by
refdes, but a component may be represented by multiple symbols with
the same
refdes. Also, there may be more than one attribute with the same
name, but
Well, as you suggest below, Groups are essentially a way of tagging
different parts, so they would be completely independent of the physical
layers - and the connectivity checker.
** Confusingly, PCB already has layer groups, which consist of
multiple layers. A layer group is what ends up
On Aug 14, 2010, at 1:28 PM, Oliver King-Smith wrote:
What do folks use for ASIC layout here?
I do schematic-level ASIC design and simulation for Osaka University with
gEDA/ngspice, but I don't do layout. Another company (in Japan) does that. I
believe they use Mentor Graphics tools for
On Sat, Aug 14, 2010 at 10:28:09PM +0200, Armin Faltl wrote:
Well, as you suggest below, Groups are essentially a way of tagging
different parts, so they would be completely independent of the physical
layers - and the connectivity checker.
** Confusingly, PCB already has layer groups,
On Aug 14, 2010, at 1:33 PM, Armin Faltl wrote:
John Doty wrote:
GPL does not restrict your use of my code, but if you wish to distribute my
GPL code under the GPL terms, you must abide by those terms.
If I'm using your library licensed with GPL in a proprietary application of
mine,
I've just ordered a new laptop and have gone over to the Dark Side.
What's the latest best-practice for building and/or running gEDA/gaf
and pcb on OS X? From my minimal knowledge, my options are:
1) VirtualBox an Ubuntu guest OS. This is my fallback, and is how I've
been running gEDA on WinXP
On Aug 14, 2010, at 3:03 PM, Gareth Edwards wrote:
2) Fink. I think John Doty uses this, and there is still a link to Jon
Schneider's build instructions using Fink on the wiki
You don't need to build it unless you want to run a development version.
Charles Lepple does a great job of
John Doty wrote:
On Aug 8, 2010, at 4:51 PM, kai-martin knaak wrote:
No it is not. Even simple things like footprint names have a pretty rigid
syntax to adhere to. The workflow breaks in cryptic ways if they are not
obeyed.
This is a pure pcb limitation, not a gEDA limitation in
I'm the maintainer of the geda-gaf port on MacPorts and it should
install pretty well under both gtk-x11 and gtk-quartz. Actually, let
me know if it does not work.
Mark
On Sat, Aug 14, 2010 at 5:16 PM, John Doty j...@noqsi.com wrote:
On Aug 14, 2010, at 3:03 PM, Gareth Edwards wrote:
2)
On Aug 14, 2010, at 3:29 PM, Armin Faltl wrote:
John Doty wrote:
On Aug 8, 2010, at 4:51 PM, kai-martin knaak wrote:
No it is not. Even simple things like footprint names have a pretty rigid
syntax to adhere to. The workflow breaks in cryptic ways if they are not
obeyed.
On Sat, 2010-08-14 at 23:29 +0200, Armin Faltl wrote:
Isn't a chain as strong as it's weakest link ?
There is no chain!
gschem - ... - PCB
is one workflow, amongst multiple.
OK, maybe the one most people use currently.
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On Aug 14, 2010, at 2:18 PM, Paul Tan wrote:
Is the case you mentioned above relates to the problem of slotting in
PCB?
No. It can happen whenever you have multiple symbols with the same refdes,
regardless of the back end. Slotting is a particular case of this, but not the
only one. It's a
Oops, forgot the attachments!
barfoo.sch
Description: Binary data
foobar.sch
Description: Binary data
On Aug 14, 2010, at 3:45 PM, John Doty wrote:
On Aug 14, 2010, at 2:18 PM, Paul Tan wrote:
Is the case you mentioned above relates to the problem of slotting in
PCB?
No. It can
On Aug 13, 2010, at 7:51 PM, kai-martin knaak wrote:
The utter failure of early
efforts to base AI on classification of objects should surely have taught
that to us.
The success of mathematics and biology to conquer their vast fields with
hierarchical classification is telltale.
On Friday 13 August 2010 18:14:17 Stefan Salewski wrote:
You may look at a few (old) bug reports of gentoo bug database:
http://bugs.gentoo.org/buglist.cgi?quicksearch=ALL+gwave
This one was one very demanding:
http://bugs.gentoo.org/show_bug.cgi?id=293397
yes thanks
I also came
Hi Andrew Poelstra,
On Aug 14, 2010; 10:34am, Andrew Poelstra wrote:
On Sat, Aug 14, 2010 at 03:17:42AM -0400, Paul Tan wrote:
...In fact, I would like to see that gEDA can process ANY attributes
attached to a net in similar fashion as it process ANY attributes
attached to a symbol currently.
On Sat, 2010-08-14 at 18:57 -0400, Paul Tan wrote:
Hi Andrew Poelstra,
On Aug 14, 2010; 10:34am, Andrew Poelstra wrote:
Otherwise, certain nets (such as power or ground nets), which often
have vastly different characteristics in different sections, would
be difficult to describe.
If
On Aug 14, 2010, at 4:57 PM, Paul Tan wrote:
If the split nets means BUS, such as addrBus[63:0] which
can be split into addrBus[12:0], addrBus[15], etc; or even
the notion of Compound BUS such as addrBus[63:0],ALE,CTRL,
it can all be done with the backend scheme code. It really
depends on
On Aug 14, 2010, at 4:57 PM, Paul Tan wrote:
gnet-verilog.scm is the Verilog netlister, which already handle
merging and splitting busses, and hierarchy. An example schematic
files with generated Verilog netlist can be found in the attached
zip file at:
I just looked through Paul's examples, and it looks just like what I'm
proposing except for the GUI details and where in the flow they're
converted. Paul's examples even look like mine.
I reused the existing BUS graphic to represent a bus, so that the NET
graphic could remain a net, where Paul
Hi ALL,
On Aug 14, 2010; 04:33pm, DJ wrote:
While I applaud his results (yay!) I think it would be better if a
bus
were a bus and a net were a net, so that DRC and gnetlist could be a
little smarter about detecting errors and resolving conflicts. One
example: a single-signal net with two
Seems to work, I pushed it to master tree. Thanks!
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More generally: What config files does import schematics look at?
Importing uses pcb's internal paths, not gafrc. Gnetlist simply
passes the list of elements to pcb and lets pcb load them.
You can point pcb's m4 library at a non-existing directory, I suppose.
Look at make_footprint_hash() in
On Aug 14, 2010, at 2:16 PM, John Doty wrote:
The only real problem with Fink is that it gets itself tied in knots
occasionally. Every couple of years, I have to rm -rf /sw and reinstall the
whole thing.
The only *other* problem with Fink is that is doesn't always play well with
This should be documented in the manual.
Done.
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Applied, thanks!
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