Ok, I could have stopped there, canceled my email and continued with
my board, but then I felt the need to ask why this FreeRotateBuffer()
isn't more visible in the user interface?
I added it :-)
It was all of a three-line change to support it, and one line per GUI
to add it.
Thanks for all the inputs, all valuable. I'd like to maintain the
fiction that I might hack on gEDA development properly one day so I'm
going to do two things:
1) install it on an Ubuntu VM anyway, as I don't want to be that far
away from a Linux install for other reasons
and
2) have a crack at
On Sat, Aug 14, 2010 at 4:24 PM, Peter TB Brett pe...@peter-b.co.uk wrote:
On Sat, 14 Aug 2010 09:53:55 +0800, Steven Michalske smichal...@gmail.com
wrote:
To make this point clear to get companies like IBM to support GPL V3
they had to put in clauses that excepted them from the IP rules.
Here is how i do it.
Use macports to install it the first time. sudo port install geda-gaf
Then build the packages from source use git ;-) and fun.
On Sun, Aug 15, 2010 at 2:06 PM, Gareth Edwards
gar...@edwardsfamily.org.uk wrote:
Thanks for all the inputs, all valuable. I'd like to
Hi John Doty,
On Aug 14, 2010; 02:45pm; John Doty wrote:
No. It can happen whenever you have multiple
symbols with the same refdes, regardless of
the back end. Slotting is a particular case
of this, but not the only one. It's a pure
gnetlist problem, having nothing to do with
pcb.
That is
On Sun, 2010-08-15 at 00:35 -0400, DJ Delorie wrote:
More generally: What config files does import schematics look at?
Importing uses pcb's internal paths, not gafrc. Gnetlist simply
passes the list of elements to pcb and lets pcb load them.
You can point pcb's m4 library at a
For PCB, you'd edit $HOME/.pcb/settings to say something like:
lib-newlib =
../imported-symbols/:../gedasymbols.org_salewski_symbols/:../custom-symbols/
lib-contents-command = /bin/true
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Stefan Salewski wrote:
On Sat, 2010-08-14 at 18:57 -0400, Paul Tan wrote:
On Aug 14, 2010; 10:34am, Andrew Poelstra wrote:
Otherwise, certain nets (such as power or ground nets), which often
have vastly different characteristics in different sections, would
be difficult to describe.
I think
DJ Delorie wrote:
Also, my proposal is to have the busses converted to multiple
independent nets in the common parts of gnetlist, so that you don't
have to tweak every single backend to add support for them. You can
still support magic net names that the backends understand, if you
want, but
Sure, and the big EDA code based on LISP/Guile also uses syntax for
names so a wire with such a name attrib seems to be all that's
necessary to define a bus. Putting the syntax netname[0:7] into
form netname[0], netname[1], for the backends is fine. Seems
to me the common code would
Paul Tan wrote:
That is the problem, whenever you have multiple
symbols with the same refdes, as I suspected
and mentioned in my previous post.
.
.
.
The final PCB netlist wants to see PACKAGE_refdes
instead of LOGICAL_SYBOL_refdes. So one of the
solution is (as I stated before and explain
One of the things we need for pin/gate swapping in pcb is a UUID for
each logical symbol in the schematic set. Refdes is not unique enough :-(
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DJ Delorie wrote:
I published my paper mostly to get a discussion going on what busses
*mean* though, not the implementation details. For example, what does
it mean when three busses with different names are connected?
D[15:0] ==** D[15:0]
||
\\
DJ Delorie wrote:
One of the things we need for pin/gate swapping in pcb is a UUID for
each logical symbol in the schematic set. Refdes is not unique enough :-(
Yep. Maybe it could be handled without needing to see it all the time?
Since UUIDs are long... they could be a generated attribute
Hello Paul,
On Aug 15, 2010, at 4:08 AM, Paul Tan wrote:
Hi John Doty,
On Aug 14, 2010; 02:45pm; John Doty wrote:
No. It can happen whenever you have multiple
symbols with the same refdes, regardless of
the back end. Slotting is a particular case
of this, but not the only one. It's a
DJ Delorie wrote:
More generally: What config files does import schematics look at?
Importing uses pcb's internal paths, not gafrc.
This adds to the confusion. Both methods to transfer the the schematic
information to pcb should come up with the same set of footprints with no
subtleties in
And what will these subnets translate into in a layout tool? How
would that translation be handled in the net list? A net is a net in
my designs. If I have a subnet that I want handled differently
from the rest of the net, that is not something that is added to a
schematic because it is not
Rick Collins wrote:
And what will these subnets translate into in a layout tool? How would
that translation be handled in the net list? A net is a net in my
designs.
.
.
.
If I really want to designate portions of a net that need to be
separated by some PWB feature, I draw them as separate
There has been a lot of discussion on this list about new gEDA structures
and different ways of defining and applying DRC rules. (Mainly, net classes
and the ability to assign different rules to different nets.)
I'm working on implementing my functional block proposal. Right now the
DRC rules
Rick Collins wrote:
How would you make use of subnets that would be useful that you
can't do with just nets?
Of course you can do everything manually in the layout app. Just like you
can do any layout without a schematic in the first place. But the schematic
serves as a convenient way to
On Sun, 2010-08-15 at 12:36 -0400, Rick Collins wrote:
And what will these subnets translate into in a layout tool? How
would that translation be handled in the net list? A net is a net in
my designs. If I have a subnet that I want handled differently
from the rest of the net, that is
At 01:16 PM 8/15/2010, you wrote:
Rick Collins wrote:
And what will these subnets translate into in a layout tool? How
would that translation be handled in the net list? A net is a net
in my designs.
.
.
.
If I really want to designate portions of a net that need to be
separated by some
I don't see anything in your post that actually
addresses a need for subnets. Or maybe I don't
understand what a subnet is. From the context
used I figured it meant a portion of a net which
had special attributes separate from the rest of
the net. If you simply are talking about adding
Andrew Poelstra wrote:
The string value would support the wildcards ? and * for single- and
multi- character matching. I don't think more wildcards (or a full regex
engine, for that matter) would be necessary, and would certainly slow the
thing down.
Please make regexp matching optional. It
John Griessen wrote:
Rick Collins wrote:
How would you make use of subnets that would be useful that you
can't do with just nets?
After my last post, I saw you could argue, You can do that with just nets.,
and I see your point that from a schematic view a net is a net, and most
of the use of
Stefan Salewski wrote:
And I can not imagine that commercial EDA tools do not support the
layouter in a similar way as we now consider.
By the way, protel99SE did so more than 10 years ago...
---)kaimartin(---
--
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
Andrew Poelstra wrote:
So here is my proposal for structuring DRC rules.
.
.
Each rule is composed of a Filter, to choose which parts the rule applies to,
and a Rule, to specify the parameters these parts must conform to. Both the
Filter and the Rule will be the same data structure: let's
I see we are talking about two different things. I was responding to
Andrew's post about splitting nets into portions with different
properties. In my way of thinking if they have different properties,
they should be separate nets.
I see that your example of Power/Bypass we are talking
On Sun, 2010-08-15 at 14:10 -0400, Rick Collins wrote:
I see we are talking about two different things. I was responding to
Andrew's post about splitting nets into portions with different
properties. In my way of thinking if they have different properties,
they should be separate nets.
On Sun, Aug 15, 2010 at 01:11:15PM -0500, John Griessen wrote:
Andrew Poelstra wrote:
So here is my proposal for structuring DRC rules.
.
.
Each rule is composed of a Filter, to choose which parts the rule applies to,
and a Rule, to specify the parameters these parts must conform to. Both
On Sun, 2010-08-15 at 21:03 +0200, Stefan Salewski wrote:
attributes/class). For my picture P1 is a common point of these subnets.
One restriction is: This subnet with property bypass shall be short, low
impedance.
Sorry, I forgot:
Points which connects subnets will be always pads or pins on
At 03:03 PM 8/15/2010, you wrote:
On Sun, 2010-08-15 at 14:10 -0400, Rick Collins wrote:
I see we are talking about two different things. I was responding to
Andrew's post about splitting nets into portions with different
properties. In my way of thinking if they have different properties,
This seems like a pretty sharp group. One of the problems I
consistently have is generating an XYRS file for auto assembly of my
boards. The X and Y require a specified origin and orientation of
the board, which is done in the fab drawing. The side is pretty
clear as well. But I always
My experience: ask you assembly house. The guys I work with us the
fiducial in the bottom right as the zero, and rotations CCW.
One issue (big issue) is that components have varying rotations in the
reels, so assembly houses prefer to confirm the rotations against a
prototype board. IPC-7531
D[15:0],A[1:16] with a branch called A[1:16]
I was thinking the above renames the wires but perhaps that's a bad
idea. Yeah, I guess it would have to create a bundle of 32 wires.
No reason you couldn't attach some random attribute to the bus that's
just to give it a mnemonic name :-)
When I
More generally: What config files does import schematics look at?
Importing uses pcb's internal paths, not gafrc.
This adds to the confusion.
No, this is the same confusion that's always existed, which is why we
wanted to get rid of gsch2pcb and *only* use pcb's list. We've always
had
On Sun, 2010-08-15 at 15:43 -0400, Rick Collins wrote:
First, I want to say that power supply bypassing is probably not a
good example to use since there are a number of ways to layout such
things and many people will disagree about the optimal way of doing
it. Perhaps a more general
At 04:27 PM 8/15/2010, you wrote:
On Sun, 2010-08-15 at 15:43 -0400, Rick Collins wrote:
First, I want to say that power supply bypassing is probably not a
good example to use since there are a number of ways to layout such
things and many people will disagree about the optimal way of doing
On Sun, 2010-08-15 at 16:43 -0400, Rick Collins wrote:
At 04:27 PM 8/15/2010, you wrote:
On Sun, 2010-08-15 at 15:43 -0400, Rick Collins wrote:
For details see the related posting in this list...
Maybe you are missing my point. What value does the subnet have if
the layout TOOL doesn't
On Sun, Aug 15, 2010 at 01:11:15PM -0500, John Griessen wrote:
Sounds good. Do you imagine constructing a set of objects, (a LISP list
maybe),
that belong to a range after the filters are done, and then doing operations
on it such as sum up number values of capacitance? If you maintain
Rick Collins wrote:
First, I want to say that power supply bypassing is probably not a good
example to use since there are a number of ways to layout such things
and many people will disagree about the optimal way of doing it.
I think it's an OK example. There's no need to assume any way of
Rick Collins wrote:
you still have to decide if the bottom side is
viewed from the top or the bottom.
Always take the viewpoint of looking down at the board
as it physically would be, never as a see through image
is what they want.
When I have asked assembly houses about what they assume as
DJ Delorie wrote:
JG wrote:
When I say modules, I'm thinking in verilog, where a port
corresponds to a pin, and a port can be multiwire. Or, you could
define pin as single wire and create a new thing called a port, that
has multiwire function.
I'm worried about pcb, though, where pin ==
Stefan Salewski wrote:
OK, one more, but very special case,
where subnets may be useful: We can have nets of 3 nodes, where we want
a linear shape, not a T or star shape. For this case we may define one
subnet from pin 1 to 2, and one more from 2 to 3. We make these two
subnets not compatible,
Hi John Doty,
On Aug 15, 2010; 08:18am; John Doty wrote:
A front end function gnetlist:get-all-symbol-attributes
would make a pretty decent primitive factor here.
It could return a nested list like:
( ( ( refdes U1 )
( device 7400 ) )
( ( refdes U1 )
( device 14pwr )
Rick Collins wrote:
This pie-in-the-sky stuff is fine, but I can see much more utility
coming from more mundane developments.
It's not pie in the sky. Some of these ideas to use sets and lists
and groups are the easiest kind to implement... Zones in layout are
an easy part of what it
Right, when we have a signal-pin-symbol relation, we have a bunch of
information:
* net name
* pin number
* pin sequence
* pin label
* physical pin location
If I have a bus A[1:3] connected to pin EN[0:2] at pin number 4,8,7 -
I mean the same as if I had connected net A1 to pin EN0 at 4, A2 to
Andrew Poelstra wrote:
Suppose I have a trace whose clearance is set to 2.5mm - if I lay any component
too close while the real-time DRC is running, how can it know that it's breaking
a rule without re-checking the clearance for every object on the PCB?
Hmm... well, I have not written DRC
I just found something that changes what I thought I knew. I have a
PDF of an IPC magazine from 2005 where they are touting a leap
forward in land pattern generation. An illustration showing pin 1
in the upper left for SOT components is what I used as my
reference. That and the post in the
DJ Delorie wrote:
Right, when we have a signal-pin-symbol relation, we have a bunch of
information:
* net name
* pin number
* pin sequence
* pin label
* physical pin location
If I have a bus A[1:3] connected to pin EN[0:2] at pin number 4,8,7 -
I mean the same as if I had connected net A1 to
So, in this example, pin label is EN[0:2], pin number list is (4,8,7),
netname is A[1:3].
Right.
bus pin confuses me. Is there another name for what you are thinking?
It's a symbolic pin that means multiple physical pins. It can look
the same or look different, doesn't matter to me, but I
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Am 15.08.2010 22:25, schrieb DJ Delorie:
D[15:0],A[1:16] with a branch called A[1:16]
I was thinking the above renames the wires but perhaps that's a bad
idea. Yeah, I guess it would have to create a bundle of 32 wires.
No reason you
in general I don't like having 2 names for the same net, Maybe I'm
biased with my experience of vhdl synthesis, normally the name that you
don't expect survives synthesis and the other one gets lost (and that
even may vary between two releases of the same tool). So having only one
name has
DJ Delorie wrote:
bus pin confuses me. Is there another name for what you are thinking?
It's a symbolic pin that means multiple physical pins. It can look
the same or look different, doesn't matter to me, but I figured a bus
pin would be thicker, and could connect directly to a bus, instead
Thanks. The chip design tools don't worry with making busses look
any different unless added by the user just for looks. For them,
the different label does it all. But they done' have that
additional constraint of a package.
Right, with verilog signal is more abstract - one signal can be
DJ Delorie wrote:
You can refer to the nets within the bus when you pull them out for
a connection:
A[0:15],D[0:7],RD,WR,EN - all the nets
A[0:1],RD,EN - some of the nets
A15,D[0:7],WR,EN - some of the nets
but we could also give the *grouping* a name, like
At 06:02 PM 8/15/2010, you wrote:
That's what Tom Hauscherr mentioned talking about layout, LP Wizard
IPC and EIA on the 10th herein Austin. EIA made a standard that
noone would use
once and they were dropped for a while until they got specifying tape
and reel to do. They do it differently.
On Aug 15, 2010, at 4:15 PM, DJ Delorie wrote:
I called it bus pin meaning a pin that connects to a bus, vs a pin
that connects to a net, in gschem. I mean, we already have two
fundamental connection types in gschem - nets and busses. Why don't
we have two pin types that correspond?
But
Hello, Paul.
On Aug 15, 2010, at 3:34 PM, Paul Tan wrote:
Hi John Doty,
On Aug 15, 2010; 08:18am; John Doty wrote:
A front end function gnetlist:get-all-symbol-attributes
would make a pretty decent primitive factor here.
It could return a nested list like:
( ( ( refdes U1 )
(
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Am 16.08.2010 00:07, schrieb DJ Delorie:
in general I don't like having 2 names for the same net, Maybe I'm
biased with my experience of vhdl synthesis, normally the name that you
don't expect survives synthesis and the other one gets lost (and
But in Paul's approach, every connection is a bus.
To use your own words: But synthesis is not the only geda flow!
With physical electronics, individual electrical connections are
fundamental, and groupings are synthetic. They're totally distinct
concepts, unlike in synthesis.
I completely disagree.
Yes, I expected you to.
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On Sun, Aug 15, 2010 at 04:46:55PM -0500, John Griessen wrote:
Andrew Poelstra wrote:
Suppose I have a trace whose clearance is set to 2.5mm - if I lay any
component
too close while the real-time DRC is running, how can it know that it's
breaking
a rule without re-checking the clearance
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