- back-annotation to schematic from the PCB editor.
An example of where this is essential is if impedance controlled nets
end up having to cross plane breaks and extra capacitors have to be
added to couple the ground return paths between the planes.
A net in the schematic may have an impedance
What is mfgs?
Manufacturers?
(Not sure why they'd be bothered to contribute symbols anyway. They do
very few for commercial packages.)
Andy.
signality.co.uk
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Which browser and OS are you using ?
Chrome (with default settings i.e. JS enabled) on WinXP Pro SP3 32 bit.
Haven't tried it at home with FF on LMDE 64 bit.
:)
BTW; just submitted a couple of your pages to:
http://validator.w3.org/
Quite a few errors. H.
:(
Andy
Hi Stephen,
FWIW,
It's not clear to me if the prices shown are in $AU or $US and the
option to select one or the other doesn't appear to change the prices
shown on the products or in the cart.
I'm in the UK on a fairly throttled broadband connection and the
pictures took some seconds to load.
Hi John,
Sounds like you've not yet found this:
http://geda.seul.org/wiki/geda:faq-gnetlist
I know, netlist isn't necessarily the first search term that comes
to mind when looking for info on how to generate a BoM ...
See also:
http://geda.seul.org/wiki/geda:faq-attribs
Cheers,
?!?
John
On Wed, Aug 17, 2011 at 9:43 AM, Andy Fierman
[1]andyfier...@signality.co.uk wrote:
Hi John,
Sounds like you've not yet found this:
[2]http://geda.seul.org/wiki/geda:faq-gnetlist
I know, netlist isn't necessarily the first search term that comes
to mind
Drifting off topic ... but going with the flow somewhat:
I've been running Linux Mint Debian Edition 64bit since about February
this year.
Very impressed.
I like the rolling distro idea. So far nothing serious has broken and
have not had to be too techy with it. There are some good ideas coming
Is it just me being a Grumpy Old Man or does anyone else take issue
with RS over their advertising for their Design Spark EDA tool?
In particular the statement at the end of the last paragraph in:
http://www.designspark.com/content/designspark-pcb-version-2-takes-pcb-design-another-dimension
As long as you have access to a single wire and not the return path!
:)
Andy.
signality.co.uk
On 13 July 2011 22:48, Stephen Ecob silicon.on.inspirat...@gmail.com wrote:
On Thu, Jul 14, 2011 at 1:18 AM, David C. Kerber
dker...@warrenrogersassociates.com wrote:
Hi, electronics
the same, so the distortion is in the transformer. If you say it
doesn't work then why doesn't it work?
On 22/06/11 22:39, Andy Fierman wrote:
Sorry Robert,
Both Wojciech and I are wrong.
His suggestion about adding a choke is basically the same as mine of
using a transformer
The most recent circuit you posted is not the same as your original
and as Gene pointed out, you have now made a series resonant circuit
between the 220nF cap and the 200uH primary inductance.
In the simulation, the source resistance is zero, the ESR of the cap
is zero and there is only 0.25R
Ooops,
Just missed the Undo Send window ...
Typo in (i):
if the source has a peak to peak swing of x volts but a dc offset of y
then (neglecting the diode drops) vcc = x/2+y and vss = x/2-y.
:)
Andy
On 19 June 2011 11:01, Andy Fierman andyfier...@signality.co.uk wrote:
Rick
Simply reproducing the filter twice, one for each polarity of
rectifier will not work.
If you can float the load or the source then splitting the circuit
into two and using a bridge rectifier in each will work OK.
The attached shows what I mean.
Cheers,
Andy.
www.signality.co.uk
Oh, yes. We like this!
Cheers,
Andy.
signality.co.uk
On 31 May 2011 07:11, Russell Dill russ.d...@asu.edu wrote:
As edge rates increase, signal intergrity (SI) becomes more and more
important, even for the hobbyist. Unfortunately, the models provided
by semiconductor vendors
Well done that man.
Cheers,
Andy.
On 23 May 2011 05:18, Steven Michalske smichal...@gmail.com wrote:
Cool,
Got photos?
Steve
On May 22, 2011, at 6:57 PM, John Doty j...@noqsi.com wrote:
Well, here I am in Osaka. It's Monday morning, and I just saw the prototype
Soft
and it is extremely hard to get
zeners to not gag in the middle of a transient sim I was looking for a
very generic all purpose model that won't yak. It doesn't haven't to
be accurate, just work.
On Mon, Apr 18, 2011 at 1:38 PM, Andy Fierman
andyfier...@signality.co.uk wrote:
Hmmm.
Tricky things zener
Hmmm.
Tricky things zener, schottky and soft recovery diode models ...
Try a different vendors model (check to see if it is actually a
different model)?
You could try using a V (voltage) source in series with an ordinary
diode plus a second diode in anti-parallel with the series V and
diode.
If you are going to model the PA - particularly to look at resonance
effects - then you should include reasonably accurate models for the
inductors and capacitors which include their major parasitic
components.
The Murata Chip S-Parameter Impedance Library is a handy tool for
looking at their
Uwe is spot on.
The capacitance vs. voltage of the X7R dielectric is not very good.
NP0/COG are usually specified for precision timing and filter
applications.
NP0/COG also have a much lower temperature coefficient.
Andy.
On 11 April 2011 15:58, Uwe Bonnes
Fairchild no longer make the 2N3416 so there is no longer a direct
link to it. However, after a bit of educated guesswork it turns out
that you can still get their model.
Follow this link then fill in the form.
http://www.fairchildsemi.com/cgi-bin/email_model.cgi?file=2N3416.mod
Andy.
:)
Andy.
www.signality.co.uk
On 4 February 2011 21:27, Peter Clifton pc...@cam.ac.uk wrote:
On Fri, 2011-02-04 at 13:07 +, Andy Fierman wrote:
* Sorry, I can't remember who.
John Luciani. I think.. http://www.luciani.org/index.html
He has a lot of nice footprints available
I downloaded a copy something over a year ago. I gave up on it very
quickly because (if I remember correctly) it's very limited in terms
of circuit size and model and symbol creation/editing.
Andy.
www.signality.co.uk
On 4 February 2011 07:05, Gareth Edwards
Sorry if I seem a bit scathing but it seems less an interesting
article, more a very wordy advert.
And I'm struggling with the Open Source part of the title.
Free, yes. FOSS; no.
As a schematic capture and pcb layout package it looks nice.
As an EDA tool it looks a bit thin.
And as for:
.
Someone* on this list has a tagline along the lines of: You can't
design open hardware using closed source tools.
Andy.
www.signality.co.uk
* Sorry, I can't remember who.
On 4 February 2011 09:54, Gareth Edwards gar...@edwardsfamily.org.uk wrote:
On 4 February 2011 09:28, Andy Fierman
I reached much the same place ...
Is this it?
Chortle-Technology Mapping for Lookup Tables (ZIP File)
on this page:
http://www.eecg.toronto.edu/~jayar/software/software.html
Otherwise try contacting Jonathan Rose directly.
Andy
signality.co.uk
On 13 July 2010 15:27, John McCaskill
Hi Hari,
If you want to simply model the bidirectional behaviour of a
transformer to see - very roughly - what the input to the transformer
looks like but are not too worried about the ac behaviour then an
ideal transformer like this will do the job.
**
* This is the
Another problem is that the ear is very sensitive to the delay between
the note being struck and the actual sound being produced. The
processing delay has to be in the order of a few milliseconds or life
gets very confusing for the player and any other listeners.
The guitars Roland built for
Could be interesting.
Thanks for that!
Cheers,
Andy.
Signality Solutions
York, UK
t: +44 (0) 5601 720 580
m: +44 (0) 7796 538 192
skype: andyfierman
www.signality.co.uk
On 24 February 2010 15:12, Kai-Martin Knaak k...@familieknaak.de wrote:
I just got aware of the open source
Larry,
Are you thinking of this:
http://www.liquidpcb.org/index.html
?
Cheers,
Andy.
Signality Solutions
t: +44 (0) 5601 720 580
m: +44 (0) 7796 538 192
skype: andyfierman
www.signality.co.uk
On 21 February 2010 03:20, Larry Battraw lbatt...@gmail.com wrote:
I had a quick
Hi Gene,
As has already been mentioned, the problem will be what happens as the
supply turns on. In theory, as VCC ramps up, the 431 will start to
regulate and so limit its own cathode voltage. However, there may be a
delay before this starts to happen (due to the devices internal
startup and any
Hi Chris,
Welcome to the free world!
If you've not already found it, a good place to start is here:
http://geda.seul.org/wiki/geda:gsch2pcb_tutorial
then have a good read of:
http://geda.seul.org/wiki/geda:gschem_symbol_creation
and
http://geda.seul.org/wiki/geda:transistor_guide
Then
Hi Gene,
The usually quoted formula is:
IS = A*exp(-Eg/(k*T)
Where
IS = saturation current,
A is nearly constant independent of temperature and dependent on
diffusion coefficients of electrons and holes.
k is the Boltzmann constant. ν is a constant; 1 for germanium and 2
for silicon; and
T is the
Now don't open your presents all at once!
Save some to read for the rest of those long dark winter nights .
:)
Cheers,
Andy.
www.signality.co.uk
2009/11/24 Karl Hammar k...@aspodata.se:
A lot of people responding:
On Tue, Nov 24, 2009 at 9:34 AM, Karl Hammar k...@aspodata.se
Hi Torsten,
Have a wander round:
http://www.cherryclough.com/Pages/Publications%20and%20downloads.htm
and
http://www.signalintegrity.com/
After all, push your signal fast enough and you can no longer treat
the PCB and the schematic as separate entities.
Cheers,
Andy.
Hi Karl,
It's worth having a look around Doug Self's site:
http://www.dself.dsl.pipex.com/ampins/ampins.htm
A lot of the info has been removed in advance of his publishing a new
book but there's a lot of other stuff there and pointers to more.
Andy.
www.signality.co.uk
2009/11/24
Hi Gene,
Some more things to think about as sanity checks.
Following on from Peter's question, what is the gain of your amplifier
(including any effects of the source resistance if it's an inverting
amplifier configuration)?
You say that The gain is sufficiently large that the opamp is driven
For the opa2132, it's not clear what the slew rate would do as it
comes out of saturation but it may well only really add some delay
rather than reduce the slew rate.
Using opamps as comparators can be tricky. Alan's suggestion of using
something from the LM339 / LM2907 / LM3302 comparator family
There are some nice little tools to show the behaviour of multilayer
chip ceramics (and some of Murata's inductors)
Although they don't include their single layer microwave caps in the
database, the Murata Chip Capacitor and Inductor S-Parameter
Impedance Library program from here:
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space that you could use for additional ground planes and
that you might need to run traces ...
... and then urges you to run power traces where?
In the - now empty - Vcc plane layer?
Or in the same layer as your
Please excuse me if if I haven't understood your question correctly
but if your question is about making a PCB element then would this
help?
http://www.geda.seul.org/wiki/geda:pcb_tips
and in particular,
http://brorson.com/gEDA/land_patterns_20070818.pdf
Andy.
2009/9/10 Goran
Hi Robert,
I think if you look for the system-gschemrc file (probably in
/etc/gEDA/) then you'll find a section in there
; net-style string
;
; Set to thin if you want thin nets.
; Set to thick if you want thick nets.
; This mode also determines what net style gets printed
;
;(net-style
Hi Micheal,
Sorry about that, Al Davis is right, OFF doesn't seem to help.
Here are two ways to fix the problem.
1) As has already been described, if you start the simulation with the
supply voltage at 9V but apply an initial condition of 0V to one of
the transistor bases - using the .IC spice
Hi Michael,
Another way to do this is to use the OFF option in the bipolar
transistor model to force one of the transistors into a known initial
state.
I'm not sure how you introduce this parameter into you particular
simulation schematic, you may have to just hand edit the device model
in your
Add the pins to the symbol, name them as already suggested and then in
schematic add one of the not connected symbols
(nc-bottom/left/right/top-1.sym in the Misc unsorted symbols
library) to each pin.
That should ensure that all the pins in the symbol and the footprint
then match but the nc
...@ssalewski.de:
On Mon, 2009-06-15 at 10:27 +0100, Andy Fierman wrote:
Add the pins to the symbol, name them as already suggested and then in
schematic add one of the not connected symbols
(nc-bottom/left/right/top-1.sym in the Misc unsorted symbols
library) to each pin.
That should ensure
Hi,
I'm puzzled by a couple of gschem DRC errors I'm getting.
I'm using Stefan Salewski's quad comparator symbol with the separate
power pins symbol. I have four comparators plus the power pin symbol
all with the refdes of U1. All symbols are given an SO14.fp footprint.
When I run:
gnetlist
Hi John,
The comparator symbol has a numslots and slotdef attributes and I have
edited the slot attribute for each. The power pin symbol does not have
a numslots or any slotdef attributes.
I've got the right pinout for each of the four comparator symbols in
gschem and as I say, the connectivity
THEY USE IT?
On Jun 11, 2009, at 10:28 AM, Andy Fierman wrote:
Hi,
I'm puzzled by a couple of gschem DRC errors I'm getting.
I'm using Stefan Salewski's quad comparator symbol with the separate
power pins symbol. I have four comparators plus the power pin symbol
all with the refdes of U1
Stefan,
I should have said that I am using your latest symbols after all
it was me that found the slotting bug.
I've not tried Kai-Martin's symbols yet.
:)
Andy.
http://.signality.co.uk
2009/6/11 Stefan Salewski m...@ssalewski.de:
On Thu, 2009-06-11 at 17:28 +0100, Andy
Bug report posted . ID: 2793743
:)
BTW the version I'm using pops up various messages about things not
being implemented yet such as opening a file, finding or searching for
attributes. Is that what you'd expect from this version?
Thanks,
Andy
The version of gattrib I'm using (1.4.0.20080127 from the Debian lenny
repos) has the option to add a new attribute column (Edit Add new
attribute column).
Having read the gattrib readme I'm confused by how this function behaves.
Say I have attributes A, B , and D in my schematic and I want to
Hi Stuart,
Should I file a bug report?
Should have said: I'm running the 64bit debs from the Mepis 8 repos on
a dual core Athlon machine.
2009/5/18 Stuart Brorson s...@cloud9.net:
Hi --
Say I have attributes A, B , and D in my schematic and I want to add a
new attribute C to all the
Quick tip on your schematic: it's a good idea to offset 4 wire
junctions (C1, R1, R2 Q1b) so that they appear as two pairs of 3
wire junctions. That way even if the junction dot disappears in a .png
or .pdf or whatever, it is obvious that the 4 wires are all joined and
it's not just 2 wires
Interesting idea.
Looks like it's a single (maybe double) sided through hole PCB.
Probably only a low frequency board.
I can see this may have some advantages for high current and therefore
maybe switch mode PSU's but it may only have limited use for the
following reasons:
i) All tracks have
As Anthony has already asked, where is a copy of the schematic? I
followed your link but haven't found one from there yet.
For guitar pickup modelling, you might like to do a bit of Googling on
spice model guitar pickup or similar.
The first one I found was this
Hi,
I am new to gEDA and have a question about how to make gschem
attributes invisible in the schematic.
I think I understand the basics of how to create and edit symbols with
their associated attributes and text etc.
* This is what I want to do:
Add a set of attributes to every symbol I
Duncan,
That's exactly what I needed thanks!
Andy.
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John,
Thanks for that. I think I may have mislead a bit by saying that I
wanted to edit my attributes in the schematic. Thinking a bit more and
reading your comments of course I wouldn't want to edit much in a
schematic for the reasons you describe. If I wanted to convert all the
R's and all the
John,
Also, I was a bit sloppy in my library terminology. I didn't mean
local library as in /usr/share/gEDA/sym/local. I meant as in
${HOME}/gaf/gschem-sym.
I've had a quick play to prove to myself that I can set up a gafrc
file and libraries anywhere I want.
Andy.
H I now see more what John D was warning me about. I hadn't
realised that once a component is placed in a schematic although the
graphical stuff is loaded from the library at gschem startup, the
texty bits such as footprint aren't.
For instance if I place my mosfet with
Hi Stefan,
Sorry, forgot to set composer to plain text ..
Edit / Update component has basically the same effect as closing and
restarting gschem: it updates the graphical parts of a symbol but not
the text attributes.
If I enclose the text attributes in curly brackets in the symbol file
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