Vaclav -
The characteristic you are seeing is a known bug in 1.6.0 - there is
a patch for it in 1.6.1.
That being said - I am trying to make 1.6.1 and hit the following error:
/usr/bin/ld: cannot find -lltdl
collect2: ld returned 1 exit status
make[3]: *** [libgeda.la] Error 1
make[3]:
resistors, and this seems to come up as not unique in the
call. Is there another argument I can give the component-library call to
uniquify the library name?
Cheers!
Tony Radice
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Gentlemen -
Isn't 1.6.1 the latest gschem release? I just went to update my
installation, and I see that 1.6.0 is still the latest. Would someone
advise which is which?
Thanks!
Tony
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I'm in for $20 - just identify where it should go.
Tony Radice
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Gentlemen - and Ladies if appropriate -
Is there a way to incluse comment fields - specifically RCS type tags
- in a schematic symbol file?
I would like to include my symbols in a CVS structure and want to tag
them. Any advice?
Thanks
Tony Radice
Ladies and Gentlemen -
Is there an update to gschem scheduled, and if so, when? Is there a
release notes that we can view to know what is coming?
Thanks!
Tony Radice
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again recommend talking to the fab house!
Good Luck!
Tony Radice
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Actually DJ, I am interested in the algorithm used TO make them unique -
I am considering a methodology of testing panelized boards that takes
the uniqued refdes's into account.
Tony
On Sun, 2010-01-31 at 13:37 -0500, DJ Delorie wrote:
My question: What is the methodology used for resetting
Kip -
This is actually very timely - went to get this app and tried to
install. No Joy: Following is result:
[r...@gandalf gerbmerge-1.1]# python setup.py install
Traceback (most recent call last):
File setup.py, line 9, in module
from gerbmerge.gerbmerge import VERSION_MAJOR,
John -
Thanks for the reply - but no joy... same results.
T.
On Sat, 2010-01-30 at 12:29 -0600, John Griessen wrote:
Tony Radice wrote:
Kip -
This is actually very timely - went to get this app and tried to
install. No Joy: Following is result:
[r...@gandalf gerbmerge-1.1
Krzysztof
That was it! Thank You!
On Sat, 2010-01-30 at 21:12 +0100, Krzysztof Kościuszkiewicz wrote:
Krzysztof
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Does anyone know a method of drawing objects (specifically, lines or
keepouts) on the Solder Mask Layer?
Thanks!
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OK. I would like to recommend this feature for the following reason: My
Board House tells me that soldermask extending to the end of the board
tends to peel after the scoring/routing process to separate boards. As a
result, they recommend a 15 mil or so clearance at the edge of the
boards.
On
to look at it and start
teaching myself how to do this inside the tool... I'm no expert, but
He CAN be taught!...
Cheers!
Tony
On Mon, 2010-01-25 at 22:18 -0500, Dan McMahill wrote:
Tony Radice wrote:
Larry -
Thanks for the heads up on the xy data - from what I am getting from
my CM
On Mon, 2010-01-25 at 22:23 -0500, Dan McMahill wrote:
Tony Radice wrote:
As I am also developing a Perl script to write an IPC-D-356 data file
It would be very helpful of someone could provide the following four
bits of information:
1) In a Via definition, the first three fields
length long - it was a quick write-up to get rid of orphan lines
hiding under pads and such. Anyone else interested?
Cheers!
Tony Radice
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Larry -
Thanks for the heads up on the xy data - from what I am getting from
my CM this is not the data he needs: He needs a formatted X Y Data set
for the pick and place machines. This is why I am developing the script
to be able to use the formatted output.
But you tagged me into a
This is a resend - Postmaster advised as undeliverable before.
I Highly recommend the following:
1) Use Hierarchical design - I have worked on schematics ranging
from a few sheets to a monster 390 C-Size sheets - USE
HIERARCHY!! It will make your design flow MUCH
Has anyone encountered converting pcb data to manufacturer pick and
place or test data formats? (For example: IPC-D-356?) Would anyone have
any hints or criteria to do so? (Again, for example: Where is the
origin for a data file written in the IPC-D_356 format? Upper left? Y is
positive doing
Folks -
In the Netlist section of a PCB file a net has the following form:
NET(netname (unknown))
(
Connect(node_member)
Connect(node_member)
...
)
My question is: What is the unknown field and what is it for?
Thanks!
Tony
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Gentlemen – First – Happy New Year!
And just to start the New Year off I had an interesting problem crop up
on a design in progress.
1. I started off by building a new component (UCI... attached) for
a DC-to-DC Converter. I copied the coils for the transformers
from a
; charset=UTF-8
On Wed, 2009-12-02 at 09:16 -0600, John Griessen wrote:
Tony Radice wrote:
8) What happened: All components got ripped off the board and the new
parts file was populated with the parts with prefix-appended part
numbers (SA4/R112).
I think taking away the netname
Folks -
I need a hint on settings. Here is the scenario:
1) I have a heirarchical schematic developed - level one linking seven
sheets on level two. Each page on level two has a reference designator
of SAn (ie: SA1, SA2, ...etc)
2) I have a PWB developed for the design. Currently each part
that would make a
few more (12?) more convenient.
I thank you for your hard work and wish you the best in the
Christmas holidays!
Cheers!
Tony Radice
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The idea of a 56 layer board makes my eyes water.
I Have worked on a 36, and that was (believe me) BAD ENOUGH!!
T.
Outstanding Work, Gentlemen...
On Fri, 2009-11-27 at 11:29 -0500, DJ Delorie wrote:
I've tested up to 56 just by using the add new layer button.
.
On Fri, 2009-11-27 at 20:25 +0100, Gabriel Paubert wrote:
On Fri, Nov 27, 2009 at 12:41:45PM -0500, Tony Radice wrote:
The idea of a 56 layer board makes my eyes water.
I Have worked on a 36, and that was (believe me) BAD ENOUGH!!
I've never seen more than 24 myself, and designed
and checked? If so, where? I would rather not
submit 1 M files for review (Yes, Peter!! ;-)) - and (although I WILL do
this next time) perhaps a checklist of Is this the latest release - do
this first - may be helpful?
Thank you again for your advice and help!!
Tony Radice
P.S. Who CARES how
to include these shapes?
I would appreciate any guidance.
Thanks!
Tony Radice
trad...@ieee.org
OS: Fedora 11; updated with latest yum patches.
Machine: 32 Bit / 2GB Ram
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obviously do NOT want to have
voids. Is this a normal thing? (I have yet to check my gerbers...)
Cheers!
Tony Radice
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, and viola! - the
footprints come up correctly WITH the silkscreen around them.
SO, I will place all locally developed footprints into this directory.
Comments and questions are invited.
Tony Radice
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with this attribute
attached to a pin?
Valid pintypes are: unknown in out io oc oe pas tp tri
clk pwr unconnected
Regards,
Carlos
El jue, 17-09-2009 a las 19:17 -0400, Tony Radice escribió:
Ladies and Gentlemen -
When attempting to run a drc on my heirarchical design, the drc
unconnected
Regards,
Carlos
El jue, 17-09-2009 a las 19:17 -0400, Tony Radice escribió:
Ladies and Gentlemen -
When attempting to run a drc on my heirarchical design, the drc
routine crashes with the following error:
Backtrace:
In /usr/share/gEDA/scheme/gnet-drc2.scm
Ladies and Gents -
Looks like I may not hit every error possible, but I'm gonna give it
my best shot at as many as possible...
Latest dilemma: When I issue the netlist command with the argument
-g bom, I get a valid bom.
When I issue the netlist command with ANY other form of the
DJ -
Added the (debug-options (list 'stack 20)) command to my
system-gafrc file. Worked like a charm!!
THANK YOU!!!
Tony
On Wed, 2009-09-23 at 21:12 -0400, DJ Delorie wrote:
Try http://archives.seul.org/geda/user/Feb-2008/msg00277.html
(loaded with the pcb {filename}.pcb command) but the silk
screen courtyards put into the parts were not there.
Cheers!
Tony
On Wed, 2009-09-23 at 23:32 +0200, Stefan Salewski wrote:
On Wed, 2009-09-23 at 15:10 -0400, Tony Radice wrote:
Update:
Ladies and Gentlemen -
I experimented
]
ElementLine [ 24000 36000 -24000 36000 1000]
ElementLine [ -24000 36000 -24000 -36000 1000]
ElementLine [ -24000 -36000 24000 -36000 1000]
ElementLine [ 24000 -36000 24000 36000 1000]
)
My thanks for your assistance!!
Tony Radice
the 'pintype' attribute...
INTERNAL ERROR: unknown pin type : wr
Again, thank you for your consideration.
Tony Radice
BTW: Machine is running Fedora 11, 2 G Mem.
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it?
If this is already documented, please direct me to the documentation - -
With my thanks!
Tony Radice
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Ladies and Gentlemen -
I would like to know why a :0 is needed to prevent errors when
naming a net. What does the number after the colon signify?
Thank You.
Tony Radice
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