John Griessen wrote:
> This is probably a Mike Jarabek question:
>
Could be... Sorry for the delay, got swamped.
> I don't get usable hierarchic netlist output when I have placed schematics
> and use the gnet-verilog.scm back-end.
> It drops the module definitions and endmodule statements of th
Paul Tan wrote:
> Hi John,
>
> There is a BASH script "geda_hier_tools.bsh" to generate
> Hierarchical Verilog netlist
Thanks Paul,
I'm wanting to get things going in an easy to maintain way with as few steps
as possible. I'd like to do it in scheme, from one launch of gnetlist, if
possible.
(hierarchy-traversal "disabled")
This is needed, because Verilog needs a "non-flatten"
hierarchy. The example shows that.
Hope that helps
Best Regards,
Paul Tan
-Original Message-
From: John Griessen
To: gEDA user mailing list
Sent: Mon, 9 Feb 2009 1:22 pm
Subjec
This is probably a Mike Jarabek question:
I don't get usable hierarchic netlist output when I have placed schematics and
use the gnet-verilog.scm back-end.
It drops the module definitions and endmodule statements of the placed symbols
that refer to schematics.
So, is that the normal behavior, a
My goal is to do slot-level simulation, to use a gschem term.
I started with an existing schematic. After jumping thru several
hoops, I am still not there.
The library for common ttl components may be more difficult than it
first appears.
Maybe the better way to go is the verilog library... Ne
Hi,
On Sat, 2006-07-22 at 12:52 -0700, User Tomdean wrote:
> It looks like if I change all symbols to contain an attribute
> VERILOG_PORTS=POSITIONAL
> the pin number will be commented out.
Correct.
>
> I want to avoid having two symbols for everything.
>
I am a bit confused here. If you a
It looks like if I change all symbols to contain an attribute
VERILOG_PORTS=POSITIONAL
the pin number will be commented out.
I want to avoid having two symbols for everything.
I am looking into something to carry over positional from the top
level schematic.
tomdean
_
Hi,
On Sat, 2006-07-22 at 10:39 -0700, User Tomdean wrote:
> How do I cause 'gnetlist -g verilog' to pick up the pinlabel rather
> than the pin number for the module port name?
At the moment, no. The backend uses the pinnumber information as passed
directly from the gnetlist core. When I wrote
How do I cause 'gnetlist -g verilog' to pick up the pinlabel rather
than the pin number for the module port name?
Is there a doc that describes the flow in gnetlist?
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-b
Hi,
I assume you are talking about these messages (from an old version
of gschem / gnetlist, but the warning you are getting should be the
same, I have not updated the netlister since that time):
-
[EMAIL PROTECTED] tmp]$ gnetlist -g verilog -o test.v test.sch
gEDA/gnetlist version 2004
How do I generate verilog with gnetlist? I have a simple schematic
with a 7400 and a 7474, below.
I used gnetlist -g verilog -o test.vl test.sch. Gnetlist complains of
pin numbers not being valid identifiers.
I made symbols with pintype CHIPIN, CHIPOUT, etc., naming these
7400-vl.sym and 7474-v
11 matches
Mail list logo
