Some things have indeed been done. At the very least, you can
explicitly list in $dumpvars the array words that you want to
dump. The list needs to be explicit to prevent the explosion
of traces when you have large memories in your design.
Denis Daly wrote:
> Hi,
>
> I'm trying to simulate a Ver
Hi,
I'm trying to simulate a Verilog file with many multi-dimensional arrays.
e.g.
wire [31:0] bus[7:0];
It appears that these signals do not show up in the VCD file and thus can't be
viewed in GTKWave. This was confirmed back in 2001 by Steve Williams.
http://www.geda.seul.org/mailinglist/ged
Hello,
I am reviewing some Verilog code written by somebody else and run
through some other Verilog simulation tool, so I know this is a little
off topic, but I'm not sure where else to ask.
Anyway, I see code that looks like this:
reg [7:0] unit_matrix [12:0];
for (j = 0; j<8
Hello, Patrick,
I just starts re-targeting iverilog to some of our own FPGA fabrics. I
am still learning the iverilog codes. But, ff you are worrying about
generating netlist for your structure, iverilog has provided an
interface called ivl for you to manipulate logic gates and computing
units lik
Would somebody point me in the right direction for learning more about
synthesis with Icarus Verilog? I'm happy to read the source, but
synth.cc doesn't seem like the right place to start.
Specifically, I am curious to learn if anybody has used Icarus Verilog
to target a custom ASI
Günter Dannoritzer wrote:
> Jared Casper wrote:
>> On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer <[EMAIL PROTECTED]>
>> wrote:
>>> So with the latest development snapshot it gave me an assertion, but
>>> with the git version a segmentation fault.
>>>
>> I saw this behavior as well, so I don
Jared Casper wrote:
> On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer <[EMAIL PROTECTED]>
> wrote:
>> So with the latest development snapshot it gave me an assertion, but
>> with the git version a segmentation fault.
>>
>
> I saw this behavior as well, so I don't think it is your setup. Som
On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer <[EMAIL PROTECTED]> wrote:
> So with the latest development snapshot it gave me an assertion, but
> with the git version a segmentation fault.
>
I saw this behavior as well, so I don't think it is your setup. Something must
have changed in git
Stephen Williams wrote:
> Günter Dannoritzer wrote:
...
>>
>> How can I check that it works correct?
>
> It is just as likely that you found a bug that is segfaulting instead
> of tripping an assert. That is rare in Icarus Verilog because we're
> so liberal with assertions, but it does happen from
Günter Dannoritzer wrote:
> Hi,
>
> I tried to install Icarus Verilog from git and wonder whether I did
> something wrong, as when things go wrong it crashes with a segmentation
> fault.
>
> I have to say that I have the latest development snapshot installed in
> parallel in the standard path.
Hi,
I tried to install Icarus Verilog from git and wonder whether I did
something wrong, as when things go wrong it crashes with a segmentation
fault.
I have to say that I have the latest development snapshot installed in
parallel in the standard path.
So what I did with the git version is th
Darren Stevens wrote:
> Hello Stephen
> There are however a very large number of logic gate entries, AND2, AND2B1,
> AND2B2.. AND3 (up to 9 inputs IIRC) along with OR, NAND XOR etc..
>
> So I editied the EDF file and changed the LUT2 entry to AND2 - ngdbuild was
> quite happy with that. I even ma
Hello Stephen
On 25/03/08, Stephen Williams wrote:
> The -tfpga code generator for virtex is almost certainly trying
> to implement your gates with LUT2 devices. It uses an INIT= attribute
> attached to the LUT2 to specify the logic. That's pretty basic and
> should work.
>
> Looks like ngdbuild
Hello Stephen
On 25/03/08, Stephen Williams wrote:
>> Since the Xilinx free tools for this chip don't include a synthesis tool
>> I've been trying to use Iverilog, with some success.
>
> I'm surprised by that. I thought the webpack releases support
> spartan chips of various sort via xst. However
Darren Stevens wrote:
> Hello All,
>
> I've been trying to use a Digilent XLA development board fitted with a Xilinx
> spartan XCS10 fitted.
>
> Since the Xilinx free tools for this chip don't include a synthesis tool I've
> been trying to use Iverilog, with some success.
I'm surprised by that.
Hello All,
I've been trying to use a Digilent XLA development board fitted with a Xilinx
spartan XCS10 fitted.
Since the Xilinx free tools for this chip don't include a synthesis tool I've
been trying to use Iverilog, with some success.
This program can be compiled and converted to a bit file an
I recently found out (painfully) that an intuitive
and excellent feature of iverilog is nonstandard.
The OVI reference manual states:
The text specified for must not be split across the
following lexical tokens:
* comments
* numbers
* strings
* identifiers
This is relevant:
http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/
3bc899be1008b8e5/8c0086d88906db19#8c0086d88906db19
Hello.
Consider:
module A (input theInput, output theOutput);
parameter delay = 2;
// Do something
endmodule
module B (inpu
On 7 Apr 2007, at 7:18:42 PM, [EMAIL PROTECTED] wrote:
Hello,
I had a bunch of parameters that I was duplicating across modules,
so I decided to replace them with macro definitions in one file.
After creating this file and including it in my other files, I kept
getting
these errors:
Stuart Brorson wrote:
Can somebody confirm that Icarus supports/doesn't support the modulo
operator for reals? I'm very willing to believe that my problem has
to do with my head being wedged, but I just want to make sure that
Icarus supports the operation I want to perform.
Stuart
from
As the subject line says -- I am using Icarus Verilog 0.8.2. I am
getting bad results using the modulo operator for reals. Here's an
example:
// declaration of variables
real pos;
real foo;
// other stuff occurs before here. . .
foo = pos % 6300;
$display(pos, " ", foo);
For me,
That was it.
I renamed everything .v and now, it finds all the modules.
Thanks,
tomdean
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it looks like iverilog does not accept +define+.v from the command line,
but as it is the default, not a big issue.
[EMAIL PROTECTED] ~]$ iverilog -y lib test.v && ./a.out
out is 0 at 0
out is 1 at 25
out is 2 at 35
out is 3 at 45
perhaps your module file is not called module_name.v ??
jo
I tried the -y switch.
I have a directory ../modules with files like ver_7400 containing
module ver_7400(O,A,B);
...
endmodule
My source file contains ver_7400 U8 (...)
iverilog -y ../modules source.vl
complains
source.vl:54: error: Unknown module type: ver_7400
...
I tried
iveril
User Tomdean wrote:
Is this off topic?
How do I cause iverilog to pick up modules from files?
I tried '-I../modules'
if the module fred is in the file fred.v, then
add the directory path -y dirpath
and tell the tool the file suffix with +libext+.v
(for the .v extension ))
-I is for thing
Is this off topic?
How do I cause iverilog to pick up modules from files?
I tried '-I../modules'
I created a schematic with device equal to the verilog file containing the
module definition. For example,
in gschem,
device ver_7474
in the file,
../modules/ver_7474
module ver_747
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