gEDA-user: Request for VHDL and Hierarchical Spice References

I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting.

Re: gEDA-user: Request for VHDL and Hierarchical Spice References

On Wed, Nov 28, 2007 at 08:17:49AM -0800, Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext You want the LRMs. VHDL is IEEE standard 1076; Verilog is IEEE standard 1364. The correct way would be to purchase them from the IEEE. There may be copies (legal or

Re: gEDA-user: Request for VHDL and Hierarchical Spice References

On Wednesday 28 November 2007, Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that

Re: gEDA-user: Request for VHDL and Hierarchical Spice References

Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex

Re: gEDA-user: Request for VHDL and Hierarchical Spice References

Since I build a flat netlist for each sheet it should be fairly streight forward to build a hierarchical netlist thus I think it will just be a syntax issue for the various formats. As a side note: I have moved the reading of schematics from the c code to a guile script. I am in process of doing

Re: gEDA-user: Request for VHDL and Hierarchical Spice References

To be fair . The same circuit --- verilog-A -- // basic CMOS inverter with parameter passing (in, out, vdd, vss) module myinv (2 1 100 200); inout 2, 1, 100, 200; electrical 2, 1, 100, 200; parameter WP=30u, WN=10u; pfet #(.w(WP),