Re: [gem5-dev] workaround: "Ruby functional read failed" error

> BTW, in the scenario above, the functionalWrite will not work correctly, data > updated by functionalWrite in controllers will be replaced with old data from a > queued packet several ticks later. functionalWrite works well in this scenario, the "functional write failed" bug is already fixed. So

Re: [gem5-dev] bi-mode branch predictor miss prediction rate is high

A bug was recently found in the bimodal predictor. If you are still looking at this, you might want to try a new checkout. Hope this helps. On Wed, Jul 2, 2014 at 4:52 PM, Zi Yan via gem5-dev wrote: > I get 5 100-million-instruction simpoints for each benchmark in > SPEC CPU 2006 with *ref in

Re: [gem5-dev] Review Request 2372: style: add .clang-format file

> On Sept. 1, 2014, 6:14 p.m., Andreas Sandberg wrote: > > .clang-format, line 18 > > > > > > Has this changed name? The clang documentation lists > > DerivePointerAlignment, but not DerivePointerBinding. > > Nilay Vaish wr

[gem5-dev] changeset in gem5: stats: Update stats for CPU and cache changes

changeset 5f1f92bf76ee in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5f1f92bf76ee description: stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches. di

[gem5-dev] changeset in gem5: config: Add port splicing capability to PortR...

changeset 7565dcd505a4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7565dcd505a4 description: config: Add port splicing capability to PortRef class The new configuration scripts need the ability to splice a simobject between a pair of ports that are

[gem5-dev] changeset in gem5: dev: seperate legacy io offsets from PCI offset

changeset 1e2f39859382 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1e2f39859382 description: dev: seperate legacy io offsets from PCI offset The PC platform has a single IO range that is used both legacy IO and PCI IO while other platforms may use

[gem5-dev] changeset in gem5: base: Use STL C++11 random number generation

changeset 939094c17866 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=939094c17866 description: base: Use STL C++11 random number generation This patch changes the random number generator from the in-house Mersenne twister to an implementation relying

[gem5-dev] changeset in gem5: base: Use the global Mersenne twister throughout

changeset c91b23c72d5e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c91b23c72d5e description: base: Use the global Mersenne twister throughout This patch tidies up random number generation to ensure that it is done consistently throughout the code b

[gem5-dev] changeset in gem5: dev, arm: Add support for linux generic pci h...

changeset 198dfef33403 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=198dfef33403 description: dev, arm: Add support for linux generic pci host driver This change adds support for a generic pci host bus driver that has been included in recent Linux k

[gem5-dev] changeset in gem5: mem: write streaming support via WriteInvalid...

changeset b5bef3c8e070 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b5bef3c8e070 description: mem: write streaming support via WriteInvalidate promotion Support full-block writes directly rather than requiring RMW: * a cache line is allocated in th

[gem5-dev] changeset in gem5: arm: Support >2GB of memory for AArch64 systems

changeset 644b615fbe6a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=644b615fbe6a description: arm: Support >2GB of memory for AArch64 systems diffstat: configs/common/FSConfig.py | 27 +++ src/dev/arm/RealView.py| 9 + 2 fil

[gem5-dev] changeset in gem5: mem: Fix a bug in the cache port flow control

changeset fa9ef374075f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fa9ef374075f description: mem: Fix a bug in the cache port flow control This patch fixes a bug in the cache port where the retry flag was reset too early, allowing new requests to a

[gem5-dev] changeset in gem5: mem: Avoid unecessary retries when bus peer i...

changeset d548d1d7597c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d548d1d7597c description: mem: Avoid unecessary retries when bus peer is not ready This patch removes unecessary retries that happened when the bus layer itself was no longer busy,

[gem5-dev] changeset in gem5: arm: Assume we have a kernel that supports pc...

changeset 1aff1376921e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1aff1376921e description: arm: Assume we have a kernel that supports pci devices Change the default kernel for AArch64 and since it supports PCI devices remove the hack that made it

[gem5-dev] changeset in gem5: arm: Mark v7 cbz instructions as direct branches

changeset 5e424aa952c5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5e424aa952c5 description: arm: Mark v7 cbz instructions as direct branches v7 cbz/cbnz instructions were improperly marked as indirect branches. diffstat: src/arch/arm/isa/insts/branch.i

[gem5-dev] changeset in gem5: arm: Make memory ops work on 64bit/128-bit qu...

changeset d96b61d843b2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d96b61d843b2 description: arm: Make memory ops work on 64bit/128-bit quantities Multiple instructions assume only 32-bit load operations are available, this patch increases load siz

[gem5-dev] changeset in gem5: tests: Use medium dataset for perlbmk regress...

changeset ee383b8e4d3f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ee383b8e4d3f description: tests: Use medium dataset for perlbmk regressions This patch changes the perlbmk regression script from the large to the medium dataset to reduce the regre

[gem5-dev] changeset in gem5: cpu, mem: Make software prefetches non-blocking

changeset a1eea45928e6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a1eea45928e6 description: cpu, mem: Make software prefetches non-blocking Previously, they were treated so much like loads that they could stall at the head of the ROB. Now they ar

[gem5-dev] changeset in gem5: config: Refactor RealviewEMM to fit into new ...

changeset dfebd39c48a7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=dfebd39c48a7 description: config: Refactor RealviewEMM to fit into new config system This eliminates some default devices and adds in helper functions to connect the devices defined

[gem5-dev] changeset in gem5: cpu: Fix o3 quiesce fetch bug

changeset 1ba825974ee6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1ba825974ee6 description: cpu: Fix o3 quiesce fetch bug O3 is supposed to stop fetching instructions once a quiesce is encountered. However due to a bug, it would continue fetching

[gem5-dev] changeset in gem5: tests: Use O3_ARM_v7a config for full-system ...

changeset 60dddc0a6f78 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=60dddc0a6f78 description: tests: Use O3_ARM_v7a config for full-system ARM regressions This patch changes the CPU configuration used for the full-system ARM regressions to increase

[gem5-dev] changeset in gem5: config: Update Streamline scripts and configs

changeset 2d6d7a056a38 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=2d6d7a056a38 description: config: Update Streamline scripts and configs Updated the stat_config.ini files to reflect new structure. Moved to a more generic stat naming scheme that

[gem5-dev] changeset in gem5: alpha: Stop using 'inorder' and rely entirely...

changeset 35241e33c38f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=35241e33c38f description: alpha: Stop using 'inorder' and rely entirely on 'minor' This patch avoids building the 'inorder' CPU model for any permutation of ALPHA, and also removes

[gem5-dev] changeset in gem5: cpu: fix bimodal predictor to use correct glo...

changeset 1b627a6ddac0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1b627a6ddac0 description: cpu: fix bimodal predictor to use correct global history reg A small bug in the bimodal predictor caused significant degradation in performance on some ben

[gem5-dev] changeset in gem5: mem: Refactor assignment of Packet types

changeset 711eb0e64249 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=711eb0e64249 description: mem: Refactor assignment of Packet types Put the packet type swizzling (that is currently done in a lot of places) into a refineCommand() member function.

[gem5-dev] changeset in gem5: x86: Flag instructions that call suspend as I...

changeset 0b4d10f53c2d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0b4d10f53c2d description: x86: Flag instructions that call suspend as IsQuiesce The o3 cpu relies upon instructions that suspend a thread context being flagged as "IsQuiesce". If t

[gem5-dev] changeset in gem5: arm: ISA X31 destination register fix

changeset 85001c018d4c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=85001c018d4c description: arm: ISA X31 destination register fix This patch substituted the zero register for X31 used as a destination register. This prevents false dependencies ba

[gem5-dev] changeset in gem5: arm: use condition code registers for ARM ISA

changeset 8bee5f4edb92 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8bee5f4edb92 description: arm: use condition code registers for ARM ISA Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code t

[gem5-dev] changeset in gem5: cpu: Fix cache blocked load behavior in o3 cpu

changeset 6be8945d226b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6be8945d226b description: cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline

[gem5-dev] changeset in gem5: cpu: Fix o3 front-end pipeline interlock beha...

changeset 867b536a68be in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=867b536a68be description: cpu: Fix o3 front-end pipeline interlock behavior The o3 pipeline interlock/stall logic is incorrect. o3 unnecessicarily stalled fetch and decode due to

[gem5-dev] changeset in gem5: cpu: Fix o3 drain bug

changeset 40d24a672351 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=40d24a672351 description: cpu: Fix o3 drain bug For X86, the o3 CPU would get stuck with the commit stage not being drained if an interrupt arrived while drain was pending. isDraine

[gem5-dev] changeset in gem5: arm: Fix v8 neon latency issue for loads/stores

changeset 53278be85b40 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=53278be85b40 description: arm: Fix v8 neon latency issue for loads/stores Neon memory ops that operate on multiple registers currently have very poor performance because of interle

[gem5-dev] changeset in gem5: dev: Avoid invalid sized reads in PL390 with ...

changeset 72890a571a7b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=72890a571a7b description: dev: Avoid invalid sized reads in PL390 with DPRINTF enabled The first DPRINTF() in PL390::writeDistributor always read a uint32_t, though a packet may ha

[gem5-dev] changeset in gem5: arch: Properly guess OpClass from optional St...

changeset 43516d8eabe9 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=43516d8eabe9 description: arch: Properly guess OpClass from optional StaticInst flags isa_parser.py guesses the OpClass if none were given based upon the StaticInst flags. The exi

[gem5-dev] changeset in gem5: cpu: Fix SMT scheduling issue with the O3 cpu

changeset ed05298e8566 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ed05298e8566 description: cpu: Fix SMT scheduling issue with the O3 cpu The o3 cpu could attempt to schedule inactive threads under round-robin SMT mode. This is because i

[gem5-dev] changeset in gem5: cpu: Add a fetch queue to the o3 cpu

changeset 12e3be8203a5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=12e3be8203a5 description: cpu: Add a fetch queue to the o3 cpu This patch adds a fetch queue that sits between fetch and decode to the o3 cpu. This effectively decouples fetch from

[gem5-dev] changeset in gem5: cpu: Fix incorrect speculative branch predict...

changeset f54586c894e3 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f54586c894e3 description: cpu: Fix incorrect speculative branch predictor behavior When a branch mispredicted gem5 would squash all history after and including the mispredicted bra

[gem5-dev] changeset in gem5: mem: Add utility script to plot DRAM efficien...

changeset 5169ebd26163 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5169ebd26163 description: mem: Add utility script to plot DRAM efficiency sweep This patch adds basic functionality to quickly visualise the output from the DRAM efficiency script.

[gem5-dev] changeset in gem5: arm: support 16kb vm granules

changeset f40134eb3f85 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f40134eb3f85 description: arm: support 16kb vm granules diffstat: src/arch/arm/miscregs.hh | 26 - src/arch/arm/table_walker.cc | 125 +- sr

[gem5-dev] changeset in gem5: mem: Packet queue clean up

changeset 7f4059e4f2d5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7f4059e4f2d5 description: mem: Packet queue clean up No change in functionality, just a bit of tidying up. diffstat: src/mem/packet_queue.cc | 20 +++- src/mem/packet_qu

[gem5-dev] changeset in gem5: cpu: Change writeback modeling for outstandin...

changeset 5b6279635c49 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5b6279635c49 description: cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch

[gem5-dev] changeset in gem5: cache: Fix handling of LL/SC requests under c...

changeset 7aacec2a247d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7aacec2a247d description: cache: Fix handling of LL/SC requests under contention If a set of LL/SC requests contend on the same cache block we can get into a situation where CPUs wi

[gem5-dev] changeset in gem5: config: Change parsing of Addr so hex values ...

changeset 19f5df7ac6a1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=19f5df7ac6a1 description: config: Change parsing of Addr so hex values work from scripts When passed from a configuration script with a hexadecimal value (like "0x8000"), gem5 w

[gem5-dev] changeset in gem5: arch, cpu: Factor out the ExecContext into a ...

changeset 4207f9bfcceb in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4207f9bfcceb description: arch, cpu: Factor out the ExecContext into a proper base class We currently generate and compile one version of the ISA code per CPU model. This is obvious

[gem5-dev] changeset in gem5: sim: Fix checkpoint restore for Ticked

changeset 82a4fa2d19a0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=82a4fa2d19a0 description: sim: Fix checkpoint restore for Ticked This patch makes restoring the 'lastStopped' value for Ticked-containing objects (including MinorCPU) optional so th

[gem5-dev] changeset in gem5: arm: Fix ExtMachInst hash operator underlying...

changeset d2850235e31c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d2850235e31c description: arm: Fix ExtMachInst hash operator underlying type This patch fixes the hash operator used for ARM ExtMachInst, which incorrectly was still using uint32_t.

[gem5-dev] changeset in gem5: arch: Cleanup unused ISA traits constants

changeset 98771a936b61 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=98771a936b61 description: arch: Cleanup unused ISA traits constants This patch prunes unused values, and also unifies how the values are defined (not using an enum for ALPHA), align

Re: [gem5-dev] Ruby regression tests and null isa

Hi Nilay, That all sounds good. I am not adverse to the idea of including a ruby protocol in the NULL build, but I??d like it to be for a good reason as it does indeed add quite some time to the build. That??s all... Andreas On 03/09/2014 05:44, "Nilay Vaish" wrote: >On Mon, 1 Sep 2014, Andrea

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

Would someone be able to fry the build directory? Thanks, Andreas On 03/09/2014 08:11, "Cron Daemon via gem5-dev" wrote: >scons: *** [build/ALPHA/mem/ruby/structures/RubyMemoryControl.do] Error 1 >scons: *** [build/ALPHA/mem/protocol/DMARequestMsg.do] Error 1 >scons: *** [build/ALPHA/mem/proto

[gem5-dev] Cron /z/m5/regression/do-regression quick

scons: *** [build/ALPHA/mem/ruby/structures/RubyMemoryControl.do] Error 1 scons: *** [build/ALPHA/mem/protocol/DMARequestMsg.do] Error 1 scons: *** [build/ALPHA/mem/protocol/DMA_Controller.do] Error 1 scons: *** [build/ALPHA/mem/protocol/DMA_Transitions.do] Error 1 scons: *** [build/ALPHA/mem/proto