[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of jalr

2020-08-27 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/33155 ) Change subject: arch-riscv: Fix disassembling of jalr .. arch-riscv: Fix disassembling of jalr The 'jalr' instruction of

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix bug in getting branch target of jalr

2020-08-23 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/33234 ) Change subject: arch-riscv: Fix bug in getting branch target of jalr .. arch-riscv: Fix bug in getting branch

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of jalr

2020-08-21 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/33155 ) Change subject: arch-riscv: Fix disassembling of jalr .. arch-riscv: Fix disassembling of jalr The 'jalr'

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Add float registers in copyRegs

2020-08-20 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32934 ) Change subject: arch-riscv: Add float registers in copyRegs .. arch-riscv: Add float registers in copyRegs The origin

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Add float registers in copyRegs

2020-08-19 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32934 ) Change subject: arch-riscv: Add float registers in copyRegs .. arch-riscv: Add float registers in copyRegs The

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of CSR instructions

2020-08-18 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32814 ) Change subject: arch-riscv: Fix disassembling of CSR instructions .. arch-riscv: Fix disassembling of CSR instructions The

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of CSR instructions

2020-08-18 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32814 ) Change subject: arch-riscv: Fix disassembling of CSR instructions .. arch-riscv: Fix disassembling of CSR

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of all register instructions

2020-08-17 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32694 ) Change subject: arch-riscv: Fix disassembling of all register instructions .. arch-riscv: Fix disassembling of all register

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of all register instructions

2020-08-13 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32694 ) Change subject: arch-riscv: Fix disassembling of all register instructions .. arch-riscv: Fix disassembling of all

[gem5-dev] Change in gem5/gem5[develop]: sim: Add checkpoint parameters for VMA list

2020-08-06 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31875 ) Change subject: sim: Add checkpoint parameters for VMA list .. sim: Add checkpoint parameters for VMA list Add checkpoint

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of float register instructions

2020-07-31 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32054 ) Change subject: arch-riscv: Fix disassembling of float register instructions .. arch-riscv: Fix disassembling of float

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of float register instructions

2020-07-31 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32054 ) Change subject: arch-riscv: Fix disassembling of float register instructions .. arch-riscv: Fix disassembling of

[gem5-dev] Change in gem5/gem5[develop]: sim: Move checkpoint parameters for ptable into seperate section

2020-07-30 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31874 ) Change subject: sim: Move checkpoint parameters for ptable into seperate section .. sim: Move checkpoint parameters for

[gem5-dev] Change in gem5/gem5[develop]: sim: Add checkpoint parameters for VMA list

2020-07-28 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31875 ) Change subject: sim: Add checkpoint parameters for VMA list .. sim: Add checkpoint parameters for VMA list Add

[gem5-dev] Change in gem5/gem5[develop]: sim: Move checkpoint parameters for ptable into seperate section

2020-07-28 Thread Ian Jiang (Gerrit) via gem5-dev
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31874 ) Change subject: sim: Move checkpoint parameters for ptable into seperate section .. sim: Move checkpoint