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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
("int16_t", "int32_t"), 4, sqrdmlshCode,
byElem=True,
+ readDest=True, scalar=True, extra=rdm_check)
+# SQRDMLSH (vector)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshDX", "SimdMultOp",
+ (
rrit-Branch: develop
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Static(_data);
resp->senderState = _senderState;
_port.completeDataAccess(resp);
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),
+ pkt->req);
delete resp;
}
return
1);
+if (aarch32) {
+ uint32_t isar5 = tc->readMiscReg(MISCREG_ID_ISAR5);
+return bits(isar5, 27, 24) == 0x1;
+
+} else {
+AA64ISAR0 id_aa64isar0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
+return id_aa64isar0.rdm;
+}
+}
+
+bool
HavePACExt(ThreadContext *tc)
{
AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 636625d..5084e52 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -151,6 +151,7 @@
return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
}
+bool HaveQRDMLAHExt(ThreadContext * tc);
bool HavePACExt(ThreadContext *tc);
bool HaveVirtHostExt(ThreadContext *tc);
bool HaveSecureEL2Ext(ThreadContext *tc);
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Gerrit
veLVA(ThreadContext *tc);
bool HaveSecureEL2Ext(ThreadContext *tc);
bool IsSecureEL2Enabled(ThreadContext *tc);
bool EL2Enabled(ThreadContext *tc);
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alid phys. address range");
}
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VirtHostExt(ThreadContext *tc);
+bool HaveLVA(ThreadContext *tc);
bool HaveSecureEL2Ext(ThreadContext *tc);
bool IsSecureEL2Enabled(ThreadContext *tc);
bool EL2Enabled(ThreadContext *tc);
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
using AArch64.
known = true; aarch32 = false;
+} else if (secure && el == EL2) {
+known = true; aarch32 = false;
} else if (!ArmSystem::highestELIs64(tc)) {
// All ELs are using AArch32:
known = true; aarch32 = true;
+} else if (ArmSystem:
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/gem5/+/31694
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res0_2;
Bitfield<6> err;
Bitfield<5, 2> moe;
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ults.hh b/src/arch/arm/faults.hh
index 7a2f69e..b911136 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -406,6 +406,8 @@
public:
HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
+ bool routeToHyp(ThreadContext *tc) const override;
+bool routeToMonitor(Threa
bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-bool secEL2 = false;
-bool aarch32_at_el1 = (aarch32_below_el3
- || (have_el2
- && (secEL2 || !isSecureBelowEL3(tc))
- && hcr.rw == 0 && !(hcr.e2h && hcr.tge
-&& HaveVirtHostExt(tc;
+bool secEL2 = HaveSecureEL2Ext(tc) && scr.eel2;
+bool aarch32_at_el1 = (aarch32_below_el3 ||
+ (have_el2 && (secEL2 || !secure) &&
+hcr.rw == 0 && !(hcr.e2h && hcr.tge &&
+ HaveVirtHostExt(tc;
// Only know if EL0 using AArch32 from PSTATE
if (el == EL0 && !aarch32_at_el1) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 971306f..e1f123a 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -128,6 +128,8 @@
return !inUserMode(tc);
}
+bool isSecure(ThreadContext *tc);
+
bool isSecureBelowEL3(ThreadContext *tc);
bool inAArch64(ThreadContext *tc);
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int32_t _imm);
+bool routeToHyp(ThreadContext *tc) const override;
+ bool routeToMonitor(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t vectorCatchFlag() const override { return 0x; }
};
@@ -677,6 +679,8 @@
{
public:
IllegalInstSetStateFault();
+
+bool routeToHyp(ThreadContext *tc) const override;
};
/*
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lt;= EL1 && hcr.tge == 1;
}
SystemError::SystemError()
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%(
rc/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -693,6 +693,7 @@
EC_WATCHPOINT_LOWER_EL = 0x34,
EC_WATCHPOINT_CURR_EL = 0x35,
EC_SOFTWARE_BREAKPOINT = 0x38,
+ EC_VECTOR_CATCH = 0x3A,
EC_SOFTWARE_BREAKPO
648,6 +686,9 @@
EC_HW_BREAKPOINT = 0x30,
EC_HW_BREAKPOINT_LOWER_EL = 0x30,
EC_HW_BREAKPOINT_CURR_EL = 0x31,
+EC_SOFTWARE_STEP = 0x32,
+EC_SOFTWARE_STEP_LOWER_EL = 0x32,
+EC_SOFTWARE_STEP_CURR_EL = 0x33,
EC_WATCHPOINT
3dea555e82
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&& hcr.tge == 1;
}
SystemError::SystemError()
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h
+++ b/src/arch/arm/types.hh
@@ -712,6 +712,7 @@
EC_WATCHPOINT_LOWER_EL = 0x34,
EC_WATCHPOINT_CURR_EL = 0x35,
EC_SOFTWARE_BREAKPOINT = 0x38,
+EC_VECTOR_CATCH= 0x3A,
EC_SOFTWARE_BREAKPOINT_64 = 0x3C,
};
--
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= 0x30,
EC_HW_BREAKPOINT_LOWER_EL = 0x30,
EC_HW_BREAKPOINT_CURR_EL = 0x31,
+EC_SOFTWARE_STEP = 0x32,
+EC_SOFTWARE_STEP_LOWER_EL = 0x32,
+EC_SOFTWARE_STEP_CURR_EL = 0x33,
EC_WATCHPOINT = 0x34,
EC_WATCHPOINT_L
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VR13_EL1 },
+{ "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
+{ "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
{ "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 },
{ "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 },
{ "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 },
{ "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 },
+{ "dbgwcr4_el1", MISCREG_DBGWCR4_EL1 },
+{ "dbgwcr5_el1", MISCREG_DBGWCR5_EL1 },
+{ "dbgwcr6_el1", MISCREG_DBGWCR6_EL1 },
+{ "dbgwcr7_el1", MISCREG_DBGWCR7_EL1 },
+{ "dbgwcr8_el1", MISCREG_DBGWCR8_EL1 },
+{ "dbgwcr9_el1", MISCREG_DBGWCR9_EL1 },
+{ "dbgwcr10_el1", MISCREG_DBGWCR10_EL1 },
+{ "dbgwcr11_el1", MISCREG_DBGWCR11_EL1 },
+{ "dbgwcr12_el1", MISCREG_DBGWCR12_EL1 },
+{ "dbgwcr13_el1", MISCREG_DBGWCR13_EL1 },
+{ "dbgwcr14_el1", MISCREG_DBGWCR14_EL1 },
+{ "dbgwcr15_el1", MISCREG_DBGWCR15_EL1 },
{ "mdccsr_el0", MISCREG_MDCCSR_EL0 },
{ "mddtr_el0", MISCREG_MDDTR_EL0 },
{ "mddtrtx_el0", MISCREG_MDDTRTX_EL0 },
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 0dd3dac..3a5e741 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -648,6 +648,9 @@
EC_HW_BREAKPOINT = 0x30,
EC_HW_BREAKPOINT_LOWER_EL = 0x30,
EC_HW_BREAKPOINT_CURR_EL = 0x31,
+EC_WATCHPOINT = 0x34,
+EC_WATCHPOINT_LOWER_EL = 0x34,
+EC_WATCHPOINT_CURR_EL = 0x35,
EC_SOFTWARE_BREAKPOINT = 0x38,
EC_SOFTWARE_BREAKPOINT_64 = 0x3C,
};
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Change subject: arch-arm: Implementation of Hardware Breakpoint exception
..
arch-arm: Implementation of
"FcmlaQX", "SimdFloatMultAccOp",
+ floatTypes, 4, fcmla_vec, True, complex=True)
# CLS
clsCode = '''
unsigned count = 0;
diff --git a/src/arch/arm/isa/templates/neon.isa
b/src/arch/arm/isa/templates/neon.isa
index ee38c2b..39e
floatTypes, 4, fcmla_vec, True, complex=True)
# CLS
clsCode = '''
unsigned count = 0;
diff --git a/src/arch/arm/isa/templates/neon.isa
b/src/arch/arm/isa/templates/neon.isa
index ee38c2b..39e6d22 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/template
buildFixedCvtFpOp(isSigned, isDouble, isXReg)
+buildFpJsCvtFixedOp();
}};
let {{
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Change subject: arch-arm: This commit adds Pointer Authentication feature.
..
arch-arm: This commit adds
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Change subject: arch-arm: Implementation of Hardware Breakpoint exception
..
arch-arm: Implementation of
REG_DBGWVR10_EL1 },
+{ "dbgwvr11_el1", MISCREG_DBGWVR11_EL1 },
+{ "dbgwvr12_el1", MISCREG_DBGWVR12_EL1 },
+{ "dbgwvr13_el1", MISCREG_DBGWVR13_EL1 },
+{ "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
+{ "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
{ &quo
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ct BaseCacheParams;
/**
@@ -331,6 +332,9 @@
/** Prefetcher */
BasePrefetcher *prefetcher;
+/** Atomic Memory operation Policy **/
+BaseAmoPolicy *amoPolicy;
+
/** To probe when a cache hit occurs */
ProbePointArg *ppHit;
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Change subject: arch-arm: Added LD/ST atomic instruction family and SWP
instrs
..
arch-arm: Added LD/ST atomic
+}};
+
+
+def template AmoPairOpConstructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst,
+IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _base, _re
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MASKS = { 1: 0xFF,
2: 0x,
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