As the error message suggest you seem to have a packet that spans a cache
line boundary. Have you checked the address and/or size to make sure they
all are within a cache line?
Andreas
On 26/02/2015 21:15, "Sensen Hu - EWI via gem5-dev"
wrote:
>hi, Andreas.
>I've tried to set Maxtick more than
hi, Andreas.
I've tried to set Maxtick more than 16000. But in the command window, it shows
Aborted (core dumped).
And the simerr file shows:
gem5.opt: build/ARM/mem/cache/cache_impl.hh:164: void
Cache::satisfyCpuSideRequest(PacketPtr, Cache::BlkType*,
bool, bool) [with TagStore = LRU; PacketP
Could it not be as simple as back pressure?
The traffic generator can only send requests as fast as the port (crossbar
in this case), can accept them.
I suspect if you set the max time to some larger value it is all fine.
Andreas
On 26/02/2015 08:04, "Sensen Hu - EWI via gem5-dev"
wrote:
>tha
thanks, Erfan.
I see. But my TraceGen can't still traverse the whole tgen-simple-mem.trc file,
while it only executes the first 4 instructions. Then it stops. I check the
following simout file, shows that:
Global frequency set at 1 ticks per second
info: Entering event queue @ 0. St
Dear Sensen,
If you take a look at *src/sim/ClockedObject.py*, you can see that the
parameter *clk_domain* is by default inherited from the parent. This means
that:
For all classes which are inherited from the ClockedObject class (including
CPU, memories, ...), if you do not specify any value for
hi, Andreas.
Thanks for your help.
I followed your advise to delete the test.py file and just set maxtick directly
in run.py.
But I failed again. Could you tell me the relationship among these parameters
cpu_clk_domain, system.cpu_clk_domain
STATE 0 100 TRACE tests/quick/se/70.tgen/tgen-simpl
Hi,
I would suggest to rather make a self-contained script and not rely on
test.py. That way it is easier to get a global picture of what you are
actually doing.
I suspect something is going wrong in how you are launching the simulator.
Andreas
On 23/02/2015 16:47, "Sensen Hu - EWI via gem5-dev
Hi Sensen,
In python you should be careful about indentation, because whitespaces are
significant in this language. This means that all lines in the same block
must start at the same indentation.
Here is an example
if A == 2:
expr1;
expr2;
expr3; > This is incorrect
There is on
发件人: Sensen Hu - EWI
发送时间: 2015年2月22日 14:06
收件人: gem5-dev@gem5.org
主题: how can I add cache in tgen-simple-mem
hi, all
I got a memory reference trace file from Pin-tools. Now I want to work out
cache miss rate from the file.
I use GEM5's trafficgen (TraceGen) and
