[gem5-users] Re: How to create two memory object in SE mode

Hi, What is the address organization between DRAM and PM? If applications want to allocate 1G DRAM and 1G PM, is there any hint for the memory allocator function?___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-use

[gem5-users] Re: 2 level TLB in ARM Full System with Ruby

Hi Ciro, Thanks for your reply! I don't remember seeing this patch before. I will check it out. The reason I specified RUBY is that one solution I found posted used a cache as a second level TLB and modified the port connections accordingly. However, that was a cache from the classical system and

[gem5-users] Re: question about cache organization

Hello Sourjya, First of all, welcome! gem5 is very versatile, and there is an infinitude of things you can do with it. The first thing you will need to decide is whether you are going to use the Classic Cache (https://www.gem5.org/documentation/general_docs/memory_system/classic_caches/) or

[gem5-users] Re: Running a program on GEM5 for specific number of instructions

If you are talking about the SE mode, you can use the se.py. The fast forward option and max instruction option will be helpful. On Wed, Jul 8, 2020 at 2:28 PM ABD ALRHMAN ABO ALKHEEL via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > I want to run a program for 100k instructions but I wa

[gem5-users] Running a program on GEM5 for specific number of instructions

Hi All, I want to run a program for 100k instructions but I want to skip the first 50k instructions? How can i do this? Any help would be appreciated. Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-

[gem5-users] gem5-20 paper on arXiv

Hi everyone! I'm excited to announce that we've published a new gem5 paper! Right now, it's available on arXiv at this URL: https://arxiv.org/abs/2007.03152 I tried to reach out to everyone who has been involved in gem5 development since its inception in 2011. However, I'm certain to have missed

[gem5-users] ARM full-system simulation error during checkpoint: rcu_preempt detected stalls on CPUs/tasks

Hi, I am currently running a 32-bit ARM full-system simulation. After I boot up the OS on the simulated system, I take a checkpoint. This worked fine before, but after I made some changes to the DRAM controller code, the checkpoint stalls and I get this error message in the simulated console: IN

[gem5-users] question about cache organization

Hi I am very new to gem5. I wanted to know if there is tutorial on changing cache data mapping or cache organization(eg If I want to change sram with any other device technology for a L2 cache) . Also I wanted to know if I can change the cache policies and data mapping inside caches. Regards

[gem5-users] Re: How to track the register values of instructions.

Hi Yuan, To be honest, I'm unfamiliar with those functions. I would consult the source code for more information. Additionally, in gdb, you can just call any function :). Cheers, Jason On Tue, Jul 7, 2020 at 4:05 PM Shougang Yuan wrote: > Hi, Prof.Jason, > > Thanks for your detailed reply. I f

[gem5-users] Re: How to create two memory object in SE mode

Hi May, This is definitely possible, and it's enabled by these recent changesets: https://gem5-review.googlesource.com/c/public/gem5/+/29027 They haven't been merged, yet, but I'm hopeful they'll be merged soon. Feel free to download them from gerrit and apply them locally :). You should see a do

[gem5-users] Re: 2 level TLB in ARM Full System with Ruby

Shehab, sorry for the delay, I had to check a few things about this, First, are you aware that there is a not-yet-merged patch that implements a two level TLB at: https://github.com/giactra/gem5/commit/3022ecc8a06a9182b2cf1936941901a785c1b21d ? It hasn't been merged because we noticed that it

[gem5-users] Re: How to check ...

It's a regular inorder 5 stage pipeline model designed to mimic the microarchitectural states of actual C-class processor mentioned here. https://gitlab.com/shaktiproject/cores/c-class Has fetch, decode(modified), execute, memaccess, writeback connected through pipe like structures containing FIF

[gem5-users] How to create two memory object in SE mode

Hi, I want to create two memory object, one is persistent memory and the other is DRAM. They are both connected to memory bus. Is there any method to achieve this in SE mode? Thanks, may___ gem5-users mailing list -- gem5-users@gem5.org To unsubscrib

[gem5-users] Re: What is miscellaneous register

Also, in ARM more specifically, you can see miscregs at https://github.com/gem5/gem5/blob/cc3e12b504c20b3bc78db52059d3f4f9b02dfbe8/src/arch/arm/miscregs.hh#L56 Most are what the ARM manuals call "System Registers", but a few others are just convenient ways to implement other ISA features like e.g.