Hello,
I build binary of gem5.opt firstly output at build/RISCV/gem5.opt, then I build
another binary of gem5.debug, but seems it's still at build/RISCV dir, looks
like all the build outputs shares same directories.
Even though I ran both with my workloads an they all worked properly, I'm
On 3/9/2023 5:44 PM, Ayaz Akram wrote:
Hi Eliot,
gem5 splits the memory system modeling into two parts: 1) the memory controller and 2) the memory
interface. The memory interface can be a DRAMInterface or NVMInterface and provides many parameters
that are configured to achieve a specific
On 3/9/2023 6:45 PM, Mirco Mannino via gem5-users wrote:
Hi all,
I'm trying to take checkpoints from SimPoints for SPEC CPU 2017 in SE mode. I would like to generate
checkpoints for different ISAs (RISCV and X86).
So far, I did the following:
1) BBV files created using "qpoints" tool
Hi all,
I'm trying to take checkpoints from SimPoints for SPEC CPU 2017 in SE
mode. I would like to generate checkpoints for different ISAs (RISCV and
X86).
So far, I did the following:
1) BBV files created using "qpoints" tool
(https://github.com/pranith/qpoints), since
Hi Eliot,
gem5 splits the memory system modeling into two parts: 1) the memory
controller and 2) the memory interface. The memory interface can be a
DRAMInterface or NVMInterface and provides many parameters that are
configured to achieve a specific memory device model (e.g., DDR4, GDDR5).
The
On 3/9/2023 3:01 PM, Eliot Moss via gem5-users wrote:
Dear gem5'ers - In my current simulation work it would be helpful to
understand better DRAM and NVM configuration. How do I determine, and how do
I set, the number of channels, interleaving, etc.? I'm far from being an
expert in memory
Hi Karim
Sorry for the chain emails, but I just realised that I mixed up x1 != x2
and x1 == x2 in my explanation. So please keep that in mind while
interpreting my explanation. You can mail me if you are still confused. You
can refer to https://youtube.com/playlist?list=PL8EC1756A7B1764F6
Dear gem5'ers - In my current simulation work it would be helpful to
understand better DRAM and NVM configuration. How do I determine, and how do
I set, the number of channels, interleaving, etc.? I'm far from being an
expert in memory devices / boards, so something that starts more from
Hi Karim,
I'm not very familiar with the Mesh_XY topology, but here is my attempt to
explain this.
I think the layout of the topology looks like this,
2 (0,1) <-> 3 (1,1)
^ ^
| |
v v
0 (0,0) <-> 1 (1,0)
It's straightforward to send a packet
Know any resources for “the anatomy of an ELFie”? Alongside the anatomy of a
Gem5 Checkpoint. That way I can possibly write something similar to pinball2elf
but for gem5 -> ELFie…
From: Jason Lowe-Power
Date: Thursday, March 9, 2023 at 9:56 AM
To: Jonathan Kang
Cc: Giacomo Travaglini , The
Yes, that's correct.
Cheers,
Jason
On Thu, Mar 9, 2023 at 9:44 AM Jonathan Kang wrote:
> I think I’d want the opposite: to get ELFies out of Gem5 CheckPoints.
> That’ll allow me to run it on an ARM Cycle Model.
>
>
>
> From the links you sent, it’s still Pin based and the resulting ELFies are
I think I’d want the opposite: to get ELFies out of Gem5 CheckPoints. That’ll
allow me to run it on an ARM Cycle Model.
From the links you sent, it’s still Pin based and the resulting ELFies are x86
right? I’d want to do this for ARM.
From: Jason Lowe-Power
Date: Thursday, March 9, 2023 at
Hi Jonathan,
We just did a tutorial on how to use ELFies with gem5. See
https://looppoint.github.io/hpca2023/ for details.
We are able to load ELFies and run them in gem5. See
https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py
for an example.
That said, we
Hi Jonathan,
On 08/03/2023 17:47, Jonathan Kang wrote:
Thanks Giacomo,
A few questions:
1. Who is Jason? So that I can contact him
Jason Lowe-Power, here CCed
1. Regarding ELFie, I found these:
*
https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
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