[gem5-users] Re: Running pthread in gem5 se mode

Am I missing something? Or am I building it wrong? >> ANy suggestions would be greatly appreciated. >> >> On Mon, Jul 26, 2021 at 2:03 AM Hossein Golestani >> wrote: >> >>> [I'm resending my reply without the attachments in case they caused it >>> to

[gem5-users] Re: Running pthread in gem5 se mode

t, Jul 24, 2021 at 10:28 PM Hossein Golestani > wrote: > >> Hi Krishnan, >> >> I use m5threads, which is a light-weight alternative for pthread, to >> simulate multi-threaded programs in the SE mode: >> https://github.com/gem5/m5threads >> (I

[gem5-users] Re: Running pthread in gem5 se mode

Hi Krishnan, I use m5threads, which is a light-weight alternative for pthread, to simulate multi-threaded programs in the SE mode: https://github.com/gem5/m5threads (I'm not sure if there are any other ways.) Thanks, Hossein On Sat, Jul 24, 2021 at 11:00 AM krishnan gosakan via gem5-users <

[gem5-users] Re: Prefetcher Configurations Issue

Hi Shawn, As for the error you got, I think TaggedPrefetcher should be properly imported in that script. You could also simply enable the prefetcher in the SE mode by adding the following to se.py (or similarly, in any other configuration script you are using): system.cpu[0].dcache.prefetcher =

[gem5-users] Re: memory instructions detected as branch: O3CPU SE MODE

Hi Francisco, I encountered the same issue a while back (look here ). It seems that at the O3 fetch stage, all RISC-V compressed instructions are treated as branches. A dirty solution that worked for me was adding the following if

Re: [gem5-users] RISC-V non-branch instructions detected as a branch

. I'm going to make my RISC-V compiler not generate compressed instruction as a temporary work-around. But I'd appreciate it if someone could help to solve this problem. Thanks, Hossein On Tue, Feb 25, 2020 at 12:48 PM Hossein Golestani wrote: > Hello everyone, > > I'm facing an iss

[gem5-users] RISC-V non-branch instructions detected as a branch

Hello everyone, I'm facing an issue regarding using the RISC-V ISA with the DerivO3CPU model. Apparently, some RISC-V instructions are incorrectly detected as a branch. Here's a piece of debugging output: 5682918000: system.switch_cpus.fetch: [tid:0] Instruction PC 0x10586 (0) created [sn:1].

Re: [gem5-users] gem5 stable release proposal [PLEASE VOTE!]

Hi Jason, I think master should be stable. I think gem5 should be released three times per year. Thanks, Hossein On Mon, Dec 16, 2019 at 2:51 PM Jason Lowe-Power wrote: > Hi all, > > As many of you have seen on gem5-dev, we are going to be adding a > "stable" version of gem5. Below is the

Re: [gem5-users] x86 O3 SMT: Int port not connected to anything

5-users@gem5.org/msg04271.html It seems that a patch was suggested for it. Since this zero register issue still persists, I wonder if it has been reviewed/applied. Thanks, Hossein On Wed, Oct 30, 2019 at 3:42 PM Hossein Golestani wrote: > Hello, > > When I use an O3 SMT core with the x8

[gem5-users] x86 O3 SMT: Int port not connected to anything

Hello, When I use an O3 SMT core with the x86 ISA in gem5 SE mode, I get the following error: panic: panic condition !intMasterPort.isConnected() occurred: Int port not connected to anything! The command I'm using is: $GEM5/build/X86/gem5.opt $GEM5/configs/example/se.py --cmd="./test;./test"

Re: [gem5-users] RISC-V DerivO3CPU: Assertion `atomicOpFunctor != NULL' failed

getFlags() > Ideally I'd like to respond to the thread you've posted on the mailing list but I don't know if I am able to do it. Thanks, Ataberk On Thu, Jun 13, 2019 at 12:28 PM Hossein Golestani wrote: > Hi, > > I'm using gem5 for simulation of cross-compiled RISC-V programs. >

[gem5-users] RISC-V DerivO3CPU: Assertion `atomicOpFunctor != NULL' failed

Hi, I'm using gem5 for simulation of cross-compiled RISC-V programs. I receive the following error when using the DerivO3CPU model: gem5.opt: build/RISCV/mem/request.hh:678: AtomicOpFunctor* Request::getAtomicOpFunctor(): Assertion `atomicOpFunctor != NULL' failed. I have used this command:

Re: [gem5-users] Android boot problem with workload automation

(ret_from_fork+0x14/0x3c) ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) Can you help on this problem? Regards, Hossein On Tue, Nov 22, 2016 at 5:52 PM, Hossein Golestani <hosse...@umich.edu> wrote: > Dear gem5 maintainers, > > I'm havin

[gem5-users] Android boot problem with workload automation

or message: fatal: Unable to find destination for addr 0x1c03 on system.iobus @ tick 101175788500 [findPort:build/ARM/mem/xbar.cc, line 358] I've spent so much time to reach this point because the gem5 documentation for Android and ARM WA is not clear enough. I'd appreciate it if you help me on this issue. Regards, Hossein Golestani ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users