stack range.
Hope this helps?
Jack
Jack Harvard
On Mon, Jan 26, 2015 at 4:25 PM, Leonardo Ecco via gem5-users
wrote:
> I'm currently struggling to trace accesses to the software stack that
> are not found in the cache (and, therefore, must be forwarded to the
> DRAM).
> By stack I
Steve,
A further question on TLB walker caches, they don't get any writes,
but they they have writebacks, which are only for evicted dirty lines
or uncached writes? It's ARM FS mode running BBench.
Jack Harvard
On Tue, Oct 7, 2014 at 9:22 PM, Steve Reinhardt via gem5-users
wrote:
&g
I ran m5threads/tests/test___thread and a few others in the tests
folder, they all had the same page fault panic (I side), it's an BLX
instruction caused the page table panic.
Jack Harvard
On Fri, May 30, 2014 at 6:50 PM, Ali Saidi wrote:
> What test are you running?
>
>
>
To add, x86 SE runs fine
Jack Harvard
On Fri, May 30, 2014 at 4:21 PM, Jack Harvard wrote:
> Did the same as this
> http://lacasa.uah.edu/portal/Upload/tutorials/gem5/RunningPrograms-gem5.txt,
> the run now says "panic: Page table fault when accessing virtual
> address 0xf00
s the same?
Jack Harvard
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
debug flags in gem5, and also insert printfs in your
kernel code, to help with your kernel boot debug.
Jack
Jack Harvard
On Tue, May 6, 2014 at 7:31 AM, luming via gem5-users
wrote:
> Dear gem5 users,
>
> I have been stuck on a kernel too old problem when running PARSEC3.0. The
>
Or, I believe you can add some accounting logic to figure out the
number of major and minor page faults, if not relying on the OS
(http://lxr.free-electrons.com/source/arch/arm64/mm/fault.c).
-Jack
Jack Harvard
On Thu, May 1, 2014 at 5:19 AM, Ali Saidi wrote:
> You’ll need to use FS mode
Hi V,
I don't know for sure, but have you checked the CloneFunc here
(http://grok.gem5.org/source/xref/gem5/src/sim/syscall_emul.cc#cloneFunc),
clone SysCall gets called when pthreads create a new thread and run on
another available core.
Jack
Jack Harvard
On Tue, May 6, 2014 at 9:
Hi Yuejia,
Which architecture are you targeting?
Jack
Jack Harvard
On Sun, May 4, 2014 at 12:06 PM, 陈越佳 via gem5-users wrote:
> Hi Jack.
> I load the symbol table, but I find the address is 64bit. And when I use gdb
> to print out the data at the 64-bit address. It print out error.
Note the classic cache model is PIPT, further to my comments above.
Jack Harvard
On Mon, Apr 28, 2014 at 5:51 PM, Jack Harvard wrote:
> You probably need to check the virtual address, rather than physical.
>
> Jack Harvard
>
>
> On Thu, Apr 24, 2014 at 5:13 AM, anonymo
You probably need to check the virtual address, rather than physical.
Jack Harvard
On Thu, Apr 24, 2014 at 5:13 AM, anonymous wrote:
> Hi,
>
> I have a question about cache block locations.
>
> I have a C struct with 2 integer members
>
> I have an array of these structs.
Probably something you will need to fix if you change the cache line size
away from 64 bytes, would be great if you could post back the patch to fix
the issue.
Thanks,
Jack
Jack Harvard
On Fri, Apr 25, 2014 at 8:06 PM, Chetan Patil wrote:
> Hi,
>
> I am trying to simulate X86 wit
viewing data in memory, there's no memory visualisation tool available,
but you can use printf to get a glimpse or use gdb to inspect memory
content.
Thanks,
Jack
Jack Harvard
On Fri, Apr 25, 2014 at 8:14 AM, 陈越佳 wrote:
> hi， All.
>I am a newer of using gem5. And I want to
It can be a significant effort to correlate a set of gem5 configurations to
a specific target, the following work did for a A-15 based platform,
http://web.eecs.umich.edu/~atgutier/papers/ispass_2014.pdf
Jack
Jack Harvard
On Mon, Mar 24, 2014 at 11:14 AM, Stian Hvatum wrote:
> Hi,
>
http://stackoverflow.com/questions/21556051/how-to-use-aarch64-linux-gnu-objdump-to-disassemble-v7-mode-instructions-a32-t3should
help
Jack Harvard
On Wed, Mar 19, 2014 at 2:41 PM, Yuchen Hou wrote:
> Hi Fernando,
> Thank you for your help. I will check rand(). When you sai
Also, there's readfile gem5 microop,
- readfile: Print the file specified by the config parameter
system.readfile. This is how the the rcS files are copied into the
simulation environment.
You may want to implement writefile to get files out though
Jack Harvard
On Wed, Feb 19,
You can use adb to get files in/out of the simulated Android filesystem,
push/pull to transfer files between simulated OS and host
ADB commands can be found here
http://developer.android.com/tools/help/adb.html
Jack Harvard
On Tue, Feb 11, 2014 at 8:52 PM, Peng Wei wrote:
> Hi,
>
&
Would be nice if you could update the wiki page too
Jack Harvard
On Mon, Feb 10, 2014 at 5:11 PM, Martin Brown wrote:
> *Now, to build the 2.6.35 kernel.*
>
>1. Get the kernel source: git clone
>git://linux-arm.org/linux-2.6-armdroid.git -b 2.6.35-armdroid
>2.
).
Jack
Jack Harvard
On Wed, Feb 5, 2014 at 10:16 PM, Walters, Dan wrote:
>
>
> What is the recommended way to attach a remote GDB to Gem5 in order to
> debug the program being run in simulation, particularly when the simulated
> program finishes execution very quickly?
>
>
org/source/xref/gem5/src/cpu/simple_thread.cc>
Line
84~90.
Jack
Jack Harvard
On Tue, Jan 14, 2014 at 10:32 AM, Jack Harvard wrote:
> Hi Fateme,
>
> gem5.perf is for benchmarking gem5 simulator itself, i.e., which functions
> are being called most in the simulator etc, not the wo
iling is supported though,
others have done kernel profiling.
Jack
Jack Harvard
On Tue, Dec 24, 2013 at 11:46 AM, Fateme Movafagh wrote:
> Hi :)
> I should profile and find out the hot spot of my workloads to continue my
> work. For instance, I want to determine which parts of my wo
I don't have a direct answer, but I would think the scheduling of threads is
done by the Kernel, not gem5. However I think it should not be impossible if
you want to write a patch which instruct gem5 to manually move a thread from
one core to the other, as gem5 should have the thread context inf
There's a patch to display stats in DS-5 Streamline, which can display per
thread stats, that'll get what you need. Just search for "gem5 streamline"
On 21 Jun 2013, at 15:56, Konstantinos Parasyris wrote:
> Hello,
>
> I am wondering if there is a patch for displaying statistics for a specific
Why not has a try "Download AndEBench apk" into Google?
Jack Harvard
On Tue, Feb 19, 2013 at 6:16 PM, Anthony Gutierrez wrote:
> Google's user agreement dictates that APKs from the play store can only be
> downloaded to approved Android devices; this does not include dev
Did you manage to run AndEBench? You can install the app in the Android
image and then run it on gem5.
Jack Harvard
On Thu, Sep 27, 2012 at 3:25 PM, Fangfei Liu wrote:
> Hi,
>
> ** **
>
> I tried to run Bbench on gem5 with Gingerbread disk image (atomic mode and
> def
As somebody on the list said, you can isolate the 11 pages into 11 parallel
runs on your cluster. You need to configure the javascript file that iterates
through the pages.
On 23 Jan 2013, at 15:57, Si Chen wrote:
> Hi,
>
> Bbench takes about 150 hours to finish one single iteration on a clust
Can you post the /data/anr/traces.txt and /data/tombstones/tombstones files
if they exist?
Jack Harvard
On Wed, Jan 23, 2013 at 11:20 AM, Jack Harvard wrote:
> Looks the pipe created by mkfifo() is broken
>
> Jack Harvard
>
>
> On Tue, Jan 22, 2013 at 2:24 AM, huangyongbing
Looks the pipe created by mkfifo() is broken
Jack Harvard
On Tue, Jan 22, 2013 at 2:24 AM, huangyongbing wrote:
> Hi,
>
> ** **
>
> The last logcat information related to browser are shown below.
> And all the information printed out by logcat are stored
It's cycle approximate
On 24 Nov 2012, at 09:32, Frank Yang wrote:
> Hi All,
>
> I am trying to dig into Gem5 but I found it's fairly complicated. Can someone
> give me any hint on how gem5 bring the concept of timing into those CPU
> models? I can understand that each instruction is divided
Why not, just put a bus in between CPUs and L1? But why would you do so?
Jack Harvard
On Fri, Nov 23, 2012 at 4:06 PM, Pavlos Maniotis wrote:
> Thanks Andreas,
>
> I would like to ask you one more thing:
> Do you believe it is feasible to simulate
> a system with L1 shared c
The error could happen due to the following reasons (by looking at
http://grok.gem5.org/source/xref/gem5/src/base/loader/object_file.cc#createObjectFile)
1) user pmokri has no read permission of the file boot.arm
2) file not in the format Ecoff, Aout, Elf
3) mmap failed which is unlikely
On 16 N
It's possible to run simpoint on any architecture, there's no reason
it should be architecture-dependent.
Jack Harvard
On Wed, Jun 20, 2012 at 10:43 PM, Jee Ho Ryoo wrote:
> Hi,
>
> In the ASPLOS tutorial, it says that the simpoint is only implemented in
> alpha. Has ther
Hi,
Why a ring buffer [implemented in an array as in C/C++] with one
producer thread and one consumer thread will not meet your
requirement?
Jack
On Wed, Jun 20, 2012 at 5:27 AM, vishal rawtiya wrote:
> Hello!
>
> I am a beginner at gem5, so forgive me for any ignorance. I want to
> test
Your question is not specific enough, bare-metal or OS, X86 or ARM
architecture, for example, ARM provides a register indicating the
Stack Pointer (r13). In Linux, you can cat /proc/pid/maps to get per
process info on stack and heap.
Jack Harvard
On Wed, Jun 13, 2012 at 5:01 PM, Simon Garcia
X86 does say com_1, my mistake. You probably need to use m5term,
rather than telnet.
Jack Harvard
On Wed, Jun 13, 2012 at 9:25 AM, Jack Harvard wrote:
> I notice something unusual in your log
>
> "Listening for com_1 connection on port 3458"
>
> usually it says "L
nd('.') - 1;
148 p1 = name().rfind('.', p2);
149 ccprintf(cerr, "Listening for %s connection on port %d\n",
150 name().substr(p1+1,p2-p1), port);
It seems your port 3458 is engaged with something else, com_1 sounds
like a serial port.
Jack H
Seems you're using a slightly old version of the code base, as I wouldn't
expect to see ARM_FS any more.
On 12 Jun 2012, at 22:32, Ira Ray Jenkins wrote:
> Since I can't see the terminal output, my assumption is that everything is
> running fine. The warnings and such are all expected/known. On
No.
On 8 Jun 2012, at 12:16, GE ZHIGUO wrote:
> Hi, All,
>I would like to run multi-instance of full system simulation of GEM5.
> Is there any interferences as the multi-instance need to use the same linux
> image file?
>
> Thanks!
>
> ___
> gem
You wouldn't expect the O3CPU and Timing/Atomic to have exactly the same cache
miss rate, for example, when the branch prediction is turned on in the O3 CPU,
the i cache miss rate won't be the same, when it's out of order execution the d
cache miss rate won't be the same. For timing and atomic d
Which version did you use? Try on a latest version of gdb.
Jack Harvard
On Thu, Mar 8, 2012 at 3:21 PM, Samuel Hitz wrote:
> Hi,
>
> I'm trying to remote debug an ARM kernel on gem5. However as soon as I
> attach the remote debugger I get:
>
> (gdb) target remote
The warning message is due to not using "--debug-flags", as you used
"--trace-flags". You can just run one of the two commands being
generated, and see what happens, just to make sure all the options are
correctly applied.
Jack Harvard
On Wed, Feb 15, 2012 at 10:14 AM, Ma
Tracediff is a small perl script, ./util/tracediff, have a look at the
file directly, that should answer your question.
Jack Harvard
On Tue, Feb 14, 2012 at 3:10 PM, Mahmood Naderan wrote:
> Hi
> How can I use tracediff? The document at
> http://gem5.org/Debugging#tracediff is not v
This is a known issue, the same as another thread "checkpointing issue".
Jack Harvard
On Tue, Feb 7, 2012 at 9:03 PM, Rio Xiangyu Dong wrote:
> Hi all,
>
>
>
> After checking out the latest gem5 repo (repo 8818), I got running errors
> when there is a cpu mode switc
You may want to use configs/common/O3_ARM_v7a.py for A15 like config.
Not sure there's an AMBA4 like model.
Jack Harvard
2012/2/7 김명진 :
> With using Gem5 simulator, I have some questions about supported CPU & BUS
> architecture.
>
> Here is my question.
>
> Does Gem
Would expect that to be bytes.
Jack Harvard
On Wed, Jan 25, 2012 at 7:20 PM, Mahmood Naderan wrote:
> Hi
> What is the unit of bus width?
>
> bus_width = Param.Int(8, "")
>
> Is it bits or bytes?
> --
> // Naderan *Mahmood;
> ___
Why you would want to change the number of cache ports? Would expect
one port on the CPU side and one port on the MEM side. See
src/mem/cache/base.hh
Jack Harvard
On Wed, Jan 25, 2012 at 6:51 AM, Mahmood Naderan wrote:
> Hi,
> Is it possible to change the number of cache ports? I can no
->getITBPtr()->invalidateMiscReg();
Jack Harvard
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
On Tue, Jun 14, 2011 at 4:18 PM, Dawei Wang wrote:
> Hello, everyone
> Now I am using M5 to simulate 4-core CPU. When I saw the stats.txt reports,
> here are some questions showing below.
> 1. For some L2 statistic parameters, there are 5 or 6 different values, for
> example
> system.l2.occ_blocks
That's the total number of cache misses per thread. Be very careful,
that the total cache miss rate number is wrong in current source tree,
as it just adds up the miss rate for each thread.
Jack Harvard
On Wed, Sep 21, 2011 at 8:54 PM, shu wrote:
> Hi all,
>
> I want to check
see something like this:
415 Tick time = curTick() + hitLatency;
Does this help?
On Fri, Sep 30, 2011 at 8:50 PM, Mahmood Naderan wrote:
> Grepping "latency" or "l2" returns a lot of result. Where is that
> "cache constructor" ?
>
> On 9/30/11,
lue affect IPC? which files in
> src/ use this value? Which one is the first that grab this value and
> schedule that?
>
> On 9/30/11, Jack Harvard wrote:
>> There's a parameter 'latency' in the cache config .py file:
>> http://grok.m5sim.org/source/xref/m5/src
There's a parameter 'latency' in the cache config .py file:
http://grok.m5sim.org/source/xref/m5/src/mem/cache/BaseCache.py
You can set the value from a python config file or pass through command line.
Jack Harvard
On Fri, Sep 30, 2011 at 2:47 PM, Mahmood Naderan wrote:
> Hi,
You can make two checkpoints to switch over twice, or you may only need the
first checkpoint. You need to find out where you want to switch in your code.
On 25 Aug 2011, at 15:11, Shu Wang wrote:
> Hello Jack,
>
> Thank you for the reply.
>
> What do you mean "start with atomic CPU, then O3 C
Assuming you're running with O3 CPU model, the simulator is only running at
5.34 KIPS, which is very slow.
- a fast machine should speed your simulation up to finish within 6
hours.
- run with gem5.fast
- start with atomic CPU, then O3 CPU, then back to atomic CPU.
On
That depends on what you want to do
On Wed, Aug 17, 2011 at 6:53 PM, Srinivasulu Naik B.
wrote:
> what r the things i want absorb when i run this command
>
>
> build/ALPHA_SE/gem5.opt configs/spec2006/se.py --caches --l2cache -d
> --fast-forward=1 --maxinsts 1000 -s --l2_assoc 8 --l1d_a
>> I would like to restore a checkpoint stored in a different folder than
>> default (specified by --outdir option in previous simulation). How can I
>> restore an arbitrary checkpoint.
use --checkpoint-dir="path/to/your/checkpoints/dir" option to the
fs.py on the command line.
-r 1 means to res
> 3. If you have any better idea regarding batch simulation please share.
If you have a cluster to use in your organisation, then just submit loads of
jobs to your cluster and run them in parallel.
On 17 Aug 2011, at 13:46, Nilanjan Goswami wrote:
> Hi All,
>
> I would like to simulate a set o
Abhishek, why you want to run Atomic CPU with cache?
On 11 Aug 2011, at 02:44, Abhishek Rawat wrote:
> Hi Iordan,
>
> Here is the patch for checkpointing caches. I was working on the current
> stable revision 8337:b9ba22cb23f2. This works for Simple Atomic CPU.
>
> -Abhishek
> On Wed, Aug 10,
You can search the old m5 mailing list, somebody asked the same question before
and there was a patch attached to one of the answers. Assuming you mean DRAMSim
1, there's DRAMSim 2 as well.
On 8 Aug 2011, at 19:13, tejasi pimpalkhute wrote:
> Hi there,
>
> I wish to integrate gem5 with DRAMSi
You should be able to do that in the Python config files under /configs.
On 30 Jul 2011, at 04:56, xxx wrote:
> Hi,
> In the file config.ini under m5out directory, I find the mem_width is 64 as
> the following.
> I want to decrease the mem width to 32.
> -
Yes, you need to reset stats before app run and dump stats at the end of app
run, if you just want to get cycle counts, you can try a bare-metal app first.
On 20 Jul 2011, at 21:09, Digant wrote:
> Thx for quick reply,
> Lets make it simple,
> Is it possible to get a total execution time in term
> While taking the checkpoint, you probably mentioned results/bzip2 as the
> output directory. So when you want to restore from a checkpoint, you
> mention the same directory again.
>
> --
> Nilay
What about, you have a checkpoint, and run ten simulations restoring from that
same checkpoint, b
Almost true to say, for architects, you always need to use O3 CPU, instead of
functional or timing (which are there as a mid-step to develop O3 to my
understanding).
On 16 Jul 2011, at 07:00, Mahmood Naderan wrote:
> What I found suitable for my work is SE mode and O3cpu (fs.py and -d).
> Than
Look for kernel and images here
http://www.m5sim.org/wiki/index.php/Documentation
On 17 Jun 2011, at 23:56, Shu Wang wrote:
> Hello Nilay,
>
> Thank you for the reply.
> I think I should use the full system file to test the program. However, I
> don't know how to mount the kernel system to my
64 matches
Mail list logo
