You have to use the RealView_PBX machine type to boot those images. It
used to be the default machine-type at the time of that wiki page's
writing.
Malek
On Thu, May 7, 2015 at 3:31 AM, Andreas Hansson wrote:
> Hi Junaid,
>
> Is it hanging, or just taking its time?
>
> Andreas
>
> From: Junaid
Hi Anmol,
If you revert your repository to 10345 (hg update -r 10345) or earlier
(see hg log), and try booting it should work. I am not sure why the
10346 changeset causes this problem yet.
Malek
On Wed, Feb 25, 2015 at 5:34 PM, Anmol via gem5-users
wrote:
>
>>
>
> Hi, I am facing ditto same is
If you are using the latest repo and trying to run android, then you
need to make sure the machine-type=RealView_PBX on your command line.
I think I was getting this error before I realized that android only
works with RealView. Slightly older revisions had RealView_PBX as the
default machine-type
Reza,
I recently did this for alpha. Part of the instructions on the wiki
are outdated. I found the solution buried in other email thread
discussion, which I can't find at the moment.
Here's how to do it:
git clone
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
cd lin
very much
> for your help.
>
> Best
> Tang
>
>
> On Fri, Aug 8, 2014 at 5:58 PM, Malek Musleh
> wrote:
>
>> Hi Tang,
>>
>> This is likely happening because the custom kernel you built has flags
>> for certain devices enabled, devices which are most
Hi Tang,
This is likely happening because the custom kernel you built has flags for
certain devices enabled, devices which are most likely not supported in
gem5. I encountered this problem myself when building custom x86 kernels. I
used the parsec x86 kernel flags as a starting point, and disabled
Fabian,
You should look at ./configs/topologies to see how the components are
instantiated and connected.
Malek
On Mon, Jun 23, 2014 at 3:08 PM, Weber, Fabian via gem5-users <
gem5-users@gem5.org> wrote:
> Hi,
>
> I'm still looking for the answer for my problem - where are the Ruby
> experts
You cannot access it from the prefetcher class, at least that's not what I
was suggesting. I said to pass it via a pseudoinst. A psuedoInst has the
ThreadContext available as an argument. Look at /src/sim/psuedo*.cc
After you do the conversion, then pass the physical address to the
prefetcher.
Ma
there is a function call vtophys() in the TLB class of the /arch folder.
1) Pass the virtual address from software to gem5 using a pseudo instruction
2) call vtophys()
3) check if the physical address != 0
3) should not occur if your passing in an address that is defined
Malek
On Mon, Apr 28,
You should look at using the ProtocolTrace flag to see which thread is
generating the request to this address. It's possible there is a bug in the
source code, or something else -- I think the mailing list archives show
people getting this error for a number of possible reasons.
Malek
On Mon, Ap
I have a related post on the mailing list about this, and I indicate a
workaround to the problem. It's not ideal, but it works. Keep in mind, that
just because you didn't modify the protocol, doesn't mean errors aren't
bound to occur.
Malek
On Sun, Apr 27, 2014 at 3:02 AM, sunlong wrote:
> Hi
Alex,
1)
If you based your custom protocol on one of the default (already provided)
protocols, then you can do a diff between the ProtocolTrace Flags to see
where things diverge. That way, you can isolate which new cache
states/actions are being triggered.
2) If your implementing any sort of spec
Hi Alex,
SLICC does not support loops for reasons that can be read in the SLICC
README file:
src/mem/slicc/README
Question: How comes there is no "for" loop statement in slicc?
Answer: Been there, done that. That is easy to add, first of all. But
unbound
loop make slicc eventually un-synthesizab
Alex,
It's not clear why your trying to do what your asking. It might be easier
to create a new C++ Class (or append some members to an existing C++ Class
such as Sequencer/CacheMemory/Prefetcher depending on what your trying to
do), and access whatever arrays/data structures you want via function
Hi Yuhang,
You need to enable some trace flags to see what the problem is, but I am
guessing you are running into the same problem I did not too long ago:
http://www.mail-archive.com/gem5-users@gem5.org/msg08327.html (It's one of
the first few hits on google when you search that error)
I impleme
ver used.
>
> Let me know if there are any issues.
>
> Andreas
>
> From: Malek Musleh
> Reply-To: gem5 users mailing list
> Date: Sunday, 8 September 2013 21:01
> To: gem5 users mailing list
> Subject: [gem5-users] Using Protobuf for reading CommMonitor Trace
Hi,
I am using the CommMonitor component to look at a trace of memory address
references between the cpu/cache. I seem to have connected it properly, as
in my output directory I see a protobuf binary file generated for each
monitor: e.g. monitor_0.ptrc, monitor_1.ptrc, etc.
This file generated
ely need to modified (e.g. what code sections
specifically wrt locking primitives) to support this solution? Doing a grep
through the ruby code, I only see one check for BUSY Access Permission
check, and that is in the same functionalRead() function.
Malek
On Thu, Aug 1, 2013 at 12:52 PM, Malek Mu
zling: "before the functional access
> completes". A functional access is purely a chain of function calls that
> complete in 0 time. How can anything happen before it completes?
>
> Thanks,
>
> Andreas
>
> From: Malek Musleh
> Reply-To: gem5 users mailing list
&
Hi,
I am running into a problem with one of my simulations where a functional
read accss is failing. It is failing in this case because as the RubySystem
is handling the functional accesses, it checks all the controllers in the
system to determine which controllers have the block with the necesary
to be overall L2 accesses. In fact I am calculating the
> average L2 miss rate and since my L2 is shared among all cores, I look at
> it as a big shared L2 cache.
>
> Thanks,
> Mahshid
>
>
>
>
> On Wed, Jun 12, 2013 at 1:04 PM, Malek Musleh wrote:
>
>> The patch w
The patch was incorporated into some other recent ruby stat changes
recently (1-2 weeks): specifically the removal of the cache profiler, and
the counting of hits/misses directly in the sm file. So you should probably
update.
The other thing is, I think your complicating your calculations a bit:
This patch here should do it:
http://reviews.gem5.org/r/1467/
Malek
On Sat, Apr 20, 2013 at 1:28 AM, Ashish Maurya wrote:
> That's because in file
> /src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm call to profiler is
> annotated.
>
>action(uu_profileMiss, "\u", desc="Profile the dema
can ignore the first one?
>
> Thanks
> Hui
>
>
> On Mon, Mar 25, 2013 at 4:17 PM, Malek Musleh
> wrote:
>>
>> Hi Hui,
>>
>> The first section corresponds to stats because of the psuedoInst
>> dumpstats call that binary makes and the 2nd s
Hi Hui,
The first section corresponds to stats because of the psuedoInst
dumpstats call that binary makes and the 2nd stats dump corresponds to
the stats dump that occurs at the end of the simulation (looks like
you are using the precompiled images from UT-Austin).
Malek
On Mon, Mar 25, 2013 at
ine 122]
> Memory Usage: 2755956 KBytes
> Program aborted at cycle 25000
>
> All of this worked with 9268:a0ca00815cc4 and my codebase is unmodified.
>
> On Sat, 16 Mar 2013, Malek Musleh wrote:
>
>> Marco,
>>
>> The error message is telling you that a deadlock
Marco,
The error message is telling you that a deadlock exists in the system,
meaning that some request has not been satisfied within the allotted
deadlock_threshold parameter. Turning on the ProtocolTrace debug flag,
and grepping through the traces for the address specified will tell
you when it
applied your patch.
> How should I change it?
>
> By the way, I checked out the changes you made in the code and it really
> helped me get more into it. So thanks a lot.
>
> Mehmet
>
>
> 2013/2/15 Malek Musleh
>>
>> Hi mehmet,
>>
>> I have poste
Hi mehmet,
I have posted a patch on the review board that does this:
http://reviews.gem5.org/r/1467/diff/
If I recall, I only apply it to the MOESI_CMP, MESI protocols. You can
take a look, or apply the diff (not sure if it will apply cleanly on
the dev repo).
Malek
On Fri, Feb 15, 2013 at 9:2
HI Jordan,
The protocol files themselves specified latencies for the different
ports, rather than pulling them from the config files. For example in
the MESI_CMP_directory-L1cache.sm file:
int l2_select_num_bits,
int l1_request_latency = 2,
int l1_response_latency = 2,
int to_l2_latency = 1,
Hi Vinh,
I think if you make the following change it should work:
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -267,6 +267,7 @@
for cpu in cpus:
cpu.workload = root.workload
+cpu.createInterruptController()
Hi,
I am running into a deadlock/starvation problem using the
MOESI_CMP_directory protocol due to the recycling of messages on
blocked Addresses, and so I have converted the protocol to use the
Stall/Wait MessageBuffer Actions instead of recycling the messages.
However, in doing so, I am running i
Hi Jinchun,
None of the ruby protocols correctly calculate cache hits/misses. They
basically call uu_profileMiss Action which just samples the type of
Cache Request it is. I have a posted a patch on the review board some
time ago that calculates them for MOESI_CMP_directory and MESI. You
can do s
Hi Mark,
I don't think it would be any easier, in fact it's probably more
difficult to switch out memory systems. To ensure program correctness,
even if a set of Ruby Caches and Classic Mem Caches were instantiated,
you would need to flush from one to the other, and back between every
sampling int
Roberto,
You should be able to pass the --ruby flag to the se.py script to use
the Ruby Memory Model instead of the classic memory model.
Malek
On Wed, Nov 21, 2012 at 12:52 PM, Roberto RodrÃguez-RodrÃguez
wrote:
> It is possible to pass a program as an argument to se.py.
>
> build/X86/gem5.opt
-11-20 at 13:19 -0500, Malek Musleh wrote:
>> Pavlos,
>>
>> That patch also prints the absolute values for the
>> hits/misses/accesses, and solves that misnomer issue. The only thing
>> it does not change is the member name profileMiss() of the CacheMemory
>> clas
m5
> (you said "Currently, ruby counts (refers to) all cache accesses as
> 'misses' which..."). It would be also helpful to print
> cache accesses and cache misses as absolute values, I suppose
> someone could need them.
>
> Thanks again,
> Pavlos
>
> On
is wrote:
> Hello Malek,
>
> Thanks for the reply.
> ruby.stats file reports the absolute number of cache misses but
> I need its proportion to all cache accesses. I can't understand
> how this patch will help me. Will it print the cache ratio (%) in
> ruby.stats file?
>
Hi Pavlos,
I have a patch posted here for this:
http://reviews.gem5.org/r/1467/
I only added support for MESI/MOESI Protocols, but you can extend to
the other ones also.
Malek
On Tue, Nov 20, 2012 at 11:09 AM, Pavlos Maniotis wrote:
> Hello everyone,
>
> Is there anybody who knows how to calc
Hi,
I am running into some issues with Writing / Restoring Checkpoints for
the Ruby MOESI_CMP_directory Protocol on ALPHA for simulating the NAS
Benchmarks.
In particular, generating the actual checkpoint seems fine, but the
program seems to hang when attempting to restore from the checkpoint.
W
Malek
> can u write the commands which you used in this process.
>
> regards
> Mir
> *
> *
>
>
> --- On *Fri, 12/10/12, Malek Musleh * wrote:
>
>
> From: Malek Musleh
> Subject: Re: [gem5-users] [gem5-dev] Status Matrix for Ruby SE InOrderCPU
> To: "
development release?
>
> Thanks again,
>
> Pavlos
>
> On Wed, 2012-10-31 at 10:06 -0400, Malek Musleh wrote:
>> Hi Pavlos,
>>
>> I have posted a patch on the review board that does this for
>> MOESI/MESI Protocols.
>>
>> Take a look here: http://r
Hi Pavlos,
I have posted a patch on the review board that does this for
MOESI/MESI Protocols.
Take a look here: http://reviews.gem5.org/r/1467/
Malek
On Tue, Oct 30, 2012 at 12:22 PM, Pavlos Maniotis wrote:
> Hello everyone,
>
> Could somebody please help me on how to calculate the
> miss rate
don't see how (yet) one can avoid modifying the protocol files to
support L2 initiated prefetches.
Malek
On Wed, Oct 24, 2012 at 11:19 AM, Nilay Vaish wrote:
> On Tue, 16 Oct 2012, Malek Musleh wrote:
>
>> Hi,
>>
>> I have a question about implementing prefetching
d on the MESI protocol (inclusive cache
> hierarchy), a block in L1 cache should also be in the L2. Is it correct?
> Thanks for your help.
>
>
> Best,
> Yingying
>
>
>
> Date: Tue, 16 Oct 2012 18:09:16 -0400
> From: Malek Musleh
> To: gem5 users mailing list
Hi Yingying,
NetDest indicates in which of the Memory Caches the address is present
in the protocols MachineType. In the case for MESI there are 4:
(L1Cache, L2Cache, Directory, DMA).
[NetDest (4) 0 1 - 0 0 - 0 - 0 - ]
In this case the tag is present only in the second L1Cache (L1Cache1)
[N
Hi,
I have a question about implementing prefetching with the Ruby Memory
Model. Looking at the Sequencer.cc code, there is a comment about how
hardware prefetches should be issued in the makeRequest() routine.
Now, I can sort of understand why hardware prefetches should be issued
from the sequenc
ly to
have issues than running in SE Mode.
Malek
On Thu, Oct 11, 2012 at 9:25 PM, Nilay Vaish wrote:
> On Thu, 11 Oct 2012, Malek Musleh wrote:
>
>> Hi,
>>
>> According to the status matrix: http://www.m5sim.org/Status_Matrix it
>> says that it is unknown whether or n
The GOMP_CPU_AFFINITY will only work for OpenMP benchmarks (of which only a
subset of the parsec benchmarks have OMP versions). For pthread
implementations (including Splash2 benchmarks) you have to use
pthread_affinity() scheduling, requiring you to modify the benchmark source
code.
There are com
So I have been following this thread as well since I too have an
interest in getting this working. From the trace, it seems that the
problematic request in this case is to address: 0x7ffc
The ITLB Walker is unable to queue the read request, and so it needs
to be retried
> 5403272000: system.cpu.i
Hi Xing,
I think in your case you want to add your function to the
RubySlicc_Util.sm file since your new function is similar to the other
member functions in class Address such as makeLineAddress().
Malek
On Wed, May 9, 2012 at 11:06 PM, Xing HAN wrote:
> Hello,
>
>
> I want to make some modifi
Are you sure you are specifying the correct path to the input file?
As in are you forgetting the '.' in front of the /cholesky/inputs?
cd /splash2/codes/kernels/cholesky
echo "Running SPLASH2-cholesky 16 Proc -- Cache:16384 Input:23"
/sbin/m5 resetstats
/sbin/m5 checkpoint
./CHOLESKY -p16 -C16384
>
>
> On 4/14/12, Malek Musleh wrote:
>> Well first of all, you are not making first comparisons, as each of
>> the runs you are using a different cpu type. So I think you should
>> start with fixing that parameter first.
>>
>> Malek
>>
>> On Sat,
Well first of all, you are not making first comparisons, as each of
the runs you are using a different cpu type. So I think you should
start with fixing that parameter first.
Malek
On Sat, Apr 14, 2012 at 1:34 PM, Mahmood Naderan wrote:
> For the old one, I use:
> build/X86_SE/m5.fast configs/ex
anks
Malek
Malek
On Mon, Apr 2, 2012 at 10:10 AM, Malek Musleh wrote:
> Hi Tushar,
>
> Thanks for the clarification. I had thought this earllier on, but when
> reading the tutorial (slides 13-136) and gem5 wiki
> (MOESI_CMP_directory), where there are references to multiple chips,
>
MOESI_hammer models a private L2, but the L2 tracks only partial
> state, and resorts to broadcasts.
>
> cheers,
> Tushar
>
>
> On Apr 1, 2012, at 5:29 PM, Malek Musleh wrote:
>
>> Hi Tushar,
>>
>> I am looking for clarification between configuring caches
rCorners
> topologies.
>
> cheers,
> Tushar
>
>
> On 1/9/2012 1:24 AM, gem5-users-requ...@gem5.org wrote:
>>
>> Date: Sun, 8 Jan 2012 23:26:19 -0500
>> From: Malek Musleh
>> To: gem5 users mailing list
>> Subject: [gem5-users] Issue Defining new Ruby
Hi Hongli,
I did manage to figure this out. Basically you need to check the ISA's
register using InUserMode() in the CPU Model, set a flag in the
packet, and then in the Sequencer/RubyPort code select the kind of
access permission for the rubyrequest based on if its in user mode or
not.
Here is a
Hi,
I have a question regarding using different cacheline sizes in Ruby
Memory Simulations.
Using the --cacheline_size option it is possible to change the number
of bytes each cache line is: but
According to:
http://gem5.org/Coherence-Protocol-Independent_Memory_Components
simulating with any
Hi Sudhanshu,
I don't think your problem is caused by the kernel patching:
See the following thread:
It is quite old, but seems like it should still be applicable in your case:
http://www.mail-archive.com/gem5-users@m5sim.org/msg01370.html
Malek
On Fri, Mar 2, 2012 at 2:10 PM, Sudhanshu Jha w
Thanks in advance.
Malek
musleh@sherpa13:~/gem5_push3/util/term$ ./m5term localhost 3456
m5 slave terminal: Terminal 0
Using 16 procs on 3 steps of 343 mols
Other parameters:
TSTEP = 1.50e-16
NORDER = 6
NSAVE = -1
NRST = 3000
NPRINT = 3
ll, so that whenever the L1requestToL2
port wants to schedule an event, it can reschedule MYINPORT.
You would just need to add something like * to determine when your
MYINPORT gets initialized.
Malek
On Thu, Feb 23, 2012 at 9:47 AM, Malek Musleh wrote:
> Hi Marti,
>
> In that case, you
ituation it would be possible to
> reschedule my_InPort consumer to another cycle?" And how? :D If we find out
> that my issue would be totally solved!
>
> Thanks in advance!
>
>
> 2012/2/23 Malek Musleh
>>
>> Hi Marti,
>>
>> I would think that yo
wrote:
>>
>>> Hy Malek,
>>>
>>> Thanks for your answer, but I think that this parameter (rank) is only
>>> used
>>> when 2 inports are going to access the same address. In my case I want to
>>> issue only one of the two InPorts per cycle. Do you
Hi Marti,
I believe you would need to specify the rank of the inport.
For example:
// Response Network
in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
You would then need to define the priority for each of the in_ports.
Take a look at the MOESI_CMP_Token protocol as r
Hi,
I am trying to define a new type of network topology to use with the
Ruby Memory System. Specifically, I am trying to define a Mesh-type
topology that can support multiple (n) L1 caches connected to a shared
L2 cache for a per chip node basis, unlike the currently provided
Mesh/MeshDirCorners
Hi Steve,
Try this:
http://m5sim.org/cgi-bin/mailman/private/gem5-users/2009-January/004014.html
I was able to access the patch.
Malek
On Mon, Oct 31, 2011 at 11:26 PM, Stevenson Jian
wrote:
> Hi everyone,
> I am trying to use DRAMsim with GEM5. In the mailing list archive, I found
> that the
Hi,
I was wondering if anyone could confirm the exact need of the
TimerTable in the MOESI CMP Directory Protocol for Ruby.
Looking at the code, and its usage in the Protocol, it seems that when
an L1 cache receives an exclusive copy of the Data, and thus should
make the transition to either M or
Hi,
It is because the configuration script divides the amount of physical
memory proportionally among the number of directory controllers.
Therefore, for an odd number of Directories, and an even physical
memory size, you will have some remainder. If you insert some prints
in Ruby.py, you will see
Hi Dibakar,
It is most likely because the threads are all getting mapped to the
same core. This happens, because the GOMP Affinity environment is
empty by default, and thus all scheduling is being handled by the
kernel.
Try Inserting this into your c program, and see what it prints out as
the env
Sorry if you receive this twice, it didn't seem to show up in the
email box first time through.
-- Forwarded message --
From: Malek Musleh
Date: Tue, Sep 13, 2011 at 4:05 PM
Subject: Ruby Request Default Access Mode Type is always Supervisor?
To: gem5 users mailing list
Hi,
I have a question about the creation of Ruby Requests. It seems that
when a ruby request is created in the recvTiming() of RubyPorts, it
creates the request with the RubyAccessMode_Supervisor Attribute by
default.
RubyPort::recvTiming():
RubyRequest ruby_request(pkt->getAddr(), pkt->getPt
Hi,
I am not an expert in Cache Coherency, although I have done some work in it.
In the "real world" cache state transitions are not atomic, but is initially
taught as such in courses as a way to present CC schemes. Actual
implementations of MESI and others vary depending on the vendor.
Malek
On
73 matches
Mail list logo
