Hi,
I am using gem5 se.py to run some simulations. Is there a simple way to
dump the stats into different files each time I call m5_dump_stats(…)? I.e.
I want the stats files to be organized as stats.1.txt, stats.2.txt, …
instead of one monolithic stats.txt.
Thanks!
Subhankar Pal | PhD
Thank you, Ciro. Turned out that by disabling most of the (classic) cache
stat handlers, I was able to free up a lot of memory.
Subhankar Pal | PhD Candidate, CSE | University of Michigan
On March 25, 2020 at 4:38:52 AM, Ciro Santilli (ciro.santi...@gmail.com)
wrote:
I would try to put
t which memObject the allocation fails for? I have tried
invoking gem5.opt with gdb, but I don’t get a backtrace, presumably because
the failure happens in a Python function call.
Thank for any help.
Subhankar Pal | PhD Candidate, CSE | University of Michigan
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better
suggestions?
Thanks in advance!
Subhankar Pal | PhD Candidate, CSE | University of Michigan
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I will try it out. I appreciate the help.
--
Subhankar Pal
On April 20, 2019 at 4:40:41 PM, Pouya Fotouhi (pfoto...@ucdavis.edu) wrote:
Subhankar,
As Gabe mentioned, you should simply disable listeners (set
--remote-gdb-port=0 with your gem5 binary) IF you are not inspecting your
simulations
Could someone please help with this issue?
--
Subhankar Pal
On March 31, 2019 at 10:42:22 AM, Subhankar Pal (s...@umich.edu) wrote:
Hi,
I am running simulations on a modified se.py multi-CPU config on the Arm
ISA. I am running custom benchmarks coded in C++. For some of my
long-running
your architecture"*
>From a survey of previous posts in the mailing list, it seemed that
m5threads is not supported for Alpha. Is it still the case, or is there a
workaround for it?
Thanks in advance.
--
Subhankar Pal
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ards,
Subhankar Pal
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Hi Muzamil,
It probably means that the size of your memory divided by the number of
memory devices is 256 MB, whereas the device_size of your memory is 8 MB.
You need to make sure that these two number must be equal.
- Subhankar
On March 28, 2017 at 3:39:53 PM, Muzamil Rafique (
/dram_ctrl.cc:2107: void
DRAMCtrl::Rank::processWakeUpEvent(): Assertion `(pwrState == PWR_ACT_PDN)
|| (pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF)' failed.*
Can someone help me on how to fix this error?
Thank you!
Subhankar Pal
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Hi,
Is there an better way to turn off cache coherence in the classic memory
model, than to hack the code in src/mem/cache/? I know that that there
exists a noncoherent XBar model, but couldn’t find an equivalent for
caches.
Thank you!
- Subhankar
___
to go from
XBar to cache and vice versa). How do I achieve this? Also, I would like to
know how to simulate multiple channels in the main memory.
Any pointers/explanation is highly appreciated. Thanks in advance for your
help!
Subhankar Pal | Computer Science & Engineering | Univer
to go from
XBar to cache and vice versa). How do I achieve this? Also, I would like to
know how to simulate multiple channels in the main memory.
Any pointers/explanation is highly appreciated. Thanks in advance for your
help!
Subhankar Pal
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