On 3/17/2023 10:27 AM, Peter Relson wrote:
And it's fair to wonder. We do "cheat" and turn off facility bits in "our copy" that
relate to facilities that the customer, via MACHMIG, has asked not to be exploited for migration reasons. In
practice, for those facilities it is not relevant whether
Ed J wrote
What about MACHMIG? Do you turn off the bit(s) corresponding to a
facility that we wish to pretend does not exist via LOADxx specification?
And it's fair to wonder. We do "cheat" and turn off facility bits in "our copy"
that relate to facilities that the customer, via MACHMIG, has
On 3/16/2023 5:15 AM, Peter Relson wrote:
The only difference between "your" STFLE and "our" STFLE is that the z/OS one
is done only once, at IPL.
If some facility arrived after IPL, you could find it with "your" STFLE That is
far from a frequent occurrence.
What about MACHMIG? Do you turn
Or you just could do an STFLE and check the facility bits...
Or your could use the facility bit area that z/OS set up for you. That's easier.
That is mapped by IHAFACL and the area is pointed to by ECVTFACL (this has
existed since z/OS 2.1).
A subset of those bits are also mapped within the
On z/OS 2.2 or later, the result from STFLE is stored in the PSA at offset 200
(X'C8') - look at IHAPSAE field name FLCEFACILITIESLIST (and this is a PI
field)
Kind regards
John
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> From: IBM Mainframe Discussion List on behalf
> of Ituriel do Neto <03427ec2837d-dmarc-requ...@listserv.ua.edu>
> Sent: 15 March 2023 13:30
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: CS/CDS instruction
>
> Can we detect if a specifi
Re: CS/CDS instruction
Can we detect if a specific feature is available in the current hardware?
Best Regards
Ituriel do Nascimento Neto
z/OS System Programmer
Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin
<042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu:
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: CS/CDS instruction
Can we detect if a specific feature is available in the current hardware?
Best Regards
Ituriel do Nascimento Neto
z/OS System Programmer
Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin
<042bfe9c879d-dm
Can we detect if a specific feature is available in the current hardware?
Best Regards
Ituriel do Nascimento Neto
z/OS System Programmer
Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin
<042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu:
On Sat, 11 Mar 2023
On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote:
>If some particular instruction set feature is installed, the
>definition of ASI/AGSI is enhanced to serialize the update, making it
>a simpler solution than a CDS loop or PLO.
>
>In some performance testing a while back on a z14 or z15
-MAIN@LISTSERV.UA.EDU] on behalf of
Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction
Hi all,
Is there a similar instruction to CS or CDS, but using 64 bits register ?
I have a double word
https://www.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/1/897/ENUS122-001/index.html
IBM z16tm puts innovation to work while unlocking the potential of
your hybrid cloud transformation
IBM United States Hardware Announcement 122-001
April 5, 2022
Removal of support of the
On Thu, 9 Mar 2023 20:06:10 -0600, Paul Gilmartin wrote:
>On Thu, 9 Mar 2023 18:17:14 -0600, Tom Marchant wrote:
>
>>IBM has announced that Transactional execution will be removed.
>>
>Entirely? I read much earlier that it was being removed partially.
From the z16 announcement
Removal of
The statement of direction is clear.
That stated direction is to remove the transactional execution facility.
I think that no information is yet available about "when" or whether it might
be done in stages.
Paul G wrote
>Transactional execution : software :: speculative execution : firmware.
On 3/9/2023 6:06 PM, Paul Gilmartin wrote:
On Thu, 9 Mar 2023 18:17:14 -0600, Tom Marchant wrote:
IBM has announced that Transactional execution will be removed.
Entirely? I read much earlier that it was being removed partially.
Partial disablement of anything is often a prelude to
On Thu, 9 Mar 2023 18:17:14 -0600, Tom Marchant wrote:
>IBM has announced that Transactional execution will be removed.
>
Entirely? I read much earlier that it was being removed partially.
Transactional execution : software :: speculative execution : firmware.
But in the latter case, the
On Thu, 9 Mar 2023 at 18:52, Attila Fogarasi wrote:
> The modern way is Transactional Execution.
It would be if IBM hadn't announced that it's being discontinued.
> PLO was developed decades ago
> and works well by itself but doesn't co-exist well with CS/CDS. From a
> performance
IBM has announced that Transactional execution will be removed.
--
Tom Marchant
On Fri, 10 Mar 2023 10:51:59 +1100, Attila Fogarasi wrote:
>The modern way is Transactional Execution. PLO was developed decades ago
>and works well by itself but doesn't co-exist well with CS/CDS. From a
nt performance data.
>
>
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
>
>
> From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf
> of Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu
...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction
Hi all,
Is there a similar instruction to CS or CDS, but using 64 bits register ?
I have a double word that contains a counter and using 64 bits instructions
would be faster to increment
of
Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction
Hi all,
Is there a similar instruction to CS or CDS, but using 64 bits register ?
I have a double word that contains a counter and using
Ituriel do Neto asked:
>Is there a similar instruction to CS or CDS, but using 64 bits register ?
CSG/CDSG. Look at Principles of Operation.
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CSG and CDSG in Pop.
Sent from my iPhone
> On Mar 1, 2023, at 3:53 PM, Ituriel do Neto
> <03427ec2837d-dmarc-requ...@listserv.ua.edu> wrote:
>
> Hi all,
>
> Is there a similar instruction to CS or CDS, but using 64 bits register ?
>
> I have a double word that contains a counter and
Hi all,
Is there a similar instruction to CS or CDS, but using 64 bits register ?
I have a double word that contains a counter and using 64 bits instructions
would be faster to increment this value than manipulate it with other storage
areas and an even-odd pair of 32 bits registers.
Thanks in
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