Hi Lucas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20200701]
[cannot apply to v5.8-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8689_full -> Patchwork_18063_full
Summary
---
**FAILURE**
Serio
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/dp: Helper for checking
DDI_BUF_CTL Idle status
URL : https://patchwork.freedesktop.org/series/79018/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8688_full -> Patchwork_18062_full
==
== Series Details ==
Series: drm/i915: do not read swizzle info if unavailable
URL : https://patchwork.freedesktop.org/series/79007/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8688_full -> Patchwork_18061_full
Summary
--
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8689 -> Patchwork_18063
Summary
---
**SUCCESS**
No regressions
== Series Details ==
Series: drm/i915: Fix the old vs. new epoch counter check during hotplug detect
URL : https://patchwork.freedesktop.org/series/79006/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8688_full -> Patchwork_18060_full
==
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
988d01bfbd82 drm/i915: Add has_master_unit_irq flag
241025556ca5 drm/i915/dg1: add initial DG-1 definitions
-:41: CHECK:MACRO_AR
On Wed, Jul 1, 2020 at 12:34 PM Chris Wilson wrote:
>
> Quoting Lucas De Marchi (2020-07-01 19:36:26)
> > Since gen8 we don't use swizzle anymore. Don't dump registers related to
> > it: registers may or may not be there.
> >
> > Cc: Matt Roper
> > Signed-off-by: Lucas De Marchi
> > ---
> > dri
From: Venkata Sandeep Dhanalakota
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio
Cc: Michael J. Ruhl
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 4
1 file changed, 4 insertions
From: Anshuman Gupta
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/in
From: Matt Atwood
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper
Signed-off-by: Matt Atwood
Signed-off-by: Lucas De Marchi
---
From: Matt Roper
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
v2:
- Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to
TGL's, so we'll have both functions call the tgl_ function for now;
this workaro
From: Matt Roper
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Matt Roper
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
log
From: Stuart Summers
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
v2: Also add Wa_16011227922
Cc: Matt Atwood
Cc: Matt Roper
Cc: Radhakris
From: Aditya Swarup
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/d
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
v2: Also change intel_hpd_pin_default() to include DG1 mapping
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hotplug.
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the inde
From: Matt Roper
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/i
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
>From spec we have registers GPIO_CTL[1-4], so we should not do t
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
driver
From: Uma Shankar
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB
From: Matt Roper
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+. Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.
For simplicity, let's just assume that this 38.4 MHz frequency
v3:
- Make sure we don't bind the driver to the device while the driver is
not complete. This should unblock us to have these basic patches
merged so the next parts can be developed/refactored/implemented,
particularly related to lmem.
When we have these patches applied and lmem part worki
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functio
From: Matt Roper
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Abdiel Janulgue
Add the PCI ID for DG1, but keep it out of the table we use to register
the driver. At this point we can't consider the driver ready to bind to
the device since we basically miss support for everything. When more
support is merged we can enable it to work partially for examp
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gp
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
v2: fix coding style on register definition
Cc: Radhakrishna Sripada
Cc: Daniele Spurio Ceraolo
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/
From: Aditya Swarup
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30
From: Abdiel Janulgue
Bspec: 33617, 33617
Cc: José Roberto de Souza
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Vanshidhar Konda
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Sou
From: Aditya Swarup
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
driver
From: Aditya Swarup
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display
From: Clinton A Taylor
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza
Cc: Matt Roper
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 4
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 8 inse
From: Matt Roper
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshak
From: Stuart Summers
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h
From: Anusha Srivatsa
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i
On Wed, 2020-07-01 at 21:37 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp: Correctly advertise HBR3 for GEN11+ (rev2)
> URL : https://patchwork.freedesktop.org/series/61546/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8679_full -> Patchwork
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/dp: Helper for checking
DDI_BUF_CTL Idle status
URL : https://patchwork.freedesktop.org/series/79018/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8688 -> Patchwork_18062
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/dp: Helper for checking
DDI_BUF_CTL Idle status
URL : https://patchwork.freedesktop.org/series/79018/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b5ae01c903fb drm/i915/dp: Helper for checking DDI_BUF_CTL Idl
Based on the platform, Bspec expects us to wait or poll with
timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active
after enabling DDI_BUF_CTL.
v2:
* Based on platform, fixed delay or poll (Ville)
* Use a helper to do this (Imre, Ville)
v3:
* Add a new function _active for DDI BUF CT
Modify the helper to add a fixed delay or poll with timeout
based on platform specification to check for either Idle bit
set (DDI_BUF_CTL is idle for disable case)
v2:
* Use 2 separate functions or idle and active (Ville)
v3:
* Change the timeout to 16usecs (Ville)
v4:
* Change the timeout 8, foll
== Series Details ==
Series: drm/i915/guc: Expand guc_info debugfs with more information
URL : https://patchwork.freedesktop.org/series/78997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8686_full -> Patchwork_18058_full
Thanks much Sam for reviewing the code so quickly. I'll address your reviews in
v2.
Anitha
> -Original Message-
> From: Sam Ravnborg
> Sent: Wednesday, July 1, 2020 12:01 AM
> To: Chrisanthus, Anitha
> Cc: dri-de...@lists.freedesktop.org; Paauwe, Bob J ;
> Dea, Edmund J ; Vetter, Danie
== Series Details ==
Series: drm/i915/dp: Correctly advertise HBR3 for GEN11+ (rev2)
URL : https://patchwork.freedesktop.org/series/61546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8679_full -> Patchwork_18050_full
Summ
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to v5.8-rc3 next-20200701]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
Quoting Lucas De Marchi (2020-07-01 19:36:26)
> Since gen8 we don't use swizzle anymore. Don't dump registers related to
> it: registers may or may not be there.
>
> Cc: Matt Roper
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 8 ++--
> 1 file changed, 6 ins
On Wed, Jul 01, 2020 at 11:44:04AM -0700, Manasi Navare wrote:
> On Wed, Jul 01, 2020 at 02:20:28PM +0200, Maarten Lankhorst wrote:
> > Op 30-06-2020 om 13:26 schreef Stanislav Lisovskiy:
> > > We still need "Bump up CDCLK" workaround otherwise getting
> > > underruns - however currently it blocks
On Wed, Jul 01, 2020 at 09:00:01PM +0300, Imre Deak wrote:
> The old epoch counter was left uninited, so the function returned a
> changed state always.
>
> While at it debug print the old epoch counter as well.
>
> Fixes: 35205ee9ba46 ("drm/i915: Send hotplug event if edid had changed")
> Cc: Ku
== Series Details ==
Series: drm/i915: do not read swizzle info if unavailable
URL : https://patchwork.freedesktop.org/series/79007/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8688 -> Patchwork_18061
Summary
---
*
On Wed, Jul 01, 2020 at 02:20:28PM +0200, Maarten Lankhorst wrote:
> Op 30-06-2020 om 13:26 schreef Stanislav Lisovskiy:
> > We still need "Bump up CDCLK" workaround otherwise getting
> > underruns - however currently it blocks 8K as CDCLK = Pixel rate,
> > in 8K case would require CDCLK to be arou
== Series Details ==
Series: drm/i915: Fix the old vs. new epoch counter check during hotplug detect
URL : https://patchwork.freedesktop.org/series/79006/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8688 -> Patchwork_18060
Since gen8 we don't use swizzle anymore. Don't dump registers related to
it: registers may or may not be there.
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/
== Series Details ==
Series: drm/i915/dmc: Use firmware v2.02 for RKL
URL : https://patchwork.freedesktop.org/series/78989/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8685_full -> Patchwork_18057_full
Summary
---
The old epoch counter was left uninited, so the function returned a
changed state always.
While at it debug print the old epoch counter as well.
Fixes: 35205ee9ba46 ("drm/i915: Send hotplug event if edid had changed")
Cc: Kunal Joshi
Cc: Stanislav Lisovskiy
Cc: Maarten Lankhorst
Signed-off-by:
On Wed, Jul 01, 2020 at 08:04:30PM +0300, Ville Syrjälä wrote:
On Wed, Jun 24, 2020 at 05:11:18PM -0700, Lucas De Marchi wrote:
Identify 3 possible cases in which the index numbers can be different
from the "port" and add them to the description-based ddi initialization
table. This can be used
On Wed, Jun 24, 2020 at 05:11:18PM -0700, Lucas De Marchi wrote:
> Identify 3 possible cases in which the index numbers can be different
> from the "port" and add them to the description-based ddi initialization
> table. This can be used in place of additional functions mapping from
> one to the o
On 01.07.2020 17:17, Chris Wilson wrote:
> Quoting Michał Winiarski (2020-07-01 16:07:21)
>> From: Michał Winiarski
>>
>> Getting wedged device on driver init is pretty much unrecoverable.
>> Since we're running verious scenarios that may potentially hit this in
typo
>> CI (module reload / sel
On Wed, Jul 01, 2020 at 06:17:09PM +0300, Jani Nikula wrote:
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
This is the first level conversion to use port_info directly from
intel_digital_port, rather than derive the phy or tc_port from the port.
This touches only the functions which have the enco
On Wed, 2020-07-01 at 16:27 +0200, Michał Winiarski wrote:
> From: Michał Winiarski
>
> The information about platform/driver/user view of GuC firmware usage
> currently requires user to either go through kernel log or parse the
> combination of "enable_guc" modparam and various debugfs entries.
== Series Details ==
Series: series starting with drm/i915/gt: Harden the heartbeat against a stuck
driver (rev2)
URL : https://patchwork.freedesktop.org/series/78986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8684_full -> Patchwork_18056_full
On 7/1/2020 7:27 AM, Michał Winiarski wrote:
From: Michał Winiarski
The information about platform/driver/user view of GuC firmware usage
currently requires user to either go through kernel log or parse the
combination of "enable_guc" modparam and various debugfs entries.
Let's keep things si
On Wed, Jul 01, 2020 at 06:23:05PM +0300, Jani Nikula wrote:
On Wed, 01 Jul 2020, Jani Nikula wrote:
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
Identify 3 possible cases in which the index numbers can be different
from the "port" and add them to the description-based ddi initialization
table
== Series Details ==
Series: drm/i915/gem: Move obj->lut_list under its own lock
URL : https://patchwork.freedesktop.org/series/78988/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8684_full -> Patchwork_18055_full
Summary
On Wed, 01 Jul 2020, Jani Nikula wrote:
> On Wed, 24 Jun 2020, Lucas De Marchi wrote:
>>
>> +struct intel_ddi_port_info {
>
> Just thinking out loud, should we have a "struct port" or "struct
> intel_port" instead. Maybe, maybe not. *shrug*
After reading the whole series, I might lean even mor
On Wed, Jul 01, 2020 at 06:35:55PM +0300, Jani Nikula wrote:
On Wed, 01 Jul 2020, Jani Nikula wrote:
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
+struct intel_ddi_port_info {
Just thinking out loud, should we have a "struct port" or "struct
intel_port" instead. Maybe, maybe not. *shrug*
On Tue, Jun 30, 2020 at 06:55:38PM +0300, Jani Nikula wrote:
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
We are not checking for specific SKUs and feedback from HW team is that
it may not work since it was supposed to be fixed by the same time
straps stopped to be used. So, just update comment.
On Wed, Jul 01, 2020 at 05:20:17PM +0300, Jani Nikula wrote:
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
Start adding per-platform relevant data into a table that we use for
initialization. Intention is to keep the different indexes we need (e.g.
phy, vbt, ddi, etc) and any other differences fo
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
> Now that we have tables for all platforms using ddi, keep the port_info
> around so we can use it for decisions like "what phy does it have?"
> instead of keep checking the platform/gen everywhere.
Reviewed-by: Jani Nikula
>
> Signed-off-by: Lucas D
On Wed, 01 Jul 2020, Jani Nikula wrote:
> On Wed, 24 Jun 2020, Lucas De Marchi wrote:
>> Identify 3 possible cases in which the index numbers can be different
>> from the "port" and add them to the description-based ddi initialization
>> table. This can be used in place of additional functions m
Quoting Michał Winiarski (2020-07-01 16:07:21)
> From: Michał Winiarski
>
> Getting wedged device on driver init is pretty much unrecoverable.
> Since we're running verious scenarios that may potentially hit this in
> CI (module reload / selftests / hotunplug), and if it happens, it means
> that
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
> This is the first level conversion to use port_info directly from
> intel_digital_port, rather than derive the phy or tc_port from the port.
> This touches only the functions which have the encoder or dig_port
> directly available.
Overall I like it,
Quoting Michał Winiarski (2020-07-01 16:07:21)
> From: Michał Winiarski
>
> Getting wedged device on driver init is pretty much unrecoverable.
> Since we're running verious scenarios that may potentially hit this in
> CI (module reload / selftests / hotunplug), and if it happens, it means
> that
== Series Details ==
Series: drm/i915/guc: Expand guc_info debugfs with more information
URL : https://patchwork.freedesktop.org/series/78997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8686 -> Patchwork_18058
Summary
--
From: Michał Winiarski
Getting wedged device on driver init is pretty much unrecoverable.
Since we're running verious scenarios that may potentially hit this in
CI (module reload / selftests / hotunplug), and if it happens, it means
that we can't trust any subsequent CI results, we should just ap
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
> Identify 3 possible cases in which the index numbers can be different
> from the "port" and add them to the description-based ddi initialization
> table. This can be used in place of additional functions mapping from
> one to the other. Right now we
== Series Details ==
Series: series starting with [01/33] drm/i915/gt: Harden the heartbeat against
a stuck driver
URL : https://patchwork.freedesktop.org/series/78987/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8683_full -> Patchwork_18054_full
===
From: Michał Winiarski
The information about platform/driver/user view of GuC firmware usage
currently requires user to either go through kernel log or parse the
combination of "enable_guc" modparam and various debugfs entries.
Let's keep things simple and add a "supported/used/wanted" matrix
(al
On Wed, 24 Jun 2020, Lucas De Marchi wrote:
> Start adding per-platform relevant data into a table that we use for
> initialization. Intention is to keep the different indexes we need (e.g.
> phy, vbt, ddi, etc) and any other differences for each platform in these
> tables so we don't have to keep
Hi Dave & Daniel -
Pretty quiet in the i915 front.
drm-intel-fixes-2020-07-01:
drm/i915 fixes for v5.8-rc4:
- GVT fixes
- Include asm sources for render cache clear batches
BR,
Jani.
The following changes since commit 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68:
Linux 5.8-rc3 (2020-06-28 15:0
== Series Details ==
Series: series starting with [01/26] Revert "drm/i915/gem: Async GPU
relocations only" (rev2)
URL : https://patchwork.freedesktop.org/series/78744/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8661_full -> Patchwork_18018_full
===
Quoting Ruhl, Michael J (2020-07-01 13:39:22)
> > do {
> >- if (drmIoctl(crashme.fd, DRM_IOCTL_GEM_OPEN,
> >&name))
> >+ uint32_t ctx = 0;
> >+
> >+ if (drmIoctl(crashme.fd,
> >+ DRM_IOCTL
On Tue, Jun 30, 2020 at 02:25:30PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional
> divider for 38.4MHz ref clock
> URL : https://patchwork.freedesktop.org/series/78909/
> State : success
Thanks for the reviews pushe
>-Original Message-
>From: Chris Wilson
>Sent: Tuesday, June 30, 2020 5:25 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: igt-...@lists.freedesktop.org; Chris Wilson ;
>Ruhl, Michael J
>Subject: [PATCH i-g-t] i915/gem_close_race: Mix in a contexts and a small
>delay to closure
>
>Keep the o
Op 30-06-2020 om 13:26 schreef Stanislav Lisovskiy:
> We still need "Bump up CDCLK" workaround otherwise getting
> underruns - however currently it blocks 8K as CDCLK = Pixel rate,
> in 8K case would require CDCLK to be around 1 Ghz which is not
> possible.
>
> Signed-off-by: Stanislav Lisovskiy
>
== Series Details ==
Series: drm/i915/dmc: Use firmware v2.02 for RKL
URL : https://patchwork.freedesktop.org/series/78989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8685 -> Patchwork_18057
Summary
---
**SUCCESS*
On Wed, Jul 01, 2020 at 02:57:22PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 30, 2020 at 06:06:54PM -0700, José Roberto de Souza wrote:
> > This fix some possible corruptions.
> >
> > v2:
> > Renamed SLICE_UNIT_LEVEL_CLOCK_GATING_CTL to
> > SLICE_UNIT_LEVEL_CLKGATE_CTL_94D8
>
> Spec people are ge
On Tue, Jun 30, 2020 at 06:06:54PM -0700, José Roberto de Souza wrote:
> This fix some possible corruptions.
>
> v2:
> Renamed SLICE_UNIT_LEVEL_CLOCK_GATING_CTL to
> SLICE_UNIT_LEVEL_CLKGATE_CTL_94D8
Spec people are getting creative with the naming :/
>
> BSpec: 52755
> BSpec: 52890
> Cc: Ville
On Tue, Jun 30, 2020 at 04:33:10PM -0700, Matt Atwood wrote:
> intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
> use before encoder_type is set. This caused GEN11+ to incorrectly strip
> HBR3 from source rates for edp. Move intel_dp_set_source_rates() to
> after encoder_type
== Series Details ==
Series: series starting with drm/i915/gt: Harden the heartbeat against a stuck
driver (rev2)
URL : https://patchwork.freedesktop.org/series/78986/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8684 -> Patchwork_18056
==
== Series Details ==
Series: drm/i915/display: prefer dig_port to reference intel_digital_port
URL : https://patchwork.freedesktop.org/series/78971/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8681_full -> Patchwork_18052_full
== Series Details ==
Series: series starting with drm/i915/gt: Harden the heartbeat against a stuck
driver (rev2)
URL : https://patchwork.freedesktop.org/series/78986/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with drm/i915/gt: Harden the heartbeat against a stuck
driver (rev2)
URL : https://patchwork.freedesktop.org/series/78986/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
812b34bfde95 drm/i915/gt: Harden the heartbeat against a stuck
== Series Details ==
Series: drm/i915/gem: Move obj->lut_list under its own lock
URL : https://patchwork.freedesktop.org/series/78988/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8684 -> Patchwork_18055
Summary
---
The latest firmware contains fix for PSR2 power saving.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display/int
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/tgl: Implement WA 18011464164
URL : https://patchwork.freedesktop.org/series/78965/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8680_full -> Patchwork_18051_full
=
== Series Details ==
Series: series starting with [01/33] drm/i915/gt: Harden the heartbeat against
a stuck driver
URL : https://patchwork.freedesktop.org/series/78987/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8683 -> Patchwork_18054
=
== Series Details ==
Series: series starting with [01/33] drm/i915/gt: Harden the heartbeat against
a stuck driver
URL : https://patchwork.freedesktop.org/series/78987/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [01/33] drm/i915/gt: Harden the heartbeat against
a stuck driver
URL : https://patchwork.freedesktop.org/series/78987/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d499941ea4dc drm/i915/gt: Harden the heartbeat against a stuck
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