Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: More PVC+DG2 workarounds

rsion: 0.6.4 Commit: drm/i915: More PVC+DG2 workarounds Okay! and if I do it manually with "make C=1" I just see the handful of pre-existing / expected warnings, nothing new from this patch. Any ideas what could be going on here? Maybe some quirk of the older v0.6.2 versio

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Correct DSS check for Wa_1308578152

esktop.org/drm/intel/issues/4538 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 > [i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807 > [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 > [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 > [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842 > [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853 > [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 > [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 > [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911 > [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 > [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 > [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 > [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 > [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 > [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 > [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 > [i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721 > [i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 > [i915#6129]: https://gitlab.freedesktop.org/drm/intel/issues/6129 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > > > Build changes > - > > * Linux: CI_DRM_11731 -> Patchwork_104825v1 > > CI-20190529: 20190529 > CI_DRM_11731: 9c92db552b999f75af463bd7ccae9de7165cc0f8 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6510: dacfa80158d586cd0fe322f25f5275f224a946dd @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104825v1: 9c92db552b999f75af463bd7ccae9de7165cc0f8 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104825v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

[Intel-gfx] [PATCH] drm/i915: More PVC+DG2 workarounds

uman Gupta Signed-off-by: Badal Nilawar Signed-off-by: Prathap Kumar Valsan Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++-- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 drivers/gp

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add Wa_14015795083 (rev2)

rm/intel/issues/5176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 > [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 > [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 > [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 > [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 > [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 > [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 > [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 > [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 > [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591 > [i915#5713]: https://gitlab.freedesktop.org/drm/intel/issues/5713 > [i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721 > [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723 > [i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776 > [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903 > [i915#6076]: https://gitlab.freedesktop.org/drm/intel/issues/6076 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 > [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140 > [i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > > > Build changes > - > > * Linux: CI_DRM_11730 -> Patchwork_104760v2 > > CI-20190529: 20190529 > CI_DRM_11730: 5e7f37992081d4600d6329a745ab7edb2ee42bcd @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6510: dacfa80158d586cd0fe322f25f5275f224a946dd @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104760v2: 5e7f37992081d4600d6329a745ab7edb2ee42bcd @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104760v2/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

[Intel-gfx] [PATCH] drm/i915/xehp: Correct steering initialization

uapi") Cc: Balasubramani Vivekanandan Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b7

[Intel-gfx] [PATCH] drm/i915/dg2: Correct DSS check for Wa_1308578152

te internal subslice mask representation from uapi") Reported-by: Balasubramani Vivekanandan Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers

Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_14015795083

On Tue, Jun 07, 2022 at 04:15:42PM +0530, Anshuman Gupta wrote: > i915 must disable Render DOP clock gating globally. > > v2: > - Addressed cosmetic review comments. > > Bspec: 52621 > Cc: Matt Roper > Cc: Badal Nilawar > Signed-off-by: Anshuman Gupt

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015795083

On Mon, Jun 06, 2022 at 11:33:24AM +0530, Anshuman Gupta wrote: > i915 must disable Render DOP clock gating globally. > > B.Spec: 52621 > Cc: Matt Roper > Cc: Badal Nilawar > Signed-off-by: Anshuman Gupta > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + &g

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Catch and log more unexpected values in DG1_MSTR_TILE_INTR

On Mon, Jun 06, 2022 at 12:55:20PM +0100, Tvrtko Ursulin wrote: > > On 27/05/2022 19:42, Matt Roper wrote: > > On Thu, May 26, 2022 at 11:18:17AM +0100, Tvrtko Ursulin wrote: > > > On 25/05/2022 19:05, Matt Roper wrote: > > > > On Wed, May 25, 2022 at 05:03

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pvc: Add register steering

g/drm/intel/issues/4785 > [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 > [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 > [i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011 > > > Build changes > - > > * Linux:

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pvc: GuC depriv applies to PVC

gt; [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842 > [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 > [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 > [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 > [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 > [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 > [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939 > [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 > [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 > [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 > [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 > [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 > [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 > [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591 > [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 > [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 > [i915#5843]: https://gitlab.freedesktop.org/drm/intel/issues/5843 > [i915#6076]: https://gitlab.freedesktop.org/drm/intel/issues/6076 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6139]: https://gitlab.freedesktop.org/drm/intel/issues/6139 > [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > > > Build changes > - > > * Linux: CI_DRM_11723 -> Patchwork_104688v1 > > CI-20190529: 20190529 > CI_DRM_11723: c7b64508e5166dd035e39ea0640f9e1ad840ca0f @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6505: edb1a467fb622b23b927e28ff603fa43851fea97 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104688v1: c7b64508e5166dd035e39ea0640f9e1ad840ca0f @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/adlp: More updates to voltage swing table

On Fri, Jun 03, 2022 at 12:53:08AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/display/adlp: More updates to voltage swing table > URL : https://patchwork.freedesktop.org/series/104661/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_11719_full

[Intel-gfx] [PATCH] drm/i915/pvc: Add register steering

we'll rename the HAS_MSLICES() macro to HAS_MSLICE_STEERING(). PVC hardware still has units referred to as mslices, but there's no register steering based on mslice for this platform. Bspec: 67609 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt.c | 50 ++---

Re: [Intel-gfx] [PATCH v2 0/3] drm/i915/gt: Expose per gt defaults in sysfs

On Thu, Jun 02, 2022 at 04:36:02PM -0700, Dixit, Ashutosh wrote: > On Fri, 27 May 2022 16:41:28 -0700, Matt Roper wrote: > > > > On Thu, May 26, 2022 at 12:00:42PM -0700, Ashutosh Dixit wrote: > > > Create a gt/gtN/.defaults directory (similar to > > > eng

[Intel-gfx] [PATCH] drm/i915/pvc: Add Wa_16015675438:pvc

y/expected. Cc: Stuart Summers Cc: Lucas De Marchi Signed-off-by: Badal Nilawar Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 drivers/gpu/drm/i915/gt/uc/i

[Intel-gfx] [PATCH] drm/i915/pvc: GuC depriv applies to PVC

We missed this setting in the initial device info patch's definition of XE_HPC_FEATURES. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 047a6e3

Re: [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions

he audio enable > bit being in the DP or HDMI registers on older platforms. > > Signed-off-by: Jani Nikula Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/display/intel_audio.c| 1 + > .../gpu/drm/i915/display/intel_audio_regs.h | 160 ++ > driv

Re: [Intel-gfx] [PATCH] drm/i915/display/fbc: Do not apply WA 22014263786 to DG2

On Thu, Jun 02, 2022 at 01:17:30PM -0700, José Roberto de Souza wrote: > This workaround brings some regressions to DG2 and if really necessary > for DG2 an alternative workaround will be implemented. > > BSpec: 54077 > Signed-off-by: José Roberto de Souza Reviewed

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/adlp: More updates to voltage swing table

desktop.org/drm/intel/issues/6135 > [i915#6136]: https://gitlab.freedesktop.org/drm/intel/issues/6136 > [i915#6137]: https://gitlab.freedesktop.org/drm/intel/issues/6137 > [i915#6138]: https://gitlab.freedesktop.org/drm/intel/issues/6138 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/6

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add extra registers to GPU error dump

1 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 > [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/52

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for i915: SSEU handling updates

176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 > [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264 > [i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266 > [i915#5286]: h

[Intel-gfx] [PATCH] drm/i915: Add extra registers to GPU error dump

d beyond. Most of these registers have existed since earlier platforms (e.g., gen6 or gen7) but were initially introduced only for a subset of the platforms' engines; gen11 seems to be where they became available on all engines. Signed-off-by: Stuart Summers Signed-off-by: Matt Roper --- d

[Intel-gfx] [PATCH v5 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling

opping the multi-slice logic from gen11+ platforms. v2: - Promote drm_dbg to drm_WARN_ON if the slice fuse register reports unexpected fusing. (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: Matt Roper Acked-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_sseu.c | 76 +

[Intel-gfx] [PATCH v5 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK

meaningful when used on multi-tile platforms where each tile will have its own masks. Signed-off-by: Matt Roper Acked-by: Tvrtko Ursulin Acked-by: Lionel Landwerlin # mesa --- drivers/gpu/drm/i915/i915_getparam.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

ne of the inline functions. (Bala) - Change the local variable in intel_slicemask_from_xehp_dssmask() from u16 to 'unsigned long' to make it a bit more future-proof. Cc: Tvrtko Ursulin Cc: Balasubramani Vivekanandan Signed-off-by: Matt Roper Acked-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gem/i

[Intel-gfx] [PATCH v5 1/6] drm/i915/xehp: Use separate sseu init function

- Add has_xehp_dss flag Signed-off-by: Matt Roper Acked-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_sseu.c | 86 drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++ 2 files changed, 54 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu

[Intel-gfx] [PATCH v5 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format

for every single DSS, but the code is simpler without it. (Tvrtko) v3: - Mask down EUs passed to sseu_set_eus at the callsite rather than inside the function. (Tvrtko) - Eliminate sseu->eu_stride and calculate it when needed. (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: Matt Roper A

[Intel-gfx] [PATCH v5 0/6] i915: SSEU handling updates

_SS_FUSE_BITS in one of the inline functions. (Bala) - Change the local variable in intel_slicemask_from_xehp_dssmask() from u16 to 'unsigned long' to make it a bit more future-proof. - Incorporate ack's received from Tvrtko and Lionel. Cc: Tvrtko Ursulin Cc: Balasubramani Vivekan

[Intel-gfx] [PATCH v5 6/6] drm/i915/pvc: Add SSEU changes

PVC splits the mask of enabled DSS over two registers. It also changes the meaning of the EU fuse register such that each bit represents a single EU rather than a pair of EUs. Signed-off-by: Matt Roper Acked-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu

Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

On Wed, Jun 01, 2022 at 01:48:56PM +0530, Balasubramani Vivekanandan wrote: > On 23.05.2022 13:45, Matt Roper wrote: > > As with EU masks, it's easier to store subslice/DSS masks internally in > > a format that's more natural for the driver to work with, and then only >

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for i915: PVC steppings and initial workarounds

On Sat, May 28, 2022 at 01:36:06PM +, Patchwork wrote: > == Series Details == > > Series: i915: PVC steppings and initial workarounds > URL : https://patchwork.freedesktop.org/series/104461/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_11705_full -> Patchwork_10

Re: [Intel-gfx] [PATCH 3/7] drm/i915/dg2: DG2 MBD config

each other. I'm not too familiar with the feature you're working on here. Is there a way we can detect whether it's supported by querying the pcode? Or what happens if you send your pcode request on a platform that doesn't support it? Do you just get a regular error back so that the driver would know to give up and move on, or would it actually cause some kind of behavioral problem? Matt > Thanks, > Anshuman Gupta. > > > > BR, > > Jani. > > > > > #define IS_ADLS_RPLS(dev_priv) \ > > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, > > INTEL_SUBPLATFORM_RPL) > > > #define IS_ADLP_N(dev_priv) \ > > > > -- > > Jani Nikula, Intel Open Source Graphics Center -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

Re: [Intel-gfx] [PATCH v2 0/3] drm/i915/gt: Expose per gt defaults in sysfs

rs/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 19 ++++-- > 6 files changed, 103 insertions(+), 10 deletions(-) > > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Catch and log more unexpected values in DG1_MSTR_TILE_INTR

On Thu, May 26, 2022 at 11:18:17AM +0100, Tvrtko Ursulin wrote: > > On 25/05/2022 19:05, Matt Roper wrote: > > On Wed, May 25, 2022 at 05:03:13PM +0100, Tvrtko Ursulin wrote: > > > > > > On 24/05/2022 18:51, Matt Roper wrote: > > > > On Tue, May 24, 2022

Re: [Intel-gfx] [CI] Revert "drm/i915: Add relocation exceptions for two other platforms"

CI. > > Signed-off-by: Lucas De Marchi Acked-by: Matt Roper > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 +-- > 1 file changed, 5 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > b/drivers

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing table

On Thu, May 26, 2022 at 03:22:13PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing table > URL : https://patchwork.freedesktop.org/series/104393/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_

[Intel-gfx] [PATCH 2/2] drm/i915/pvc: Add initial PVC workarounds

From: Stuart Summers Bspec: 64027 Signed-off-by: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 ++--- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915/pvc: Extract stepping information from PCI revid

ted by specific bitfields within the PCI revision ID, and we shouldn't make assumptions about the non-CT, non-BD bits staying 0. Let's update our stepping code accordingly. Bspec: 44484 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 13 ++ drivers/gpu/d

[Intel-gfx] [PATCH 0/2] i915: PVC steppings and initial workarounds

Matt Roper (1): drm/i915/pvc: Extract stepping information from PCI revid Stuart Summers (1): drm/i915/pvc: Add initial PVC workarounds drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 61

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hwconfig: Future-proof platform checks

On Wed, May 25, 2022 at 08:23:19AM -0700, Matt Roper wrote: > On Wed, May 25, 2022 at 06:41:11AM +, Patchwork wrote: > > == Series Details == > > > > Series: drm/i915/hwconfig: Future-proof platform checks > > URL : https://patchwork.freedesktop.org/series/

Re: [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL

t; > Cc: Matt. > > This also makes the hdmi link rate check in the same function redundant. > > Reviewed-by: Jani Nikula > I don't remember any specific reason the code was written this way, so the change looks okay to me. Acked-by: Matt Roper > > > >

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Catch and log more unexpected values in DG1_MSTR_TILE_INTR

On Wed, May 25, 2022 at 05:03:13PM +0100, Tvrtko Ursulin wrote: > > On 24/05/2022 18:51, Matt Roper wrote: > > On Tue, May 24, 2022 at 10:43:39AM +0100, Tvrtko Ursulin wrote: > > > From: Tvrtko Ursulin > > > > > > Catch and log any garbage in the

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hwconfig: Future-proof platform checks

> [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 > [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 > [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 > [i915#3825]: https://gi

Re: [Intel-gfx] [PATCH v3] drm/i915/dg2: Support 4k@30 on HDMI

> v2: As per the algorithm, set MPLLB VCO range control bits to 3, > in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt) > > v3: Fix typo. (Ankit) > > Signed-off-by: Vandita Kulkarni > Signed-off-by: Ankit Nautiyal Reviewed-by: Matt Roper and applied to drm-intel-next. Thanks f

[Intel-gfx] [PATCH] drm/i915/hwconfig: Future-proof platform checks

na Sripada Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c index 5aaa3948de74..4781fccc2687 10

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hwconfig: Report no hwconfig support on ADL-N

el/issues/4538 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#46

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Ponte Vecchio (rev4)

top.org/drm/intel/issues/3734 > [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 > [i915#4070]: https://gitlab.freedesktop.org

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Catch and log more unexpected values in DG1_MSTR_TILE_INTR

On Tue, May 24, 2022 at 10:43:39AM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Catch and log any garbage in the register, including no tiles marked, or > multiple tiles marked. > > Signed-off-by: Tvrtko Ursulin > Cc: Matt Roper > --- > We caught garbage

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2)

; IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ > git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > e3100146e9db drm/

Re: [Intel-gfx] [PATCH] drm/i915/hwconfig: Report no hwconfig support on ADL-N

On Mon, May 23, 2022 at 01:21:16PM +0530, Balasubramani Vivekanandan wrote: > ADL-N being a subplatform of ADL-P, it lacks support for hwconfig > table. Explicit check added to skip ADL-N. > > Signed-off-by: Balasubramani Vivekanandan > Reviewed-by: Matt Roper > --- >

[Intel-gfx] [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

subslice ID exceed sseu->max_[sub]slices; various loops in the driver are expected to exceed these, so we should just silently return 'false.' Cc: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +- drivers/gpu/drm/i915

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Enable DC5

/5122 > [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 > [i915#5681]: https://gitlab.freedesktop.org/drm/intel/issues/5681 > [i915#5704]: https://gitlab.freedesktop.org/drm/intel/issues/5704 > > > Build changes > - > > * Linux: CI_DRM_11681 -> Patchwork_104233v1 > > CI-20190529: 20190529 > CI_DRM_11681: ba369855d857f98fe5a1da1a107006891c7d37e0 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6483: 43e509f408d4a5bcc5070f6b84da42a7c3801e8d @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104233v1: ba369855d857f98fe5a1da1a107006891c7d37e0 @ > git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > 66e777973d7a drm/i915/dg2: Enable DC5 > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104233v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

[Intel-gfx] [PATCH v4 0/6] i915: SSEU handling updates

915_MAX_SS_FUSE_BITS around directly to bitmap operations. - Improved debugfs / dmesg reporting for Xe_HP dumps - Various assertion check improvements. Cc: Tvrtko Ursulin Matt Roper (6): drm/i915/xehp: Use separate sseu init function drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]

[Intel-gfx] [PATCH v4 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format

for every single DSS, but the code is simpler without it. (Tvrtko) v3: - Mask down EUs passed to sseu_set_eus at the callsite rather than inside the function. (Tvrtko) - Eliminate sseu->eu_stride and calculate it when needed. (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: Matt Roper --

[Intel-gfx] [PATCH v4 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling

opping the multi-slice logic from gen11+ platforms. v2: - Promote drm_dbg to drm_WARN_ON if the slice fuse register reports unexpected fusing. (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_sseu.c | 76 +--- 1 file c

[Intel-gfx] [PATCH v4 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

EU info. (Tvrtko) - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c| 4 +- drivers/gpu/drm/i915/gt/intel_gt.c

[Intel-gfx] [PATCH v4 1/6] drm/i915/xehp: Use separate sseu init function

- Add has_xehp_dss flag Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_sseu.c | 86 drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++ 2 files changed, 54 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i9

[Intel-gfx] [PATCH v4 6/6] drm/i915/pvc: Add SSEU changes

PVC splits the mask of enabled DSS over two registers. It also changes the meaning of the EU fuse register such that each bit represents a single EU rather than a pair of EUs. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c

[Intel-gfx] [PATCH v4 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK

meaningful when used on multi-tile platforms where each tile will have its own masks. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_getparam.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c ind

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK

On Fri, May 20, 2022 at 10:15:32AM +0100, Tvrtko Ursulin wrote: > > On 17/05/2022 04:20, Matt Roper wrote: > > Slice/subslice/EU information should be obtained via the topology > > queries provided by the I915_QUERY interface; let's turn off support for > > the old

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Support 4k@30 on HDMI

tate dg2_hdmi_594 = { > .clock = 594000, > .ref_control = > @@ -551,6 +581,7 @@ static const struct intel_mpllb_state * const > dg2_hdmi_tables[] = { > &dg2_hdmi_27_0, > &dg2_hdmi_74_25, > &dg2_hdmi_148_5, > + &dg2_hdmi_297, > &dg2_hdmi_594, > NULL, > }; > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Extend Wa_22010954014 to DG2-G11 and DG2-G12

On Wed, May 18, 2022 at 10:14:33PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dg2: Extend Wa_22010954014 to DG2-G11 and DG2-G12 > URL : https://patchwork.freedesktop.org/series/104104/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_11668_full

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Add workaround 22014600077 (rev2)

lab.freedesktop.org/drm/intel/issues/4939 > [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958 > [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 > [i915#5072]: https:

Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add workaround 22014600077

PGPU_PREEMPTION REG_BIT(2) > > #define GEN10_CACHE_MODE_SS _MMIO(0xe420) > +#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10) The whitespace on this line is still wrong. I guess we can fix that up while applying the pat

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev4)

On Wed, May 18, 2022 at 12:34:11AM +, Patchwork wrote: > == Series Details == > > Series: i915: SSEU handling updates (rev4) > URL : https://patchwork.freedesktop.org/series/103244/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11666_full -> Patchwork_103244v4_fu

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Extend Wa_22010954014 to DG2-G11 and DG2-G12

On Tue, May 17, 2022 at 01:13:38PM -0700, Swathi Dhanavanthri wrote: > Signed-off-by: Swathi Dhanavanthri Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/in

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add workaround 22014600077

rification */ Matt > +true); > + } > + > if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || > IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { > /* > -- > 2.20.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev4)

21c3cdb @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ > git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > f79229c733a2 drm/i915/pvc: Add SSEU changes > 995c1647a0d6 drm/i915/sseu: Disassociate internal subslice mask > representation from uapi > 6e28799e6216 drm/i915/sseu: Don't try to store EU mask internally in UAPI > format > 95fd2c3dc7e9 drm/i915/sseu: Simplify gen11+ SSEU handling > 9db3639b067c drm/i915/xehp: Drop GETPARAM lookups of > I915_PARAM_[SUB]SLICE_MASK > 0f70c4e7a760 drm/i915/xehp: Use separate sseu init function > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation

[Intel-gfx] [PATCH v3 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

need a single bitmask. However we already know that this mask is eventually going to grow too large for a simple u64 to hold, so we'll represent it in a manner that can be operated on by the utilities in linux/bitmap.h. v3: - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status() Cc

[Intel-gfx] [PATCH v2 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling

opping the multi-slice logic from gen11+ platforms. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_sseu.c | 80 ++-- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_ss

[Intel-gfx] [PATCH v2 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format

for every single DSS, but the code is simpler without it. (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_sseu.c | 77 +++- drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +++- drivers/gpu/drm/i915/i915_query.c| 8 +-- 3 files ch

[Intel-gfx] [PATCH v2 6/6] drm/i915/pvc: Add SSEU changes

PVC splits the mask of enabled DSS over two registers. It also changes the meaning of the EU fuse register such that each bit represents a single EU rather than a pair of EUs. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c

[Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK

meaningful when used on multi-tile platforms where each tile will have its own masks. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_getparam.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c ind

[Intel-gfx] [PATCH v2 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

need a single bitmask. However we already know that this mask is eventually going to grow too large for a simple u64 to hold, so we'll represent it in a manner that can be operated on by the utilities in linux/bitmap.h. Cc: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/g

[Intel-gfx] [PATCH v2 1/6] drm/i915/xehp: Use separate sseu init function

- Add has_xehp_dss flag Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_sseu.c | 86 drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++ 2 files changed, 54 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i9

[Intel-gfx] [PATCH v2 0/6] i915: SSEU handling updates

bit value, so when subslice masks begin to exceed 32-bits (on PVC), it simply can't return the entire mask. * The GETPARAM ioctl doesn't have a way to give sensible information for multi-tile devices. Cc: Tvrtko Ursulin Matt Roper (6): drm/i915/xehp: Use separate sseu i

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable Tile4 tiling mode

&t->buffers[2], t->hole + t->align, > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 556bca3be804..246ab8f7bf57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Introduce Ponte Vecchio (rev4)

ps://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 > [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 > [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 > [i915#3070]: https://gitl

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Introduce Ponte Vecchio (rev4)

tlab.freedesktop.org/drm/intel/issues/5879 > [i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950 > > > Build changes > - > > * Linux: CI_DRM_11632 -> Patchwork_103443v4 > > CI-20190529: 20190529 > CI_DRM_11632: f6d6ced5a4acd1bc7

[Intel-gfx] [PATCH v3 5/5] drm/i915/guc: XEHPSDV and PVC do not use HuC

From: Daniele Ceraolo Spurio Disable HuC loading since it is not used on these platforms. Cc: Stuart Summers Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 1/5] drm/i915/uncore: Reorganize and document shadow and forcewake tables

this with true kerneldoc. But this is a good intermediate step to help clarify the behavior a bit. Cc: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_uncore.c | 125 ++-- 1 file changed, 80 insertions(+), 45 deletions(-) diff --git a/drivers/gp

[Intel-gfx] [PATCH v3 4/5] drm/i915/pvc: Add new BCS engines to GuC engine list

Intialize ADS system info to reflect the availablity of new BCS engines Original-author: CQ Tang Cc: Stuart Summers Cc: John Harrison Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- drivers/gpu/drm/i915/i915_drv.h| 2 ++ 2 files changed, 3

[Intel-gfx] [PATCH v3 2/5] drm/i915/pvc: Add forcewake support

Add PVC's forcewake ranges. v2: - Drop replicated comment completely; move general cleanup of the documentation to a separate patch. Bspec: 67609 Cc: Daniele Ceraolo Spurio Cc: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_uncore.c

[Intel-gfx] [PATCH v3 3/5] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL

LACKS_3D_PIPELINE checks with !HAS_3D_PIPELINE and add has_3d_pipeline to all platforms except PVC. (Lucas) Bspec: 47112 Cc: Lucas De Marchi Signed-off-by: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 -- drivers/gpu/drm/i915/gt

[Intel-gfx] [PATCH v3 0/5] i915: Introduce Ponte Vecchio

Daniele Ceraolo Spurio (1): drm/i915/guc: XEHPSDV and PVC do not use HuC Matt Roper (3): drm/i915/uncore: Reorganize and document shadow and forcewake tables drm/i915/pvc: Add forcewake support drm/i915/pvc: Add new BCS engines to GuC engine list Stuart Summers (1): drm/i915/pvc: Remove addi

Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL

On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote: > On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote: > > From: Stuart Summers > > > > Although we already strip 3D-specific flags from PIPE_CONTROL > > instructions when submitting to a com

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Ponte Vecchio (rev3)

ues/4103 > [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278 > [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 > [i915#431

Re: [Intel-gfx] [PATCH 5/5] drm/i915/sseu: Disassociate internal subslice mask representation from uapi

On Thu, Apr 28, 2022 at 01:18:42PM +0100, Tvrtko Ursulin wrote: > > Hi, > > On 28/04/2022 00:07, Matt Roper wrote: > > Rather than storing subslice masks internally as u8[] (inside the sseu > > structure) and u32 (everywhere else), let's move over to using an >

Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL

On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote: > On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote: > > From: Stuart Summers > > > > Although we already strip 3D-specific flags from PIPE_CONTROL > > instructions when submitting to a com

Re: [Intel-gfx] [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines

On Fri, May 06, 2022 at 08:21:46AM +0100, Tvrtko Ursulin wrote: > > On 05/05/2022 21:59, Matt Roper wrote: > > On Tue, May 03, 2022 at 09:05:43AM +0100, Tvrtko Ursulin wrote: > > > > > > On 02/05/2022 17:34, Matt Roper wrote: > > > > This patch ad

[Intel-gfx] [PATCH v2 06/12] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine

atch takes the allocation of the stack and makes it dynamic instead. v2 (MattR): - Minor cosmetic changes: re-sort definition and allocate using kmalloc_array(). (Tvrtko) Cc: Tvrtko Ursulin Signed-off-by: John Harrison Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza --- drive

[Intel-gfx] [PATCH v2 08/12] drm/i915/pvc: Engine definitions for new copy engines

ar to other engnes. (Prathap) - Move GVT change to avoid u16 overflow to its own patch. (Tvrtko) Original-author: CQ Tang Cc: Tvrtko Ursulin Cc: Prathap Kumar Valsan Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/gt/intel_engine_cs.c

[Intel-gfx] [PATCH v2 11/12] drm/i915/pvc: skip all copy engines from aux table invalidate

From: Lucas De Marchi As we have more copy engines now, mask all of them from aux table invalidate. v2 (MattR): - Use I915_MAX_BCS to determine mask rather than hardcoding BCS8. (Prathap) Cc: Prathap Kumar Valsan Signed-off-by: Lucas De Marchi Signed-off-by: Matt Roper Reviewed-by: José

[Intel-gfx] [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines

variable. (Tvrtko) Bspec: 44483 Cc: Matt Roper Cc: Tvrtko Ursulin Signed-off-by: Lucas De Marchi Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++ 1 file changed, 29 insertions(+) diff --git a/drivers

[Intel-gfx] [PATCH v2 10/12] drm/i915/pvc: Reset support for new copy engines

Add the reset support for new copy engines in PVC. Bspec: 52549 Original-author: CQ Tang Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza Reviewed-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 44

[Intel-gfx] [PATCH v2 01/12] drm/i915/uncore: Reorganize and document shadow and forcewake tables

this with true kerneldoc. But this is a good intermediate step to help clarify the behavior a bit. Cc: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_uncore.c | 125 ++-- 1 file changed, 80 insertions(+), 45 deletions(-) diff --git a/drivers/gp

[Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL

: Stuart Summers Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 -- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++-- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 3 ++- drivers

[Intel-gfx] [PATCH v2 09/12] drm/i915/pvc: Interrupt support for new copy engines

Add the interrupt handler support for new copy engines. Bspec: 54030 Original-author: CQ Tang Signed-off-by: Matt Roper Reviewed-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 2 files changed, 20

[Intel-gfx] [PATCH v2 00/12] i915: Introduce Ponte Vecchio

usage in reset selftest with extra blitter engine Lucas De Marchi (2): drm/i915/pvc: skip all copy engines from aux table invalidate drm/i915/pvc: read fuses for link copy engines Matt Roper (7): drm/i915/uncore: Reorganize and document shadow and forcewake tables drm/i915/pvc: Add fo

[Intel-gfx] [PATCH v2 04/12] drm/i915/pvc: Read correct RP_STATE_CAP register

The SoC registers, including RP_STATE_CAP, have moved to a new location in GTTMMADR on Ponte Vecchio. We need to update the register offset accordingly. Cc: Rodrigo Vivi Signed-off-by: Matt Roper Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++- drivers/gpu/drm/i915

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