Hi Arnd, Mark and others,
this may not be worth arguing but I'm currently fighting excessive
workarounds in another area and so this triggers me, so I have to make
a remark ;-)
On Tue, 5 May 2020 15:25:56 +0100
Mark Rutland wrote:
> On Tue, May 05, 2020 at 04:12:36PM +0200, Arnd Bergmann
avoid code churn,
so how about we step back and debug it first?
Which version of gcc are you using and what .config?
I've tried:
Linux version 5.7.0-rc2 (gcc version 10.0.1 20200505 (prerelease) (GCC)
CONFIG_UNWINDER_ORC=y
# CONFIG_RETPOLINE is not set
and objtool didn't complain.
I would like to re
On 5/5/20 9:55 AM, Mickaël Salaün wrote:
>
>
> On 05/05/2020 17:44, Randy Dunlap wrote:
>> On 5/5/20 8:31 AM, Mickaël Salaün wrote:
>>> diff --git a/security/Kconfig b/security/Kconfig
>>> index cd3cc7da3a55..d8fac9240d14 100644
>>> --- a/security/Kconfig
>>> +++ b/security/Kconfig
>>> @@ -230,6
On Tue, May 5, 2020 at 6:36 AM Geert Uytterhoeven
wrote:
>
> The standard DT property name is "interrupt-names".
>
> Fixes: fd913ef7ce619467 ("Bluetooth: btusb: Add out-of-band wakeup support")
> Signed-off-by: Geert Uytterhoeven
> Acked-by: Rob Herring
If it matters:
Reviewed-by: Brian
The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power
state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary
power. On Windows ASPM L1 is enabled on the device and its upstream
bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of
power.
In short,
On 05/05/2020 12:55, Zhen Lei wrote:
When I studied the code of mm/swap, I found "1 << (PAGE_SHIFT - 9)" appears
many times. So I try to clean up it.
1. Replace "1 << (PAGE_SHIFT - 9)" or similar with SECTORS_PER_PAGE
2. Replace "PAGE_SHIFT - 9" with SECTORS_PER_PAGE_SHIFT
3. Replace "9" with
On Tue, 5 May 2020 at 18:05, Jerome Brunet wrote:
>
>
> On Tue 05 May 2020 at 10:17, Ulf Hansson wrote:
>
> > [...]
> >
> >> >> > +
> >> >> > + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> >> >> > +onecell_data);
> >> >>
> >> >> I
Adding Stefan Raspl, who has done a lot of kvm_stat work in the past.
On 05.05.20 19:21, Paolo Bonzini wrote:
> On 05/05/20 19:07, David Rientjes wrote:
>>> I am totally in favor of having a binary format, but it should be
>>> introduced as a separate series on top of this one---and preferably by
On Tue, May 05, 2020 at 07:05:53PM +0200, SeongJae Park wrote:
> On Tue, 5 May 2020 09:37:42 -0700 Eric Dumazet wrote:
>
> >
> >
> > On 5/5/20 9:31 AM, Eric Dumazet wrote:
> > >
> > >
> > > On 5/5/20 9:25 AM, Eric Dumazet wrote:
> > >>
> > >>
> > >> On 5/5/20 9:13 AM, SeongJae Park wrote:
>
Files can be mmap'ed read/write and later changed to execute to circumvent
IMA's mmap appraise policy rules. Due to locking issues (mmap semaphore
would be taken prior to i_mutex), files can not be measured or appraised at
this point. Eliminate this integrity gap, by denying the mprotect
On Tue, 5 May 2020 16:02:25 +0200 Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> Provide devm_register_netdev() - a device resource managed variant
> of register_netdev(). This new helper will only work for net_device
> structs that have a parent device assigned and are devres
On Tue, May 5, 2020 at 8:14 AM Andy Shevchenko
wrote:
>
> On Mon, May 04, 2020 at 06:14:43PM -0700, Jesse Brandeburg wrote:
> > On Mon, 4 May 2020 12:51:12 -0700
> > Nick Desaulniers wrote:
> >
> > > Sorry for the very late report. It turns out that if your config
> > > tickles
On Mon, May 4, 2020 at 4:25 PM Daniel Kiper wrote:
>
> Otherwise the kernel does not know its state and cannot enable various
> security features depending on UEFI Secure Boot.
I think this needs more context. If the kernel is loaded via the EFI
boot stub, the kernel is aware of the UEFI secure
On Tue, May 05, 2020 at 09:37:42AM -0700, Eric Dumazet wrote:
>
>
> On 5/5/20 9:31 AM, Eric Dumazet wrote:
> >
> >
> > On 5/5/20 9:25 AM, Eric Dumazet wrote:
> >>
> >>
> >> On 5/5/20 9:13 AM, SeongJae Park wrote:
> >>> On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet
> >>> wrote:
> >>>
>
On Tue, May 05, 2020 at 07:55:41PM +0800, Zhen Lei wrote:
> +++ b/mm/swapfile.c
> @@ -177,8 +177,8 @@ static int discard_swap(struct swap_info_struct *si)
>
> /* Do not discard the swap header page! */
> se = first_se(si);
> - start_block = (se->start_block + 1) << (PAGE_SHIFT -
On Tue, May 05, 2020 at 09:25:06AM -0700, Eric Dumazet wrote:
>
>
> On 5/5/20 9:13 AM, SeongJae Park wrote:
> > On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet wrote:
> >
> >> On Tue, May 5, 2020 at 8:47 AM SeongJae Park wrote:
> >>>
> >>> On Tue, 5 May 2020 08:20:50 -0700 Eric Dumazet
> >>>
clang points out that building without IPv6 would lead to returning
an uninitialized variable if a packet with family!=AF_INET is
passed into bareudp_udp_encap_recv():
drivers/net/bareudp.c:139:6: error: variable 'err' is used uninitialized
whenever 'if' condition is false
On 05/05/20 19:07, David Rientjes wrote:
>> I am totally in favor of having a binary format, but it should be
>> introduced as a separate series on top of this one---and preferably by
>> someone who has already put some thought into the problem (which
>> Emanuele and I have not, beyond ensuring
Hi Linus,
Collected fixes for PDx96 so far.
Thanks,
With Best Regards,
Andy Shevchenko
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
> Hi!
>
>> +#define AW2013_NAME "aw2013"
> That's not really useful define. Make it NAME? Drop it?
Will drop it as well as (unnecessary) lines it is used in.
>> +#define AW2013_TIME_STEP 130
> I'd add comment with /* units */.
Will add.
>> +#define STATE_OFF 0
>> +#define STATE_KEEP 1
>>
This patch defers its probe when the expected reset control is not
yet ready. This patch also handles properly all errors cases at probe
time.
Signed-off-by: Christophe Kerello
---
Changes in v3:
- rename labels used on errors
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 17 +++--
1
This patch adds the documentation of the device tree bindings for the STM32
FMC2 EBI controller.
Signed-off-by: Christophe Kerello
---
Changes in v3:
- pattern name has been modified
- vendor properties have been modified
- s/_/-/
- add unit suffix (-ns) on timing properties
The driver adds the support for the STMicroelectronics FMC2 EBI controller
found on STM32MP SOCs.
Signed-off-by: Christophe Kerello
---
Changes in v3:
- Move in memory folder
- Merge MFD and BUS drivers to avoid a MFD driver
drivers/memory/Kconfig | 10 +
drivers/memory/Makefile
These bindings can be used on SOCs where the FMC2 NAND controller is
in standalone. In case that the FMC2 embeds 2 controllers (an external
bus controller and a raw NAND controller), the register base and the
clock will be defined in the parent node. It is the reason why the
register base address
The FMC2 functional block makes the interface with: synchronous and
asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
peripherals) and NAND flash memories.
Its main purposes are:
- to translate AXI transactions into the appropriate external device
protocol
- to meet
This patch renames functions and local variables.
This cleanup is done to get all functions starting by stm32_fmc2_nfc
in the FMC2 raw NAND driver when all functions will start by
stm32_fmc2_ebi in the FMC2 EBI driver.
Signed-off-by: Christophe Kerello
Reviewed-by: Miquel Raynal
---
Changes in
This patch removes custom macros and uses FIELD_PREP and FIELD_GET macros.
Signed-off-by: Christophe Kerello
Reviewed-by: Miquel Raynal
---
Changes in v3:
- add Miquel reviewed-by tag
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 177 -
1 file changed, 85
FMC2 EBI support has been added. Common resources (registers base
and clock) are now shared between the 2 drivers. It means that the
common resources should now be found in the parent device when EBI
node is available.
Signed-off-by: Christophe Kerello
---
drivers/mtd/nand/raw/Kconfig
This patch uses regmap APIs to access all FMC2 registers.
Signed-off-by: Christophe Kerello
Reviewed-by: Miquel Raynal
---
Changes in v3:
- add Miquel reviewed-by tag
drivers/mtd/nand/raw/Kconfig | 2 +
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 268
This patch removes the constant FMC2_TIMEOUT_US.
FMC2_TIMEOUT_MS will be used each time that we need to wait (except
when the timeout value is set by the framework).
It was seen, during stress tests with the sequencer in an overloaded
system, that we could be close to 1 second, even if we never
Remove inline comments that are useless since function label are
self explanatory.
Signed-off-by: Christophe Kerello
Reviewed-by: Miquel Raynal
---
Changes in v3:
- add Miquel reviewed-by tag
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 40 --
1 file changed, 40
On Tue, May 05, 2020 at 05:22:42PM +0100, Will Deacon wrote:
> On Tue, May 05, 2020 at 04:04:21PM +0100, Sudeep Holla wrote:
> > On Tue, May 05, 2020 at 04:08:08PM +0200, Arnd Bergmann wrote:
> > > When CONFIG_ARM_PSCI_FW is disabled but CONFIG_HAVE_ARM_SMCCC is enabled,
> > > arm-scmi runs into a
On Mon, 4 May 2020 17:01:23 -0300
Jason Gunthorpe wrote:
> On Mon, May 04, 2020 at 01:35:52PM -0600, Alex Williamson wrote:
>
> > Ok, this all makes a lot more sense with memory_lock still in the
> > picture. And it looks like you're not insisting on the wait_event, we
> > can block on
On 05/05/20 17:47, Peter Xu wrote:
> KVM_CAP_SET_GUEST_DEBUG should be supported for x86 however it's not declared
> as supported. My wild guess is that userspaces like QEMU are using "#ifdef
> KVM_CAP_SET_GUEST_DEBUG" to check for the capability instead, but that could
> be
> wrong because the
On Tue, May 05, 2020 at 05:21:36PM +0100, Mark Rutland wrote:
> On Tue, May 05, 2020 at 04:04:21PM +0100, Sudeep Holla wrote:
> > Hi Arnd,
> >
> > On Tue, May 05, 2020 at 04:08:08PM +0200, Arnd Bergmann wrote:
> > > When CONFIG_ARM_PSCI_FW is disabled but CONFIG_HAVE_ARM_SMCCC is enabled,
> > >
On Tue, 5 May 2020 at 17:29, Arnd Bergmann wrote:
>
> On Tue, May 5, 2020 at 5:20 PM 'Marco Elver' via Clang Built Linux
> wrote:
>
> > > --- a/lib/Kconfig.kcsan
> > > +++ b/lib/Kconfig.kcsan
> > > @@ -5,7 +5,7 @@ config HAVE_ARCH_KCSAN
> > >
> > > menuconfig KCSAN
> > > bool "KCSAN:
On Tue, 5 May 2020, Paolo Bonzini wrote:
> >>> Since this is becoming a generic API (good!!), maybe we can discuss
> >>> possible ways to optimize gathering of stats in mass?
> >> Sure, the idea of a binary format was considered from the beginning in
> >> [1], and it can be done either together
On Tue, 5 May 2020 09:37:42 -0700 Eric Dumazet wrote:
>
>
> On 5/5/20 9:31 AM, Eric Dumazet wrote:
> >
> >
> > On 5/5/20 9:25 AM, Eric Dumazet wrote:
> >>
> >>
> >> On 5/5/20 9:13 AM, SeongJae Park wrote:
> >>> On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet
> >>> wrote:
> >>>
> On
Em Tue, May 05, 2020 at 11:57:18AM -0500, Daniel Díaz escreveu:
> Hello!
>
> On Tue, 5 May 2020 at 11:37, Arnaldo Carvalho de Melo
> wrote:
> >
> > Em Mon, May 04, 2020 at 02:07:56PM -0500, Daniel Díaz escreveu:
> > > Hello!
> > >
> > > On Fri, 24 Apr 2020 at 09:10, Andreas Gerstmayr
> > >
On Tue, May 05, 2020 at 11:50:28PM +0800, Jia-Ju Bai wrote:
> In alloc_rx_resources():
> sge->respQ.entries =
> pci_alloc_consistent(pdev, size, >respQ.dma_addr);
>
> Thus, "sge->respQ.entries" is a DMA value, and it is assigned to
> "e" in process_pure_responses():
> struct sge
On 05/05/20 18:53, Jim Mattson wrote:
>>> Since this is becoming a generic API (good!!), maybe we can discuss
>>> possible ways to optimize gathering of stats in mass?
>> Sure, the idea of a binary format was considered from the beginning in
>> [1], and it can be done either together with the
A test with the command below gives for example this error:
arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml: phy@0:
'#phy-cells' is a required property
The phy nodename is normally used by a phy-handle.
This node is however compatible with
"ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"
On Tue, May 05, 2020 at 10:19:31AM -0600, shuah wrote:
> On 5/5/20 9:43 AM, shuah wrote:
> > On 5/5/20 9:36 AM, Takashi Iwai wrote:
> > > On Tue, 05 May 2020 17:30:07 +0200,
> > > shuah wrote:
> > > >
> > > > On 5/5/20 9:25 AM, shuah wrote:
> > > > > On 5/4/20 11:57 AM, Greg Kroah-Hartman wrote:
On Tue, May 5, 2020 at 8:24 AM Arnd Bergmann wrote:
>
> Linus, let me know if you would like me to Cc you on the other gcc-10
> warning fixes I have and possibly apply some directly.
Sure. If you have any of the "trivially correct, and doesn't make code
look worse", push them my way.
I only did
Users of the XDMA engine need a way to reset it if something goes wrong.
Problems on the host side, or user error, such as incorrect host
address, may result in the DMA operation never completing and no way to
determine what went wrong. Therefore, add an ioctl to reset the engine
so that users can
This series adds a driver to control the Aspeed XDMA engine embedded in the
AST2500 and AST2600. The XDMA engine performs automatic DMA operations
over PCI-E between the Aspeed SOC (acting as a BMC) and a host processor.
Changes since v10:
- Fix devicetree binding documentation
- Add patches to
On Tue, May 05, 2020 at 08:31:39AM -0700, Jaegeuk Kim wrote:
> We had to grab the inode before retrieving i_ino.
>
> Signed-off-by: Jaegeuk Kim
> ---
> fs/f2fs/file.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c
> index
Document the bindings for the Aspeed AST25XX and AST26XX XDMA engine.
Signed-off-by: Eddie James
Reviewed-by: Andrew Jeffery
---
.../devicetree/bindings/soc/aspeed/xdma.yaml | 103 +
MAINTAINERS| 6 ++
2 files changed, 109
Correct the pcie-device property, and add the Aspeed SCU interrupt
controller include.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
This commits adds a miscdevice to provide a user interface to the XDMA
engine. The interface provides the write operation to start DMA
operations. The DMA parameters are passed as the data to the write call.
The actual data to transfer is NOT passed through write. Note that both
directions of DMA
The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI
DMA operations between the SOC (acting as a BMC) and a host processor
in a server.
This commit adds a driver to control the XDMA engine and adds functions
to initialize the hardware and memory and start DMA operations.
Add the PCI-E root complex reset, correct the pcie-device property, and
add the Aspeed SCU interrupt controller include.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-g6.dtsi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
Add a reserved memory node for the VGA memory. Add the XDMA engine node,
enable it, and point it's memory region to the VGA memory.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git
Add a reserved memory node for the VGA memory. Add the XDMA engine node,
enable it, and point it's memory region to the VGA memory.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git
On Tue, May 05, 2020 at 08:03:17AM -0700, Shakeel Butt wrote:
> On Tue, May 5, 2020 at 12:13 AM Michal Hocko wrote:
> > So instead of potentially removing a useful information can we focus on
> > the remote charging side of the problem and deal with it in a sensible
> > way? That would make
> From: Pavel Machek
> Sent: Tuesday, May 5, 2020 5:10 AM
> To: Greg Kroah-Hartman
> Cc: linux-kernel@vger.kernel.org; sta...@vger.kernel.org; Dexuan Cui
> ; Rafael J. Wysocki
> Subject: Re: [PATCH 4.19 11/37] PM: hibernate: Freeze kernel threads in
> software_resume()
>
> Hi!
>
> > commit
Hello!
On Tue, 5 May 2020 at 11:37, Arnaldo Carvalho de Melo
wrote:
>
> Em Mon, May 04, 2020 at 02:07:56PM -0500, Daniel Díaz escreveu:
> > Hello!
> >
> > On Fri, 24 Apr 2020 at 09:10, Andreas Gerstmayr
> > wrote:
> > >
> > > On 24.04.20 15:07, Arnaldo Carvalho de Melo wrote:
> > > > Em Thu,
On 05/05/2020 17:44, Randy Dunlap wrote:
> On 5/5/20 8:31 AM, Mickaël Salaün wrote:
>> diff --git a/security/Kconfig b/security/Kconfig
>> index cd3cc7da3a55..d8fac9240d14 100644
>> --- a/security/Kconfig
>> +++ b/security/Kconfig
>> @@ -230,6 +230,32 @@ config STATIC_USERMODEHELPER_PATH
>>
On Tue, May 5, 2020 at 2:18 AM Emanuele Giuseppe Esposito
wrote:
>
>
>
> On 5/4/20 11:37 PM, David Rientjes wrote:
> > Since this is becoming a generic API (good!!), maybe we can discuss
> > possible ways to optimize gathering of stats in mass?
>
> Sure, the idea of a binary format was considered
On Tue, May 5, 2020 at 3:13 AM Christoph Hellwig wrote:
>
> this series gets rid of playing with the address limit in the exec and
> coredump code. Most of this was fairly trivial, the biggest changes are
> those to the spufs coredump code.
Ack, nice, and looks good.
The only part I dislike is
On Tue, May 05, 2020 at 05:52:28PM +0200, Wolfram Sang wrote:
> Hi,
>
> > I don't expect this to be used for much more than a simple write to PMIC
> > to kill the power. So this patch is tailor made for exactly this purpose.
>
> Frankly, I don't like it much. The atomic callbacks are supposed to
Hi Andreas,
On Tue, May 5, 2020 at 6:04 PM Andreas Färber wrote:
> Am 05.05.20 um 17:07 schrieb Geert Uytterhoeven:
> > Support for Actions Semi SoCs depends on ARCH_MULTI_V7, and thus on
> > ARCH_MULTIPLATFORM.
> > As the latter selects COMMON_CLK, there is no need for ARCH_ACTIONS to
> >
On Tue, May 05, 2020 at 08:35:45AM -0700, Shakeel Butt wrote:
> On Tue, May 5, 2020 at 8:27 AM Johannes Weiner wrote:
> >
> > On Mon, May 04, 2020 at 12:23:51PM -0700, Shakeel Butt wrote:
> > > On Mon, May 4, 2020 at 9:06 AM Michal Hocko wrote:
> > > > I really hate to repeat myself but this is
On 2020-05-02 15:49, Lukas Wunner wrote:
On Thu, Mar 26, 2020 at 12:14:19AM +0100, Heiko Stuebner wrote:
Some 8250 ports have a TEMT interrupt but it's not a part of the 8250
standard, instead only available on some implementations.
The current em485 implementation does not work on ports
Em Mon, May 04, 2020 at 02:07:56PM -0500, Daniel Díaz escreveu:
> Hello!
>
> On Fri, 24 Apr 2020 at 09:10, Andreas Gerstmayr wrote:
> >
> > On 24.04.20 15:07, Arnaldo Carvalho de Melo wrote:
> > > Em Thu, Apr 23, 2020 at 04:28:46PM -0500, Daniel Díaz escreveu:
> > >> On Wed, 22 Apr 2020 at
On 5/5/20 9:31 AM, Eric Dumazet wrote:
>
>
> On 5/5/20 9:25 AM, Eric Dumazet wrote:
>>
>>
>> On 5/5/20 9:13 AM, SeongJae Park wrote:
>>> On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet wrote:
>>>
On Tue, May 5, 2020 at 8:47 AM SeongJae Park wrote:
>
> On Tue, 5 May 2020 08:20:50
Hi Rajendra,
On Sun, May 03, 2020 at 05:34:29PM +0530, Rajendra Nayak wrote:
> QSPI needs to vote on a performance state of a power domain depending on
> the clock rate. Add support for it by specifying the perf state/clock rate
> as an OPP table in device tree.
>
> Signed-off-by: Rajendra Nayak
> On May 5, 2020, at 9:25 AM, Dimitri Sivanich wrote:
>
> Yes, we do see a need to clean up old code where it exists, but we would like
> to assume this responsibility ourselves in order to ensure functional
> continuity
> with externally available open-sourced modules that our customers
On 05.05.20 18:12, Boris Ostrovsky wrote:
On 5/5/20 12:02 PM, Jürgen Groß wrote:
On 05.05.20 17:01, Arnd Bergmann wrote:
On Tue, May 5, 2020 at 4:34 PM Jürgen Groß wrote:
On 05.05.20 16:15, Arnd Bergmann wrote:
The __xenbus_map_ring() function has two large arrays, 'map' and
'unmap' on its
$ git log --oneline include/uapi/linux/pci_regs.h
202853595e53 PCI: pciehp: Disable in-band presence detect when possible
ed22aaaede44 PCI: dwc: intel: PCIe RC controller driver
bbdb2f5ecdf1 PCI: Add #defines for Enter Compliance, Transmit Margin
c9c13ba428ef PCI: Add PCI_STD_NUM_BARS
The K3 INTA driver, which is source TX/RX IRQs for CPSW NUSS, defines IRQs
triggering type as EDGE by default, but triggering type for CPSW NUSS TX/RX
IRQs has to be LEVEL as the EDGE triggering type may cause unnecessary IRQs
triggering and NAPI scheduling for empty queues. It was discovered with
On 5/5/20 9:25 AM, Eric Dumazet wrote:
>
>
> On 5/5/20 9:13 AM, SeongJae Park wrote:
>> On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet wrote:
>>
>>> On Tue, May 5, 2020 at 8:47 AM SeongJae Park wrote:
On Tue, 5 May 2020 08:20:50 -0700 Eric Dumazet
wrote:
>
>
czw., 30 kwi 2020 o 02:10 Kent Gibson napisał(a):
>
> Add display of the bias flags.
>
> Signed-off-by: Kent Gibson
> ---
> tools/gpio/lsgpio.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/tools/gpio/lsgpio.c b/tools/gpio/lsgpio.c
> index e1430f504c13..8a71ad36f83b
On Tue, May 05, 2020 at 09:00:44AM -0700, Eric Dumazet wrote:
> > Not exactly the 10,000,000, as it is only the possible highest number, but I
> > was able to observe clear exponential increase of the number of the objects
> > using slabtop. Before the start of the problematic workload, the
Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
loaded explicitly. Earlier versions didn't need that as they where using
an EEPROM for that purpose. This series takes care of setting up the
relevant infrastructure and run the firmware loading routine at the
right moment.
When needed, RPi4's co-processor (called VideoCore) has to be instructed
to load VL805's firmware (the chip providing xHCI support). VideCore's
firmware expects the board's PCIe bus to be already configured in order
for it to load the xHCI chip firmware. So we have to make sure this
happens in
On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
may either be loaded directly from an EEPROM or, if not present, by the
SoC's VideCore (the SoC's co-processor). Introduce the function that
informs VideCore that VL805 may need its firmware loaded.
Signed-off-by: Nicolas
śr., 29 kwi 2020 o 15:56 Takashi Iwai napisał(a):
>
> The commit 7ecced0934e5 ("gpio: exar: add a check for the return value
> of ida_simple_get fails") added a goto jump to the common error
> handler for ida_simple_get() error, but this is wrong in two ways:
> it doesn't set the proper return
On 5/5/20 9:13 AM, SeongJae Park wrote:
> On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet wrote:
>
>> On Tue, May 5, 2020 at 8:47 AM SeongJae Park wrote:
>>>
>>> On Tue, 5 May 2020 08:20:50 -0700 Eric Dumazet
>>> wrote:
>>>
On 5/5/20 8:07 AM, SeongJae Park wrote:
> On
sob., 2 maj 2020 o 19:22 Petteri Jokinen napisał(a):
>
> Add GPIO support for Fintek F81865 chip.
>
> Datasheet: http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
>
> Signed-off-by: Petteri Jokinen
Patch applied, thanks!
Bart
On Tue, May 05, 2020 at 11:54:05AM -0400, Tejun Heo wrote:
> Hello, Bruce.
>
> On Mon, May 04, 2020 at 10:15:14PM -0400, J. Bruce Fields wrote:
> > We're currently using it to pass the struct svc_rqst that a new nfsd
> > thread needs. But once the new thread has gotten that, I guess it could
> >
On Tue, May 05, 2020 at 04:04:21PM +0100, Sudeep Holla wrote:
> On Tue, May 05, 2020 at 04:08:08PM +0200, Arnd Bergmann wrote:
> > When CONFIG_ARM_PSCI_FW is disabled but CONFIG_HAVE_ARM_SMCCC is enabled,
> > arm-scmi runs into a link failure:
> >
> > arm-linux-gnueabi-ld:
It's possible to have build configuration which will force PTP_1588_CLOCK=m
and so TI_K3_AM65_CPTS=m while still have TI_K3_AM65_CPSW_NUSS=y. This will
cause build failures:
aarch64-linux-gnu-ld: ../drivers/net/ethernet/ti/am65-cpsw-nuss.o: in function
`am65_cpsw_init_cpts':
On Tue, May 05, 2020 at 04:04:21PM +0100, Sudeep Holla wrote:
> Hi Arnd,
>
> On Tue, May 05, 2020 at 04:08:08PM +0200, Arnd Bergmann wrote:
> > When CONFIG_ARM_PSCI_FW is disabled but CONFIG_HAVE_ARM_SMCCC is enabled,
> > arm-scmi runs into a link failure:
> >
> > arm-linux-gnueabi-ld:
On Mon, May 04, 2020 at 10:29:05AM +0100, Sudeep Holla wrote:
> diff --git a/drivers/firmware/psci/soc_id.c b/drivers/firmware/psci/soc_id.c
> new file mode 100644
> index ..b45f2d78e12e
> --- /dev/null
> +++ b/drivers/firmware/psci/soc_id.c
> @@ -0,0 +1,165 @@
> +//
On 5/5/20 9:43 AM, shuah wrote:
On 5/5/20 9:36 AM, Takashi Iwai wrote:
On Tue, 05 May 2020 17:30:07 +0200,
shuah wrote:
On 5/5/20 9:25 AM, shuah wrote:
On 5/4/20 11:57 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 5.6.11 release.
There are 73 patches in
wt., 5 maj 2020 o 10:45 Mian Yousaf Kaukab napisał(a):
>
> Export MODULE_DEVICE_TABLE since the driver can be built as a module.
>
> Signed-off-by: Mian Yousaf Kaukab
> ---
> drivers/gpio/gpio-tegra186.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpio/gpio-tegra186.c
Em Tue, May 05, 2020 at 08:52:18AM -0600, Mathieu Poirier escreveu:
> On Tue, 5 May 2020 at 07:37, Leo Yan wrote:
> >
> > The variable 'traceid_list' is defined in the header file cs-etm.h,
> > if multiple C files include cs-etm.h the compiler might complaint for
> > multiple definition of
On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
loaded directly from an EEPROM or, if not present, by the SoC's
VideoCore. Inform VideoCore that VL805 was just reset.
Also, as this creates a dependency between USB_PCI and VideoCore's
firmware interface, and since USB_PCI
On Tue, 5 May 2020 09:00:44 -0700 Eric Dumazet wrote:
> On Tue, May 5, 2020 at 8:47 AM SeongJae Park wrote:
> >
> > On Tue, 5 May 2020 08:20:50 -0700 Eric Dumazet
> > wrote:
> >
> > >
> > >
> > > On 5/5/20 8:07 AM, SeongJae Park wrote:
> > > > On Tue, 5 May 2020 07:53:39 -0700 Eric Dumazet
Em Tue, May 05, 2020 at 04:25:21PM +0200, Jiri Olsa escreveu:
> On Fri, May 01, 2020 at 03:13:14PM -0700, Ian Rogers wrote:
>
> SNIP
>
> > diff --git a/tools/lib/symbol/kallsyms.c b/tools/lib/symbol/kallsyms.c
> > index 1a7a9f877095..e335ac2b9e19 100644
> > --- a/tools/lib/symbol/kallsyms.c
> >
xHCI's PCI fixup, run at the end of pcie-brcmstb's probe, depends on
RPi4's VideoCore firmware interface to be up and running. It's possible
for both initializations to race, so make sure it's available prior to
starting.
Signed-off-by: Nicolas Saenz Julienne
Reviewed-by: Florian Fainelli
---
The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip
that implements xHCI. After a PCI reset, VL805's firmware may either be
loaded directly from an EEPROM or, if not present, by the SoC's
co-processor, VideoCore. RPi4's VideoCore OS contains both the non public
firmware load
The property is needed in order to trigger VL805's firmware load. Note
that gap between the property introduced and the previous one is due to
the properties not being defined.
Signed-off-by: Nicolas Saenz Julienne
Reviewed-by: Florian Fainelli
---
include/soc/bcm2835/raspberrypi-firmware.h |
On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
loaded directly from an EEPROM or, if not present, by the SoC's
co-processor, VideoCore. This series adds support for the later.
Note that there are a set of constraints we have to consider:
- We need to make sure the
On Mon, 4 May 2020 18:05:18 +0100, Daniel Thompson wrote:
> flush_icache_range() contains a bodge to avoid issuing IPIs when the kgdb
> trap handler is running because issuing IPIs is unsafe (and not needed)
> in this execution context. However the current test, based on
> kgdb_connected is
On 5/5/20 12:02 PM, Jürgen Groß wrote:
> On 05.05.20 17:01, Arnd Bergmann wrote:
>> On Tue, May 5, 2020 at 4:34 PM Jürgen Groß wrote:
>>> On 05.05.20 16:15, Arnd Bergmann wrote:
The __xenbus_map_ring() function has two large arrays, 'map' and
'unmap' on its stack. When clang decides
I think this is causing this bug (seen on 5.6.8):
# ipcs -q
-- Message Queues
keymsqid owner perms used-bytes messages
# ipcmk -Q
Message queue id: 0
# ipcs -q
-- Message Queues
keymsqid owner perms used-bytes
On Mon, Apr 27, 2020 at 03:49:30PM +0300, amirmi...@gmail.com wrote:
> From: Amir Mizinski
>
> Added a YAML schema to support tpm tis i2c related dt-bindings for the I2c
> PTP based physical layer.
>
> This patch adds the documentation for corresponding device tree bindings of
> I2C based
On Tue, May 05, 2020 at 05:43:04PM +0200, Vincent Guittot wrote:
> On Tue, 5 May 2020 at 17:16, Peng Liu wrote:
> >
> > On Tue, May 05, 2020 at 04:27:11PM +0200, Vincent Guittot wrote:
> > > Le mardi 05 mai 2020 à 21:40:56 (+0800), Peng Liu a écrit :
> > > > On Mon, May 04, 2020 at 05:17:11PM
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