Commit-ID: 955d1427a91b18f53e082bd7c19c40ce13b0a0f4
Gitweb: http://git.kernel.org/tip/955d1427a91b18f53e082bd7c19c40ce13b0a0f4
Author: Aravind Gopalakrishnan
AuthorDate: Fri, 8 Jul 2016 11:09:38 +0200
Committer: Ingo Molnar
CommitDate: Fri, 8 Jul 2016 11:29:25 +0200
x86/mce/AMD
Commit-ID: 6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419
Gitweb: http://git.kernel.org/tip/6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419
Author: Aravind Gopalakrishnan
AuthorDate: Sat, 30 Apr 2016 14:33:52 +0200
Committer: Ingo Molnar
CommitDate: Tue, 3 May 2016 08:24:15 +0200
x86/mce: Grade
Commit-ID: bb91f8c0176b072aeb6b84cfd7e04084025121e0
Gitweb: http://git.kernel.org/tip/bb91f8c0176b072aeb6b84cfd7e04084025121e0
Author: Aravind Gopalakrishnan
AuthorDate: Sat, 30 Apr 2016 14:33:53 +0200
Committer: Ingo Molnar
CommitDate: Tue, 3 May 2016 08:24:16 +0200
x86/mce: Carve
Commit-ID: 10001d91aa0efc793952051f9070a569cc388ebc
Gitweb: http://git.kernel.org/tip/10001d91aa0efc793952051f9070a569cc388ebc
Author: Aravind Gopalakrishnan
AuthorDate: Sat, 30 Apr 2016 14:33:51 +0200
Committer: Ingo Molnar
CommitDate: Tue, 3 May 2016 08:24:15 +0200
x86/mce: Log MCEs
Commit-ID: ea2ca36b658cfc6081ee454e97593c81f646806e
Gitweb: http://git.kernel.org/tip/ea2ca36b658cfc6081ee454e97593c81f646806e
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:21 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:15 +0100
x86/mce/AMD
Commit-ID: 8dd1e17a55b0bb1206c71c7a4344c5e3037cdf65
Gitweb: http://git.kernel.org/tip/8dd1e17a55b0bb1206c71c7a4344c5e3037cdf65
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:19 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:14 +0100
x86/mce/AMD: Fix
Commit-ID: 2cd3b5f9033f0b051842a279dac5a54271cbd3c8
Gitweb: http://git.kernel.org/tip/2cd3b5f9033f0b051842a279dac5a54271cbd3c8
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:20 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:15 +0100
x86/mce: Clarify
Commit-ID: be0aec23bf4624fd55650629fe8df20483487049
Gitweb: http://git.kernel.org/tip/be0aec23bf4624fd55650629fe8df20483487049
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:18 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:14 +0100
x86/mce/AMD, EDAC
Commit-ID: adc53f2e0ae2fcff10a4b981df14729ffb1482fc
Gitweb: http://git.kernel.org/tip/adc53f2e0ae2fcff10a4b981df14729ffb1482fc
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:17 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:14 +0100
x86/mce: Move
On 3/3/16 12:45 PM, Borislav Petkov wrote:
Applied, minor stuff corrected and pushed out to
http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras
so that the 0day bot can chew on them a little.
Thanks!
-Aravind.
Since this is contained to only MCE code, move
the MSR definiton there instead of adding to msr-index
Per discussion here:
http://marc.info/?l=linux-kernel&m=145633699026474&w=2
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4
arch/x86/include
In an attempt to aid in understanding of what the threshold_block
structure holds, provide comments to describe the members here.
Also, trim comments around threshold_restart_bank()
and update copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch
existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 90
2 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 59 +++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 30
nal change is introduced
Aravind Gopalakrishnan (5):
x86/mce: Move MCx_CONFIG MSR definition
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD: Add comments for easier
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0681d0a..b016219 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7
On 3/2/2016 10:38 AM, Borislav Petkov wrote:
But you can take the three here, merge them again into a single patch
and do the changes ontot.
I made them into three to show you more easily what should be changed.
Ok, I'll just spin a V3 of the entire patchset with all your suggested
changes
On 3/2/2016 10:21 AM, Borislav Petkov wrote:
On Wed, Mar 02, 2016 at 09:52:23AM -0600, Aravind Gopalakrishnan wrote:
So, I think we should continue this approach and have something like this-
static const char * const amd_core_mcablock_names[] = {
[SMCA_LS] = "load_
file,
while at it and do some minor stylistic changes.
Signed-off-by: Borislav Petkov
Looks good. Thanks.
Reviewed-by: Aravind Gopalakrishnan
-
default:
printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
-
On 3/2/2016 4:50 AM, Borislav Petkov wrote:
Ok, applied with a bunch of changes ontop.
Thanks!
The second patch is relying on the assumption that a
hwid of 0 is invalid. Is that so?
Yes, HWID of 0 is invalid.
Thanks,
-Aravind.
On 3/2/2016 4:53 AM, Borislav Petkov wrote:
Merge all IP blocks into a single enum. This allows for easier block
name use later. Drop superfluous "_BLOCK" from the enum names.
Signed-off-by: Borislav Petkov
Cc: Aravind Gopalakrishnan
enum amd_ip_types {
- SMCA_F17H_CORE
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 69f8bda..3b45e36 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 53 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 11
existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 90
2 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b
In an attempt to aid in understand of what threshold_block
structure holds, assing comments to describe the members here.
Also, trimming comments around threshold_restart_bank()
and updating copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86
code
Aravind Gopalakrishnan (5):
x86/mce: Move MCx_CONFIG MSR definition
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD: Add comments for easier understanding
arch
Since this is contained to only MCE code, move
the MSR definiton there instead of adding to msr-index
Per discussion here:
http://marc.info/?l=linux-kernel&m=145633699026474&w=2
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4
arch/x86/include
On 2/26/2016 11:44 AM, Borislav Petkov wrote:
threshold_restart_bank() reprograms the MISC MSR after sanity-checking
the fields supplied for that MSR. store_threshold_limit() sets the error
count, store_interrupt_enable() enables/disables the interrupt and both
call threshold_restart_bank() to d
On 2/23/2016 6:35 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:11PM -0600, Aravind Gopalakrishnan wrote:
/*
+ * Set the error_count and interrupt_enable sysfs attributes here.
+ * This function gets called during the init phase and when someone
+ * makes changes to either of
On 2/24/2016 5:37 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 05:02:40PM -0600, Aravind Gopalakrishnan wrote:
On 2/23/16 6:11 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:10PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
-#define MCI_STATUS_DEFERRED
On 2/24/2016 5:33 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 04:56:38PM -0600, Aravind Gopalakrishnan wrote:
I think MSR_AMD64_SMCA_MC0_MISC0 would be required in mce.c as well.
So might be better to retain it here.
Actually, I'm thinking, these all are - even if used in multiple
On 2/24/2016 5:28 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 04:50:37PM -0600, Aravind Gopalakrishnan wrote:
Sorry about that. Looks like this pair is not defined in spelling.txt. So,
might be worth adding there as well?
Oh geez, we have a spelling.txt! I think we can declare the
On 2/23/16 6:37 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:08PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
#define MCI_STATUS_POISON (1ULL<<43) /* access po
On 2/23/16 6:11 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:10PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
-#define MCI_STATUS_DEFERRED(1ULL<<44) /* declare an uncorrected error */
+#define MCI_STATUS_DEFERRED(1ULL<<44) /* declare a de
On 2/23/16 6:39 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:09PM -0600, Aravind Gopalakrishnan wrote:
/* 'SMCA': AMD64 Scalable MCA */
+#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
#define MSR_AMD64_SMC
On 2/16/2016 3:45 PM, Aravind Gopalakrishnan wrote:
In upcoming processors, the BLKPTR field is no longer used
to indicate the MSR number of the additional register.
Insted, it simply indicates the prescence of additional MSRs.
Fixing the logic here to gather MSR address from
existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/msr-index.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 94 +---
2 files changed, 69 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h
In an attempt to help folks not very familiar with the code to
understand what the code is doing, adding a bit of helper
comments around some more important functions in the driver
to describe them.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 50 ++
arch/x86/include/asm/msr-index.h | 2 +
arch
functionality
Tested the patches for regressions on Fam15h, Fam10h systems
and found none.
Aravind Gopalakrishnan (4):
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2ec67ac..476da8b 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7
Commit-ID: e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Gitweb: http://git.kernel.org/tip/e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:53 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:59 +0100
x86/mce/AMD: Set
Commit-ID: f57a1f3c14b9182f1fea667f5a38a1094699db7c
Gitweb: http://git.kernel.org/tip/f57a1f3c14b9182f1fea667f5a38a1094699db7c
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:51 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD: Fix
Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2
Gitweb: http://git.kernel.org/tip/60f116fca162d9488f783f5014779463243ab7a2
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:50 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD
Commit-ID: 284b965c146f482b4a411133f62288d52b7e3a72
Gitweb: http://git.kernel.org/tip/284b965c146f482b4a411133f62288d52b7e3a72
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:49 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:56 +0100
x86/mce/AMD: Do
Commit-ID: bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Gitweb: http://git.kernel.org/tip/bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:48 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:55 +0100
x86/mce: Fix
On 1/21/2016 6:32 AM, Borislav Petkov wrote:
On Wed, Jan 20, 2016 at 12:54:51PM +0300, Dan Carpenter wrote:
+ u64 dct_sel_base_off= (u64)(pvt->dct_sel_hi & 0xFC00) << 16;
@Aravind: do you have a box with
setpci -s 18.2 0x114.l
bits [31:16] not 0?
Nope. I don't see it set
Commit-ID: 3849e91f571dcb48cf2c8143480c59137d44d6bc
Gitweb: http://git.kernel.org/tip/3849e91f571dcb48cf2c8143480c59137d44d6bc
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer: Thomas Gleixner
CommitDate: Sat, 7 Nov 2015 10:37:51 +0100
x86/AMD: Fix
Commit-ID: e5e84a26ef2909964d964224b805236293fb4c63
Gitweb: http://git.kernel.org/tip/e5e84a26ef2909964d964224b805236293fb4c63
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 4 Nov 2015 12:52:06 +0100
x86/AMD: Fix
-off-by: Aravind Gopalakrishnan
---
Changes in V2:
- Move LLC calculation logic to amd_detect_cmp() and change patch
header as a result. (This in turn fixes the issue found by
kbuild bot on the V1 patch)
arch/x86/kernel/cpu/amd.c | 13 +
1 file changed, 13 insertions(+)
diff
On 11/3/2015 1:52 PM, Borislav Petkov wrote:
On Tue, Nov 03, 2015 at 01:41:53PM -0600, Aravind Gopalakrishnan wrote:
cpu_llc_id references should be wrapped under #ifdef CONFIG_SMP.
Did that and kernel build worked with the attached config.
Will send a V2 with the fix.
Why aren't you
On 11/3/2015 1:27 PM, kbuild test robot wrote:
Hi Aravind,
[auto build test ERROR on bp/for-next]
[also ERROR on: v4.3 next-20151103]
url:
https://github.com/0day-ci/linux/commits/Aravind-Gopalakrishnan/x86-intel_cacheinfo-Fix-LLC-topology-for-AMD-Fam17h-systems/20151104-031725
base
-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index e38d338..897a483 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b
Commit-ID: c7f54d21fb02e90042e6233b46716dcb244e70e6
Gitweb: http://git.kernel.org/tip/c7f54d21fb02e90042e6233b46716dcb244e70e6
Author: Aravind Gopalakrishnan
AuthorDate: Fri, 30 Oct 2015 13:11:37 +0100
Committer: Ingo Molnar
CommitDate: Sun, 1 Nov 2015 11:26:13 +0100
x86/mce: Add a
SMCA is enabled before
enabling the new features.
Adding code to detect if it SMCA is enabled in this patch
and store that info in mce_vendor_flags structure.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 13 -
arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
2
From: Wan Zongshun
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Add the bit here to allow /proc/cpuinfo to list the feature
Signed-off-by: Wan Zongshun
[Wrap code in patch form, fix comments]
Signed-off-by: Aravind Gopalakri
/marc.info/?l=linux-kernel&m=144592319708523&w=2
after which it worked fine.
Aravind Gopalakrishnan (1):
x86/mcheck: Add Scalable MCA cpuid bit
Wan Zongshun (1):
x86/cpufeature: Add CLZERO feature
arch/x86/include/asm/cpufeature.h | 5 -
arch/x86/include/asm
On 10/26/2015 8:09 PM, Borislav Petkov wrote:
you called it "AMD
extended features 2" - then those should really go into into the
x86_capability array, i.e., like you've done it in your initial version.
So please fix the SOB chain of your initial patch and send that one out.
Forgot to ask ea
On 10/26/2015 8:09 PM, Borislav Petkov wrote:
On Mon, Oct 26, 2015 at 05:50:47PM -0500, Aravind Gopalakrishnan wrote:
How do you prefer a V2 for this to be sent though-
Shall I wait until your fixes are in tip.git and resend?
Or send a V2 on top of current tip.git?
Actually, I just showed it
On 10/26/2015 3:22 PM, Borislav Petkov wrote:
On Mon, Oct 26, 2015 at 10:12:59AM -0500, Aravind Gopalakrishnan wrote:
For large part yes, wrapped code in patch form with commit message etc.
And modified comment a little bit.
Does that still require his address in "From"?
Yes,
(removing peter.p.waskiewicz...@intel.com as email bounced)
On 10/25/2015 5:37 AM, Borislav Petkov wrote:
On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote:
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Ad
On 10/25/2015 5:37 AM, Borislav Petkov wrote:
On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote:
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Add the bit here to allow /proc/cpuinfo to list the feature
Signe
SMCA is enabled before
enabling the new features.
Adding code to detect if it SMCA is enabled in this patch
and store that info in mce_vendor_flags structure.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 13 -
arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
2
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Add the bit here to allow /proc/cpuinfo to list the feature
Signed-off-by: Wan Zongshun
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/cpufeature.h | 5 -
arc
Patch1: Add Scalable MCA feature identification
Patch2: Add CLZERO feature
Aravind Gopalakrishnan (2):
x86/mcheck: Add Scalable MCA cpuid bit
x86/cpufeature: Add CLZERO feature
arch/x86/include/asm/cpufeature.h | 5 -
arch/x86/include/asm/mce.h| 13 -
arch/x86
Commit-ID: 1a6775c1a2c2ed863699403cda517916c22aeb72
Gitweb: http://git.kernel.org/tip/1a6775c1a2c2ed863699403cda517916c22aeb72
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 19 Oct 2015 11:17:42 +0200
Committer: Ingo Molnar
CommitDate: Wed, 21 Oct 2015 11:10:55 +0200
x86/amd_nb, EDAC
On 10/14/2015 8:51 AM, Borislav Petkov wrote:
This is in preparation for future changes anyway so the name had to
be not so generic and hint at the PCI dev argument. I'll change it to
amd_pci_dev_to_node_id() when applying.
Thanks Boris.
-Aravind.
--
To unsubscribe from this list: send th
ional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/amd_nb.h | 2 +-
drivers/edac/amd64_edac.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 1a5da2e..319843d 100644
Commit-ID: 85c9306d44f757d2fb3b0e3e399080a025315c7f
Gitweb: http://git.kernel.org/tip/85c9306d44f757d2fb3b0e3e399080a025315c7f
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 12 Oct 2015 11:22:38 +0200
Committer: Ingo Molnar
CommitDate: Mon, 12 Oct 2015 16:15:47 +0200
x86/ras
Commit-ID: a1300e50529795cd605da6a015d4944a18921db0
Gitweb: http://git.kernel.org/tip/a1300e50529795cd605da6a015d4944a18921db0
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 12 Oct 2015 11:22:39 +0200
Committer: Ingo Molnar
CommitDate: Mon, 12 Oct 2015 16:15:47 +0200
x86/ras
Commit-ID: fa20a2ed6fff717839ec03b6574ea0affcb58841
Gitweb: http://git.kernel.org/tip/fa20a2ed6fff717839ec03b6574ea0affcb58841
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 12 Oct 2015 11:22:40 +0200
Committer: Ingo Molnar
CommitDate: Mon, 12 Oct 2015 16:15:48 +0200
x86/ras
On 9/29/2015 6:45 AM, Borislav Petkov wrote:
@@ -216,12 +223,17 @@ static int set_scrub_rate(struct mem_ctl_info *mci, u32
bw)
if (pvt->fam == 0xf)
min_scrubrate = 0x0;
+ else if (pvt->fam == 0x15 && pvt->model == 0x60)
+ min_scrubrate = 0x6;
/* E
This section used to be in amd64_edac.h. Moving it here as it
seems to be a more natural place to put all documentation related info
Added links to the BKDGs while at it.
Signed-off-by: Aravind Gopalakrishnan
---
Documentation/edac.txt | 46 ++
1
nd write appropriate
scrub rate register there instead of re-factoring code.
- Removed code to set dct in get_scrub_rate() as it was unnecessary
- Removed changelogs from amd64_edac.h and add back any info about
reference documents to Documentation/edac.txt
Aravind Gopalakrishnan (3)
Git provides us all the changelogs anyway. So trimming
the comments section here.
Updated the copyrights info while at it.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/amd64_edac.h | 56 +--
1 file changed, 1 insertion(+), 55 deletions
get_scrub_rate() functions so that
they are aware of these changes.
Tested on F15hM60h, Fam15h Models 00h-0fh and Fam10h systems and
it works fine.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/amd64_edac.c | 23 +++
drivers/edac/amd64_edac.h | 2 ++
2 files changed, 21
nything to the file. Therefore, modifying the
behavior in this patch to return EINVAL on bad input strings
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/ras/mce_amd_inj.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/x86/ras/mce_amd_inj.c b/arch/x86/ras/
. Otherwise, triggering #MC or APIC interrupts on a core which is
not the NBC would not have any effect on the system, i.e we would not
see any relevant output on kernel logs for the error we just injected.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/ras/mce_amd_inj.c | 56
ection for Deferred/Threshold
error interrupts too.
Aravind Gopalakrishnan (3):
RAS, mce_amd_inj: Return early on invalid input
RAS, mce_amd_inj: Add capability to trigger apic interrupts
RAS, mce_amd_inj: Inject errors on NBC for bank 4 errors
arch/x86/ras/mce_amd_inj.c | 109
With this extension to the flags attribute, deferred error interrupts
and threshold interrupts can be triggered to test the apic interrupt
handler functionality for these type of errors
Update README section about the same too.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/ras
On 9/24/2015 11:33 AM, Borislav Petkov wrote:
And that's ugly - I much prefer having input arguments being input only
and return values being return values only. If it can be helped, that
is. And in this case, it is not necessary.
Okay, I'll fix this in the next version and do a family check
On 9/24/2015 4:18 AM, Borislav Petkov wrote:
On Wed, Sep 16, 2015 at 03:53:30PM -0500, Aravind Gopalakrishnan wrote:
-static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
+static u32 find_scrub_rate(u32 new_bw, u32 min_rate, u32 *scrub_bw)
{
u32 scrubval
On 9/17/15 10:24 AM, Borislav Petkov wrote:
On Thu, Sep 17, 2015 at 09:35:25AM -0500, Aravind Gopalakrishnan wrote:
Shall I send a V2 of this patch to update copyrights and remove the
changelogs alone?
(I can meld it with patch 2/3 too if you prefer..)
Let me take a look at the rest first. Am
On 9/17/15 2:43 AM, Borislav Petkov wrote:
On Wed, Sep 16, 2015 at 03:53:31PM -0500, Aravind Gopalakrishnan wrote:
*Changes/Fixes by Borislav Petkov :
*- misc fixes and code cleanups
*
+ * Changes by Aravind Gopalakrishnan
+ * - Add support for
We already have edac_mem_types[] that enumerates the different
kinds of memory. So, use that and remove the redundant
memory_type[] array here.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/ghes_edac.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff
Extending the comments section to include the BKDG references
for newer processors which this EDAC driver supports.
Updated the copyrights info and fixed a trivial typo while at it.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/amd64_edac.h | 30 --
1 file
documentation info
No functional change here.
Aravind Gopalakrishnan (3):
EDAC, ghes_edac: Remove redundant memory_type array
EDAC, amd64_edac: Extend scrub rate programmability feature for
F15hM60h
EDAC, amd64_edac: Update copyright and documentation info
drivers/edac/amd64_edac.c
get_scrub_rate() functions so that
they are aware of these changes.
Fixing couple of indentation issues since I am touching the file.
Tested on F15hM60h, Fam15h Models 00h-0fh and Fam10h systems and
it works fine.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/amd64_edac.c | 53
Commit-ID: e237882b8f83dd1a0eece1608bcb689d4f4b221b
Gitweb: http://git.kernel.org/tip/e237882b8f83dd1a0eece1608bcb689d4f4b221b
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 10 Aug 2015 20:20:48 -0500
Committer: Ingo Molnar
CommitDate: Wed, 12 Aug 2015 12:06:08 +0200
sched/numa: Fix
rnel&m=141353106106771&w=2
Fixing the issue here.
Signed-off-by: Aravind Gopalakrishnan
---
kernel/sched/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 67d..e51739e 100644
--- a/kernel/sched/c
ror as determined by the
'Deferred' bit.
Refer AMD Error Scope Hierarchy table in a newer BKDG
(example: 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features")
for clarification.
Therefore, fix the output to not disply 'CE'
Signed-off-by: Aravind Gopalakrishnan
-
Commit-ID: cc2749e4095cbbcb35518fb2db5e926b85c3f25f
Gitweb: http://git.kernel.org/tip/cc2749e4095cbbcb35518fb2db5e926b85c3f25f
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 15 Jun 2015 10:28:15 +0200
Committer: Ingo Molnar
CommitDate: Thu, 18 Jun 2015 11:16:06 +0200
x86/cpu/amd
On 6/10/2015 10:33 AM, Borislav Petkov wrote:
From: Borislav Petkov
When during injection we populate MCi_MISC by writing into misc, we need
to set the MiscV bit in the corresponding MCi_STATUS register which
denotes that there's valid info in the MCi_MISC register.
Signed-off-by: Borislav Pet
not have any effect on the system.
(i.e), we would not see any relevant output on kernel logs for
the error we just injected.
Update copyrights info while at it.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 57 +-
1 file
Anvin"
Cc: Borislav Petkov
Cc: Jacob Shin
Cc: Dave Hansen
Cc: Andy Lutomirski
Cc: Paolo Bonzini
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/amd.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/
age.
- checkpatch with --strict threw couple of checks on Patch 3, fixed them
- Update copyright info in mce_amd_inj.c
Aravind Gopalakrishnan (3):
x86, amd: Store number of nodes in a static global variable
x86, amd: Provide accessor for number of nodes
edac, mce_amd_inj: Inject errors on
Cc: Andy Lutomirski
Cc: Paolo Bonzini
Cc: Denys Vlasenko
Cc: Hector Marco-Gisbert
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/amd.c| 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/i
Commit-ID: 5c0d728e1a8ccbaf68ec37181e466627ba0a6efc
Gitweb: http://git.kernel.org/tip/5c0d728e1a8ccbaf68ec37181e466627ba0a6efc
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 6 May 2015 06:58:57 -0500
Committer: Borislav Petkov
CommitDate: Thu, 7 May 2015 10:28:43 +0200
x86/irq
Commit-ID: afdf344e08fbec28ab2204a626fa1f260dcb68be
Gitweb: http://git.kernel.org/tip/afdf344e08fbec28ab2204a626fa1f260dcb68be
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 6 May 2015 06:58:53 -0500
Committer: Borislav Petkov
CommitDate: Wed, 6 May 2015 19:49:20 +0200
x86/mce/amd
Commit-ID: 7559e13fb4abe7880dfaf985d6a1630ca90a67ce
Gitweb: http://git.kernel.org/tip/7559e13fb4abe7880dfaf985d6a1630ca90a67ce
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 6 May 2015 06:58:55 -0500
Committer: Borislav Petkov
CommitDate: Wed, 6 May 2015 20:34:31 +0200
x86/mce: Add
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