The Stratix10 SoCFPGA uses the PL330 DMAC. This patch adds the PL330
DMAC to the Stratix10 device tree.
Signed-off-by: Graham Moore
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/altera
The PL330 DMA driver will not load on Arria10 without devicetree entries
for clocks and clock_names. This patch adds those entries. It also adds
the ninth interrupt, which is required for error detection.
Signed-off-by: Graham Moore
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 5 -
1 file
Add socfpga_arria10_socdk_nand.dts board file for supporting NAND
on Altera Arria10.
Signed-off-by: Graham Moore
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 44
2 files changed, 45 insertions(+)
create
Howdy folks,
Any comment on this patch? Is anyone else using Denali NAND rev 5.1
controller?
Thanks,
Graham
On 07/21/2015 09:39 AM, Graham Moore wrote:
Read Denali hardware revision number and use it to
calculate max_banks, The encoding of max_banks changed
in Denali revision 5.1.
Signed
On 07/28/2015 01:07 PM, Marek Vasut wrote:
On Tuesday, July 28, 2015 at 07:38:03 PM, Graham Moore wrote:
DTTO here.
Thanks a lot for working on the driver though -- would you like me to continue
reviewing or just take over please ?
Aha, I see your strategy :) You must *really* want to take
Signed-off-by: Graham Moore
---
V2: Add cdns prefix to driver-specific bindings.
V3: Use existing property "is-decoded-cs" instead of creating a duplicate,
"ext-decoder". Timing parameters are in nanoseconds, not master reference
clocks. Remove bus-num completely.
V4: Add
Signed-off-by: Graham Moore
---
V2: use NULL instead of modalias in spi_nor_scan call
V3: Use existing property is-decoded-cs instead of creating duplicate.
V4: Support Micron quad mode by snooping command stream for EVCR command
and subsequently configuring Cadence controller for quad mode.
V5
Hi Vikas,
On 07/24/2015 07:02 PM, vikasm wrote:
Hi Graham,
On 07/24/2015 10:17 AM, Graham Moore wrote:
Signed-off-by: Graham Moore
---
V2: use NULL instead of modalias in spi_nor_scan call
V3: Use existing property is-decoded-cs instead of creating duplicate.
V4: Support Micron quad mode by
Signed-off-by: Graham Moore
---
V2: use NULL instead of modalias in spi_nor_scan call
V3: Use existing property is-decoded-cs instead of creating duplicate.
V4: Support Micron quad mode by snooping command stream for EVCR command
and subsequently configuring Cadence controller for quad mode.
V5
On 07/24/2015 11:25 AM, Marek Vasut wrote:
On Friday, July 24, 2015 at 06:12:01 PM, Graham Moore wrote:
On 07/24/2015 07:45 AM, Marek Vasut wrote:
On Monday, March 23, 2015 at 02:36:21 PM, Graham Moore wrote:
Signed-off-by: Graham Moore
---
V2: Add cdns prefix to driver-specific bindings.
V3
Signed-off-by: Graham Moore
---
V2: Add cdns prefix to driver-specific bindings.
V3: Use existing property "is-decoded-cs" instead of creating a duplicate,
"ext-decoder". Timing parameters are in nanoseconds, not master reference
clocks. Remove bus-num completely.
---
...
On 07/24/2015 07:45 AM, Marek Vasut wrote:
On Monday, March 23, 2015 at 02:36:21 PM, Graham Moore wrote:
Signed-off-by: Graham Moore
---
V2: Add cdns prefix to driver-specific bindings.
V3: Use existing property "is-decoded-cs" instead of creating a duplicate,
"ext-decoder"
Read Denali hardware revision number and use it to
calculate max_banks, The encoding of max_banks changed
in Denali revision 5.1.
Signed-off-by: Graham Moore
---
drivers/mtd/nand/denali.c | 11 ++-
drivers/mtd/nand/denali.h |2 ++
2 files changed, 12 insertions(+), 1 deletion
On 06/30/2015 06:17 AM, Mike Looijmans wrote:
Micron QUAD mode expects command, address and data on 4 lanes instead of just
one for command (extended SPI mode). This requires the controller to be in a
special mode, so check first if the controller could be in that mode. If a
controller does not h
Hi Anurag,
We're struggling with the same issue, our Cadence QSPI controller *does*
handle four-line command, address, and data, but has to be configured
for it. The setting of quad-io-protocol mode in micron_quad_enable is
really jacking up our code. We have to snoop the command stream and
On 05/20/2015 05:26 PM, Brian Norris wrote:
On Mon, Mar 23, 2015 at 08:36:22AM -0500, Graham Moore wrote:
...
I'm fixing the sparse, smatch, unused variables, etc.
...
+ if (n_tx && opcode == SPINOR_OP_WD_EVCR &&
+ !(txbuf[0] & EVCR_QUAD_EN_MICRON))
Howdy folks, Been out of the loop for a while, but does anyone have
anything to say about this driver?
Especially the hacky way it supports Micron quad mode?
Thanks,
Graham
On 03/23/2015 08:36 AM, Graham Moore wrote:
Signed-off-by: Graham Moore
---
V2: use NULL instead of modalias in
Signed-off-by: Graham Moore
---
V2: Add cdns prefix to driver-specific bindings.
V3: Use existing property "is-decoded-cs" instead of creating a duplicate,
"ext-decoder". Timing parameters are in nanoseconds, not master reference
clocks. Remove bus-num completely.
---
...
Signed-off-by: Graham Moore
---
V2: use NULL instead of modalias in spi_nor_scan call
V3: Use existing property is-decoded-cs instead of creating duplicate.
V4: Support Micron quad mode by snooping command stream for EVCR command
and subsequently configuring Cadence controller for quad mode
hanks,
Graham Moore
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On 01/08/2015 04:30 PM, Rob Herring wrote:
This controller only works with flash devices and is different than this one:?
Documentation/devicetree/bindings/spi/spi-cadence.txt
Yes, it is a different controller and is for flash only. The docs call
it the "QSPI Flash Controller".
...
Th
Signed-off-by: Graham Moore
---
.../devicetree/bindings/mtd/cadence_quadspi.txt| 50
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
Signed-off-by: Graham Moore
---
V2: use NULL instead of modalias in spi_nor_scan call
---
drivers/mtd/spi-nor/Kconfig |6 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/cadence-quadspi.c | 1277 +
3 files changed, 1284
On 12/05/2014 04:30 PM, Rafał Miłecki wrote:
Since my commit
mtd: spi-nor: allow NULL as chip name and try to auto detect it
second argument is optional.
Can you simply pass NULL instead of modalias?
OK, passing NULL. Works fine for me, thanks.
-Graham
--
To unsubscribe from this list: se
This patchset provides a driver for the Cadence Quad SPI Flash Controller.
This controller is used on SOCFPGA systems.
The driver was tested on Altera's Cyclone5 and Arria5 dev kits, with
Micron n25q00 and n25q512 flash parts.
Comments from Ezequiel Garcia were incorporated.
Graham Moo
Signed-off-by: Graham Moore
---
.../devicetree/bindings/mtd/cadence_quadspi.txt| 50
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
Signed-off-by: Graham Moore
---
drivers/mtd/spi-nor/Kconfig |6 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/cadence-quadspi.c | 1281 +
3 files changed, 1288 insertions(+)
create mode 100644 drivers/mtd/spi-nor/cadence
On Wed, 12 Nov 2014, bpqw wrote:
> This maybe your spi controller is still extended mode,
> Once EVCR bit 7 is set to 0, the spi nor device will operate in quad
> I/O.Command-address-data line is 4-x-4.
> So after send WRITE EVCR command , spi controller also must transfer to quad
> I/O Mode
QSPI controller and using EVCR quad mode
successfully?
Thanks,
Graham Moore
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Please read the FAQ at http://www.tux.org/lkml/
Signed-off-by: Graham Moore
---
drivers/mtd/spi-nor/Kconfig |6 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/cadence-quadspi.c | 1349 +
3 files changed, 1356 insertions(+)
create mode 100644 drivers/mtd/spi-nor/cadence
Signed-off-by: Graham Moore
---
.../devicetree/bindings/mtd/cadence_quadspi.txt| 30
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
kit.
So here it is, let me know what you all think, please.
Thanks,
Graham Moore
Graham Moore (2):
This is the documentation of the device tree bindings for the
Cadence QSPI Flash Controller driver.
This is a kernel driver for the Cadence QSPI Flash Controller.
It uses t
framework.
Signed-off-by: Graham Moore
--
V2: Increase size of id_bytes array to 8.
---
drivers/mtd/nand/denali.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 9f2012a..0b071a3 100644
--- a/drivers/mtd/nand
framework.
Signed-off-by: Graham Moore
---
drivers/mtd/nand/denali.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 9f2012a..7276125 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
status register in the n25q512ax3 and
n25q00
Micron QSPI flash chips.
Signed-off-by: Graham Moore
---
V4:
Do not set nor->wait_till_ready if driver has already set it.
V3:
Rebase to l2-mtd spinor branch.
V2:
Remove leading underscore in function names.
Remove type cast in dev_err call and
use the
USE_FSR flag is only for Micron chips. But the m25p80 driver doesn't
have access to the flags, they are contained in spi-nor.c. It seems
to me that the driver_data should be accessible by the driver. So
maybe there is room for improvement there.
Thanks,
Graham Moore
--
To un
On Tue, Apr 22, 2014 at 1:45 PM, Gerhard Sittig wrote:
> the patch appears to not have dev_err() references, were they
> removed? see below
[...]
> this emits a message that an error has occured, but doesn't tell
> where it occured -- can you dev_err() here to make the message
> even more helpful?
On Tue, Apr 22, 2014 at 11:55 AM, Marek Vasut wrote:
> Are you sure the n25q512a doesn't use FSR ? Do n25q512a{1,8}3 share the same
> IDs?
I looked at the datasheet and the n25q512a *does* have the same FSR
usage note, so I suppose I should add USE_FSR to it as well. But how
is it working now?
status register in the n25q512ax3 and
n25q00
Micron QSPI flash chips.
Signed-off-by: Graham Moore
---
V3:
Rebase to l2-mtd spinor branch.
V2:
Remove leading underscore in function names.
Remove type cast in dev_err call and use the proper format
specifier instead.
---
drivers/mtd/spi-nor/spi
12ax3 for the id because there are two part numbers for the
512MB part with FSR, n25q512a13 and n25qa512a83. The '83' version has a reset
line.
Graham Moore (1):
Add support for flag status register on Micron chips.
drivers/mtd/spi-nor/s
On Sun, Apr 13, 2014 at 12:18 PM, Marek Vasut wrote:
[...]
>> +#define OPCODE_RDFSR0x70 /* read flag status register */
>
> I know this is not your fault, but can you please indent this properly with
> tabs?
>
>> #define OPCODE_NORM_READ0x03/* Read data bytes (l
On Wed, Apr 9, 2014 at 6:09 AM, Gerhard Sittig wrote:
> On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
>>
>> On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
>> > From: Graham Moore
>> >
>> > This is a slightly diff
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