On Tue, Sep 15, 2020 at 10:55:17AM +0800, Xu Yilun wrote:
> On Mon, Sep 14, 2020 at 02:32:32PM -0700, Moritz Fischer wrote:
> > Hao,
> >
> > On Fri, Sep 11, 2020 at 06:50:18AM +, Wu, Hao wrote:
> > > > On 9/10/20 1:41 AM, Xu Yilun wrote:
> > > > &g
On Mon, Sep 14, 2020 at 11:11:05AM +0300, Alexandru Ardelean wrote:
> On Mon, Aug 10, 2020 at 4:41 PM Alexandru Ardelean
> wrote:
> >
> > These patches synchronize the driver with the current state in the
> > Analog Devices Linux tree:
> > https://github.com/analogdevicesinc/linux/
> >
> > They
On Mon, Aug 10, 2020 at 07:07:14AM -0700, Tom Rix wrote:
>
> On 8/10/20 6:42 AM, Alexandru Ardelean wrote:
> > From: Mircea Caprioru
> >
> > All (newer) FPGA IP cores supported by Analog Devices, store information in
> > the synthesized designs. This information describes various parameters,
> >
Hao,
On Fri, Sep 11, 2020 at 06:50:18AM +, Wu, Hao wrote:
> > On 9/10/20 1:41 AM, Xu Yilun wrote:
> > > On Wed, Sep 09, 2020 at 05:55:33AM -0700, Tom Rix wrote:
> > >> On 9/7/20 10:48 PM, Xu Yilun wrote:
> > >>> In order to support MODULE_DEVICE_TABLE() for dfl device driver, this
> > >>>
On Sun, Sep 13, 2020 at 05:10:01PM -0700, Moritz Fischer wrote:
> Replace pci_enable_device() with its devres counterpart
> pcim_enable_device().
>
> Signed-off-by: Moritz Fischer
> ---
> drivers/net/ethernet/dec/tulip/de2104x.c | 7 ++-
> 1 file changed, 2 inser
Replace devm_alloc_etherdev() with its devres version.
Signed-off-by: Moritz Fischer
---
drivers/net/ethernet/dec/tulip/de2104x.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/dec/tulip/de2104x.c
b/drivers/net/ethernet/dec/tulip/de2104x.c
index
Replace pci_enable_device() with its devres counterpart
pcim_enable_device().
Signed-off-by: Moritz Fischer
---
drivers/net/ethernet/dec/tulip/de2104x.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/dec/tulip/de2104x.c
b/drivers/net/ethernet
Replace an instance of kmemdup() with the devres counted version
instead.
Signed-off-by: Moritz Fischer
---
drivers/net/ethernet/dec/tulip/de2104x.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/dec/tulip/de2104x.c
b/drivers/net/ethernet/dec
This series is the first bunch of minor cleanups for the de2104x driver
to make it look and behave more like a modern driver.
These changes replace some of the non-devres versions with devres
versions of functions to simplify the error paths.
Next up after this will be the ioremap part.
Moritz
ssion e1, e2, e3, e4;
> @@
> -pci_dma_sync_sg_for_device(e1, e2, e3, e4)
> +dma_sync_sg_for_device(>dev, e2, e3, e4)
>
> @@
> expression e1, e2;
> @@
> -pci_dma_mapping_error(e1, e2)
> +dma_mapping_error(>dev, e2)
>
> @@
> expression e1, e2;
> @@
>
0 eth0: rx work limit reached
> [ 102.251387] de2104x :17:00.0 eth0: rx work limit reached
> [ 102.267444] de2104x :17:00.0 eth0: rx work limit reached
>
> Signed-off-by: Lucy Yan
Reviewed-by: Moritz Fischer
> ---
> drivers/net/ethernet/dec/tulip/de2104x.c | 2 +-
>
Hi Xu,
On Mon, Sep 07, 2020 at 10:23:13PM +0800, Xu Yilun wrote:
> A new bus type "dfl" is introduced for private features which are not
> initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
> private features could be handled by separate driver modules.
>
> DFL feature
On Mon, Sep 07, 2020 at 10:23:13PM +0800, Xu Yilun wrote:
> A new bus type "dfl" is introduced for private features which are not
> initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
> private features could be handled by separate driver modules.
>
> DFL feature drivers
Hi Xu,
On Wed, Aug 19, 2020 at 03:45:21PM +0800, Xu Yilun wrote:
> This patch adds support for the Nios handshake private feature on Intel
> PAC (Programmable Acceleration Card) N3000.
>
> The Nios is the embedded processor on the FPGA card. This private feature
> provides a handshake interface
Hi Xu,
On Wed, Aug 19, 2020 at 03:45:20PM +0800, Xu Yilun wrote:
> A new bus type "dfl" is introduced for private features which are not
> initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
> private features could be handled by separate driver modules.
>
> DFL feature
Hi Russ,
On Fri, Sep 04, 2020 at 04:52:54PM -0700, Russ Weight wrote:
> Create the Intel Security Manager class driver. The security
> manager provides interfaces to manage secure updates for the
> FPGA and BMC images that are stored in FLASH. The driver can
> also be used to update root entry
On Wed, Aug 19, 2020 at 03:45:19PM +0800, Xu Yilun wrote:
> This patch makes preparation for modularization of DFL sub feature
> drivers.
>
> DFL based FPGA devices may contain some IP blocks which are already
> supported by kernel, most of them are supported by platform device
> drivers. We
On Sun, Aug 30, 2020 at 06:38:50PM +0200, Luca Ceresoli wrote:
> When the DONE pin does not go high after programming to confirm programming
> success, the INIT_B pin provides some info on the reason. Use it if
> available to provide a more explanatory error message.
>
> Reviewed-by: Tom Rix
>
On Sun, Aug 30, 2020 at 06:38:49PM +0200, Luca Ceresoli wrote:
> Current code calls gpiod_get_value() without error checking. Should the
> GPIO controller fail, execution would continue without any error message.
>
> Fix by checking for negative error values.
>
> Reported-by: Tom Rix
>
On Sun, Aug 30, 2020 at 06:38:48PM +0200, Luca Ceresoli wrote:
> If this routine sleeps because it was scheduled out, it might miss DONE
> going asserted and consider it a timeout. This would potentially make the
> code return an error even when programming succeeded. Rewrite the loop to
> always
On Sun, Aug 30, 2020 at 06:38:46PM +0200, Luca Ceresoli wrote:
> Remove comment committed by mistake.
>
> Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
> write_init")
> Reviewed-by: Tom Rix
> Signed-off-by: Luca Ceresoli
>
> ---
>
> Changes in v4:
> - add
On Sun, Aug 30, 2020 at 06:38:47PM +0200, Luca Ceresoli wrote:
> Most dev_err messages in this file have no final dot. Remove the only two
> exceptions to make them consistent.
>
> Reviewed-by: Tom Rix
> Signed-off-by: Luca Ceresoli
>
> ---
>
> Changes in v4:
> - add Reviewed-by Tom Rix
>
>
Hi Xu,
On Wed, Aug 19, 2020 at 03:45:18PM +0800, Xu Yilun wrote:
> This patchset makes it possible to develop independent driver modules
> for DFL private features. It also helps to leverage existing kernel
> drivers to enable some IP blocks in DFL.
>
> Patch #1: Release the dfl mmio regions
On Thu, Aug 13, 2020 at 05:04:09PM +0800, Xu Yilun wrote:
> On Thu, Aug 13, 2020 at 08:28:05AM +, David Laight wrote:
> > From: Xu Yilun
> > > Sent: 13 August 2020 08:59
> > > On Wed, Aug 12, 2020 at 08:52:39AM +, David Laight wrote:
> > > > From: M
On Mon, Aug 17, 2020 at 06:59:09PM +0200, Luca Ceresoli wrote:
> Remove comment committed by mistake.
>
> Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
> write_init")
> Signed-off-by: Luca Ceresoli
> ---
> drivers/fpga/xilinx-spi.c | 1 -
> 1 file changed, 1
On Mon, Aug 10, 2020 at 10:41:10AM +0800, Xu Yilun wrote:
> The feature id is stored in a 12 bit field in DFH. So a u16 variable is
> enough for feature id.
>
> This patch changes all feature id related places to fit u16.
>
> Signed-off-by: Xu Yilun
> Reviewed-by: Tom Rix
> Acked-by: Wu Hao
>
; > > M: Wu Hao
> > > +R: Tom Rix
> > > L: linux-f...@vger.kernel.org
> > > S: Maintained
> > > F: Documentation/fpga/dfl.rst
> > > @@ -6813,6 +6814,7 @@ F: include/uapi/linux/fpga-dfl.h
> > >
> > &
On Fri, Jul 24, 2020 at 11:10:09AM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA
> reconfiguration process stops and the user can't perform a new FPGA
> reconfiguration properly.
>
> Set FPGA task to
ix
> L: linux-f...@vger.kernel.org
> S: Maintained
> F: Documentation/fpga/dfl.rst
> @@ -6813,6 +6814,7 @@ F: include/uapi/linux/fpga-dfl.h
>
> FPGA MANAGER FRAMEWORK
> M: Moritz Fischer
> +R: Tom Rix
> L: linux-f...@vger.kernel.org
> S: Ma
.
All patches have been reviewed on the mailing list, and have been in the
last few linux-next releases (as part of my for-next branch) without issues.
Signed-off-by: Moritz Fischer
Gustavo A. R. Silva (1):
fpga: dfl: Use
in the reset of a port.
Xu'x fix addresses a linter warning.
All patches have been reviewed on the mailing list, and have been in the
last few linux-next releases (as part of my fixes branch) without issues.
Signed-off-by: Moritz Fischer
On Mon, Jul 13, 2020 at 09:47:46AM +0800, Xu Yilun wrote:
> Add PCIe Device ID for Intel FPGA PAC N3000.
>
> Signed-off-by: Wu Hao
> Signed-off-by: Xu Yilun
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Russ Weight
> Reviewed-by: Wu Hao
> Reviewed-by: Tom Rix
> ---
>
On Fri, Jul 10, 2020 at 06:14:19AM +, Wu, Hao wrote:
> > On Thu, Jul 09, 2020 at 06:00:40AM -0700, Tom Rix wrote:
> > >
> > > On 7/9/20 3:14 AM, Wu, Hao wrote:
> > > >> On Thu, Jul 09, 2020 at 05:10:49PM +0800, Wu, Hao wrote:
> > > Subject: [PATCH] fpga: dfl: pci: add device id for Intel
On Tue, Jun 16, 2020 at 12:08:48PM +0800, Xu Yilun wrote:
> This patch adds introductions of interrupt related interfaces for FME
> error reporting, port error reporting and AFU user interrupts features.
>
> Signed-off-by: Luwei Kang
> Signed-off-by: Wu Hao
> Signed-off-by: Xu Yilun
>
On Tue, Jun 16, 2020 at 12:08:46PM +0800, Xu Yilun wrote:
> Error reporting interrupt is very useful to notify users that some
> errors are detected by the hardware. Once users are notified, they
> could query hardware logged error states, no need to continuously
> poll on these states.
>
> This
On Tue, Jun 16, 2020 at 12:08:47PM +0800, Xu Yilun wrote:
> AFU (Accelerated Function Unit) is dynamic region of the DFL based FPGA,
> and always defined by users. Some DFL based FPGA cards allow users to
> implement their own interrupts in AFU. In order to support this,
> hardware implements a
On Tue, Jun 16, 2020 at 12:08:45PM +0800, Xu Yilun wrote:
> Error reporting interrupt is very useful to notify users that some
> errors are detected by the hardware. Once users are notified, they
> could query hardware logged error states, no need to continuously
> poll on these states.
>
> This
On Tue, Jun 16, 2020 at 12:08:44PM +0800, Xu Yilun wrote:
> FPGA user applications may be interested in interrupts generated by
> DFL features. For example, users can implement their own FPGA
> logics with interrupts enabled in AFU (Accelerated Function Unit,
> dynamic region of DFL based FPGA).
On Tue, Jun 16, 2020 at 12:08:42PM +0800, Xu Yilun wrote:
> DFL based FPGA devices could support interrupts for different purposes,
> but current DFL framework only supports feature device enumeration with
> given MMIO resources information via common DFL headers. This patch
> introduces one new
On Tue, Jun 16, 2020 at 12:08:43PM +0800, Xu Yilun wrote:
> Some DFL FPGA PCIe cards (e.g. Intel FPGA Programmable Acceleration
> Card) support MSI-X based interrupts. This patch allows PCIe driver
> to prepare and pass interrupt resources to DFL via enumeration API.
> These interrupt resources
On Mon, Jun 22, 2020 at 03:37:23PM +0200, Luca Ceresoli wrote:
> The INIT_B pin reports the status during startup and after the end of the
> programming process. However the current driver completely ignores it.
>
> Check the pin status during startup to make sure programming is never
> started
On Mon, Jun 22, 2020 at 03:37:22PM +0200, Luca Ceresoli wrote:
> The INIT_B is used by the 6 and 7 series to report the programming status,
> providing more control and information about programming errors.
>
> Signed-off-by: Luca Ceresoli
>
> ---
>
> Changes in v2:
> - rename init_b-gpios to
Will look at it this week.
- Moritz
On Mon, Jun 22, 2020 at 10:30 PM Xu Yilun wrote:
>
> On Mon, Jun 22, 2020 at 05:27:20AM -0700, Tom Rix wrote:
> > In addition to reviewing, I have run these changes on the pac a10 card and
> > while i do not have an afu using interrupts, I have exercised
On Wed, Jun 17, 2020 at 05:10:39PM -0500, Gustavo A. R. Silva wrote:
> Make use of the struct_size() helper instead of an open-coded version
> in order to avoid any potential type mistakes. Also, remove unnecessary
> function dfl_feature_platform_data_size().
>
> This code was detected with the
On Mon, Jun 08, 2020 at 05:54:46AM -0700, t...@redhat.com wrote:
> From: Tom Rix
>
> Using clang's scan-build/view this issue was flagged
> a dead store issue in fpga-bridge.c
>
> warning: Value stored to 'ret' is never read [deadcode.DeadStores]
> ret = id;
>
>
On Mon, Jun 08, 2020 at 05:54:45AM -0700, t...@redhat.com wrote:
> From: Tom Rix
>
> Using clang's scan-build/view this issue was flagged in fpga-mgr.c
>
> drivers/fpga/fpga-mgr.c:585:3: warning: Value stored to 'ret' is never read
> [deadcode.DeadStores]
> ret = id;
>
>
On Thu, Jun 11, 2020 at 11:11:42PM +0200, Luca Ceresoli wrote:
> Using variables does not add readability here: parameters passed
> to udelay*() are obviously in microseconds and their meaning is clear
> from the context.
>
> The type is also wrong, udelay expects an unsigned long.
>
>
On Thu, Jun 11, 2020 at 11:11:41PM +0200, Luca Ceresoli wrote:
> The Xilinx 7-series uses the same protocol, mention that.
>
> Signed-off-by: Luca Ceresoli
> ---
> drivers/fpga/xilinx-spi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/xilinx-spi.c
On Wed, Jun 17, 2020 at 04:38:41PM -0600, Rob Herring wrote:
> On Thu, 11 Jun 2020 23:11:40 +0200, Luca Ceresoli wrote:
> > The Xilinx 7-series uses the same protocol, mention that.
> >
> > Signed-off-by: Luca Ceresoli
> > ---
> > .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9
Hi Luca,
On Thu, Jun 11, 2020 at 11:11:44PM +0200, Luca Ceresoli wrote:
> The INIT_B reports the status during startup and after the end of the
> programming process. However the current driver completely ignores it.
>
> Check the pin status during startup to make sure programming is never
>
On Thu, Jun 11, 2020 at 11:11:40PM +0200, Luca Ceresoli wrote:
> The Xilinx 7-series uses the same protocol, mention that.
>
> Signed-off-by: Luca Ceresoli
Acked-by: Moritz Fischer
> ---
> .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++---
> 1 file cha
On Wed, May 27, 2020 at 12:10:21AM +, Wu, Hao wrote:
> > -Original Message-
> > From: John Hubbard
> > Sent: Tuesday, May 26, 2020 6:18 AM
> > To: LKML
> > Cc: John Hubbard ; Xu, Yilun ;
> > Wu, Hao ; Moritz Fischer ; linux-
> > f...@vger.ke
On Fri, May 29, 2020 at 08:15:15AM -0500, Richard Gong wrote:
> Hi Moritz,
>
> Sorry for asking.
>
> When you get chance, can you review my version 2 patch submitted on
> 05/15/20?
>
> Regards,
> Richard
>
> On 5/15/20 9:35 AM, richard.g...@linux.intel.com wrote:
> > From: Richard Gong
> >
>
tems' use of those pages.
> >
> > [1] Documentation/core-api/pin_user_pages.rst
> >
> > [2] "Explicit pinning of user-space pages":
> > https://lwn.net/Articles/807108/
> >
> > Cc: Xu Yilun
> > Cc: Wu Hao
> > Cc: Moritz Fische
Hi Richard,
On Tue, May 12, 2020 at 08:27:31AM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> The reconfiguration mode is pre-set by driver as the full reconfiguration.
> As a result, user have to change code and recompile the drivers if he or
> she wants to perform a
On Mon, Apr 20, 2020 at 04:11:39PM +0800, Xu Yilun wrote:
> FPGA user applications may be interested in interrupts generated by
> DFL features. For example, users can implement their own FPGA
> logics with interrupts enabled in AFU (Accelerated Function Unit,
> dynamic region of DFL based FPGA).
On Mon, Apr 20, 2020 at 04:11:38PM +0800, Xu Yilun wrote:
> Some DFL FPGA PCIe cards (e.g. Intel FPGA Programmable Acceleration
> Card) support MSI-X based interrupts. This patch allows PCIe driver
> to prepare and pass interrupt resources to DFL via enumeration API.
> These interrupt resources
On Mon, Apr 20, 2020 at 04:11:37PM +0800, Xu Yilun wrote:
> DFL based FPGA devices could support interrupts for different purposes,
> but current DFL framework only supports feature device enumeration with
> given MMIO resources information via common DFL headers. This patch
> introduces one new
Hi Nava,
On Mon, May 04, 2020 at 11:55:23AM +, Nava kishore Manne wrote:
> Hi Mortiz,
>
> Thanks for proving the comments.
> Please find my response inline.
>
> > -Original Message-----
> > From: Moritz Fischer [mailto:m...@kernel.org]
> > Sent:
On Tue, May 05, 2020 at 04:00:11PM +0200, Arnd Bergmann wrote:
> Two symbols need to be exported to allow the zynqmp-fpga module
> to get loaded dynamically:
>
> ERROR: modpost: "zynqmp_pm_fpga_load" [drivers/fpga/zynqmp-fpga.ko] undefined!
> ERROR: modpost: "zynqmp_pm_fpga_get_status"
Hi Xu,
On Tue, May 5, 2020 at 10:13 PM Xu Yilun wrote:
>
> Hi Moritz:
>
> Hao and I did several rounds of review and fix in the mailing list. Now
> the patches are all acked by Hao.
>
> Could you please help review it when you have time?
I'll get to it this weekend. Sorry for the delay,
Moritz
On Mon, Apr 27, 2020 at 08:44:33AM +0200, Sascha Hauer wrote:
> On Fri, Apr 24, 2020 at 08:59:49PM -0700, Moritz Fischer wrote:
> > Hi Sascha,
> >
> > On Thu, Apr 23, 2020 at 08:23:31AM +0200, Sascha Hauer wrote:
> > > Hi Moritz,
> > >
> > >
Hi Matthew, Yilun
On Tue, Apr 28, 2020 at 03:06:07PM -0700, matthew.gerl...@linux.intel.com wrote:
> Hi Yilun,
>
> You raise some very interesting questions. Please see
> my comments below.
>
> Matthew
>
> On Tue, 28 Apr 2020, Xu Yilun wrote:
>
> > Hi,
> >
> > I wonder if an updating of FPGA
Hi Thor,
On Mon, Oct 07, 2019 at 01:06:51PM -0500, Thor Thayer wrote:
> Hi Moritz,
>
> On 9/27/19 1:23 PM, Moritz Fischer wrote:
> > Thor,
> >
> > On Fri, Sep 27, 2019 at 09:32:11AM -0500, Thor Thayer wrote:
> > > Hi Kedar & Moritz,
> > >
> &
Thor,
On Fri, Sep 27, 2019 at 09:32:11AM -0500, Thor Thayer wrote:
> Hi Kedar & Moritz,
>
> On 9/27/19 12:13 AM, Appana Durga Kedareswara Rao wrote:
> > Hi Alan,
> >
> > Did you get a chance to send your framework changes to upstream?
No they weren't upstreamed
From: Moritz Fischer
Add forward declaration for struct gpio_desc in order to address
the following:
./include/linux/phy_fixed.h:48:17: error: 'struct gpio_desc' declared inside
parameter list [-Werror]
./include/linux/phy_fixed.h:48:17: error: its scope is only this definition or
declaration
not what you want [-Werror]
Fixes commit 71bd106d2567 ("net: fixed-phy: Add
fixed_phy_register_with_gpiod() API")
Signed-off-by: Moritz Fischer
---
include/linux/phy_fixed.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/phy_fixed.h b/include/linux/phy_fixed.h
index 1e
);
> -... }
> |
> ...
> -dev_err(...);
> )
> ...
> }
> //
>
> While we're here, remove braces on if statements that only have one
> statement (manually).
>
> Cc: Moritz Fischer
> Cc: linux-f...@vger.kernel.org
> Cc: Greg Kroah-Hartman
> Signed-
.
This patchset adds support for the v2 revision of Intel (Altera)'s CVP
parts including the Stratix 10.
All of this patches have been reviewed and been in the last few
linux-next releases without issues.
Signed-off-by: Moritz Fischer
Hi Thor,
On Mon, Aug 19, 2019 at 03:48:05PM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
> Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
>
> Most of the CvP registers and their
receives -EPROBE_DEFER when trying to obtain a GPIO desc.
Signed-off-by: Moritz Fischer
Phil Reid (1):
fpga: altera-ps-spi: Fix getting of optional confd gpio
drivers/fpga/altera-ps-spi.c | 11 +++
1 file changed, 7
the FPGA bridge bindings by consolidating them instead of repeating
the same paragraph over and over again.
All of these patches have been in the last few linux-next releases
without issues.
Signed-off-by: Moritz Fischer
Carlos
On Thu, Jul 25, 2019 at 10:16:48AM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Add Stratix10 specific functions that use a credit mechanism
> to throttle data to the CvP FIFOs. Add a private structure
> with function pointers for V1 vs V2 functions.
>
> Signed-off-by: Thor
Move the linux-fpga tree to new location at:
git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga.git
Signed-off-by: Moritz Fischer
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..c3b5e3dbc74e 100644
Hi Thor,
On Thu, Jul 25, 2019 at 10:16:45AM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
> Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
>
> Most of the CvP registers and their
Hi Thor,
On Wed, Jul 24, 2019 at 11:59:12AM -0500, Thor Thayer wrote:
> Hi Moritz,
>
> On 7/24/19 9:57 AM, Moritz Fischer wrote:
> > On Tue, Jul 23, 2019 at 09:40:51AM -0500, Thor Thayer wrote:
> > > Hi Moritz,
> > >
> > > On 7/21/19 7
On Tue, Jul 23, 2019 at 09:40:51AM -0500, Thor Thayer wrote:
> Hi Moritz,
>
> On 7/21/19 7:59 PM, Moritz Fischer wrote:
> > Thor,
> >
> > On Tue, Jul 16, 2019 at 05:48:06PM -0500, thor.tha...@linux.intel.com wrote:
> > > From: Thor Thayer
> > >
&
On Wed, Jul 24, 2019 at 09:20:56AM +0200, Greg KH wrote:
> On Tue, Jul 23, 2019 at 10:20:12PM -0700, Moritz Fischer wrote:
> > The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
> >
> > Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
> >
&
as builtin while a dependency is built as a
module.
This has been on the list for a while and I've reviewed it.
Signed-off-by: Moritz Fischer
YueHaibing (1):
fpga-manager: altera-ps-spi: Fix build error
drivers/fpga/Kconfig
Thor,
On Tue, Jul 16, 2019 at 05:48:06PM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> In preparation for adding newer V2 parts that use a FIFO,
> reorganize altera_cvp_chk_error() and change the write
> function to block based.
> V2 parts have a block size matching the FIFO
Hi Thor,
looks mostly good.
On Tue, Jul 16, 2019 at 05:48:07PM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Add Stratix10 specific functions that use a credit mechanism
> to throttle data to the CvP FIFOs. Add a private structure
> with function pointers for V1 vs V2
Hi Thor,
On Thu, Jul 11, 2019 at 03:32:50PM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Add Stratix10 specific functions that use a credit mechanism
> to throttle data to the CvP FIFOs. Add a private structure
> with function pointers for V1 vs V2 functions.
>
>
Hi Thor,
On Thu, Jul 11, 2019 at 03:32:49PM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> In preparation for adding newer V2 parts that use a FIFO,
> reorganize altera_cvp_chk_error() and change the write
> function to block based.
> V2 parts have a block size matching the
On Thu, Jul 11, 2019 at 03:32:48PM -0500, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Newer Intel FPGAs have different Vendor Specific offsets than
> legacy parts. Use PCI discovery to find the CvP registers.
> Since the register positions remain the same, change the hard
> coded
pends on SPI
> + select BITREVERSE
> help
> FPGA manager driver support for Altera Arria/Cyclone/Stratix
> using the passive serial interface over SPI.
> --
> 2.7.4
>
>
Acked-by: Moritz Fischer
Hi Wu,
On Thu, Jun 27, 2019 at 12:44:45PM +0800, Wu Hao wrote:
> This patch adds virtualization support description for DFL based
> FPGA devices (based on PCIe SRIOV), and introductions to new
> interfaces added by new dfl private feature drivers.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu
Make alt_pr_unregister function void, since it always returns 0,
and nothing would act on the value anyways.
Signed-off-by: Moritz Fischer
---
drivers/fpga/altera-pr-ip-core-plat.c | 4 +++-
drivers/fpga/altera-pr-ip-core.c | 4 +---
include/linux/fpga/altera-pr-ip-core.h | 2 +-
3 files
Hi Greg,
please take this cleanup patch.
It's been on the list but somehow fell through the cracks.
Thanks,
Moritz
Enrico Weigelt (1):
drivers: fpga: Kconfig: pedantic cleanups
drivers/fpga/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--
2.22.0
From: Enrico Weigelt
Formatting of Kconfig files doesn't look so pretty, so just
take damp cloth and clean it up.
Signed-off-by: Enrico Weigelt
Signed-off-by: Moritz Fischer
---
drivers/fpga/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/fpga
K: fmc_d.*register
>
> FPGA MANAGER FRAMEWORK
> -M: Alan Tull
> M: Moritz Fischer
> L: linux-f...@vger.kernel.org
> S: Maintained
> --
> 2.21.0
>
Cheers,
Moritz
Hi Scott,
On Wed, May 08, 2019 at 04:39:51PM -0500, Scott Wood wrote:
> On Mon, 2019-04-15 at 14:22 -0500, Alan Tull wrote:
> > On Thu, Apr 11, 2019 at 11:36 AM Moritz Fischer
> > wrote:
> >
> > Hi Scott,
> >
> > Thanks!
> >
> > > Hi Scott
the EPROBE_DEFER value in a
special manner.
Fixes commit c09f7471127e ("fpga manager: Adding FPGA Manager support for
Xilinx zynqmp")
Reported-by: Dan Carpenter
Signed-off-by: Moritz Fischer
---
Changes from v1:
- Address Alan's feedback regarding handling both occurences.
---
drivers/f
Alan,
On Tue, May 07, 2019 at 02:11:06PM -0500, Alan Tull wrote:
> On Tue, May 7, 2019 at 12:03 PM Moritz Fischer wrote:
>
> Hi Moritz,
>
> >
> > Fixes the following static checker error:
> >
> > drivers/fpga/zynqmp-fpga.c:50 zynqmp_fpga_ops_write()
> >
Please for next round:
+CC linux-hwmon, Guenter etc ...
On Mon, Apr 29, 2019 at 04:55:48PM +0800, Wu Hao wrote:
> This patch adds support to thermal management private feature for DFL
> FPGA Management Engine (FME). This private feature driver registers
> a hwmon for thermal/temperature
Z
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Acked-by: Alan Tull
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-pci.c | 40
> drivers/fpga/dfl.c | 41 +
> drivers/fpga/dfl
form device of given port back to PF, it configures
>PF/VF access mode to PF, then adds port platform device back to
>re-enable related userspace interfaces on PF.
>
> Signed-off-by: Zhang Yi Z
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Acked-by: Alan Tull
m files to driver.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Acked-by: Alan Tull
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-fme-pr.c | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/fpga/dfl-fme-pr.c b/
On Mon, Apr 29, 2019 at 04:55:35PM +0800, Wu Hao wrote:
> This patch removes copy_to_user() code in partial reconfiguration
> ioctl, as it's useless as user never needs to read the data
> structure after ioctl.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
Acked-
pport for
Xilinx zynqmp")
Reported-by: Dan Carpenter
Signed-off-by: Moritz Fischer
---
drivers/fpga/zynqmp-fpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
index f7cbaadf49ab..abcb0b2e75bf 100644
--- a/drivers/f
.
>
> Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver")
> Signed-off-by: Wen Yang
> Cc: Alan Tull
> Cc: Moritz Fischer
> Cc: Nicolas Saenz Julienne
> Cc: linux-f...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
Reviewed-by: Moritz
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