On Fri, 19 Jun 2020, Chen Tao wrote:
> Fix memory leak in omap_hwmod_allocate_module not freeing in
> handling error path.
>
> Fixes: 8c87970543b17("ARM: OMAP2+: Add functions to allocate module data from
> device tree")
> Signed-off-by: Chen Tao
Reviewed-by: Paul Walmsley
- Paul
On Tue, 12 May 2020, Rob Herring wrote:
> The 'reg' description and example have a 2nd register region for memory
> mapped flash, but the schema says there is only 1 region. Fix this.
>
> Cc: Mark Brown
> Cc: Palmer Dabbelt
> Cc: Paul Walmsley
> Cc: linux-...
+ hch
On Wed, 23 Oct 2019, Alan Mikhak wrote:
> From: Alan Mikhak
>
> Modify plic_init() to skip .dts interrupt contexts other
> than supervisor external interrupt.
Might be good to explain the motivation here.
>
> Signed-off-by: Alan Mikhak
> ---
> drivers/irqchip/irq-sifive-plic.c | 4 ++
On Wed, 23 Oct 2019, Alistair Francis wrote:
> On Tue, 2019-10-22 at 18:06 -0700, Paul Walmsley wrote:
> > On Tue, 22 Oct 2019, Alistair Francis wrote:
> >
> > > I think it makese sense for this to go into Linux first.
> > >
> > > The QEMU patches are g
On Wed, 23 Oct 2019, Anup Patel wrote:
> On Wed, Oct 23, 2019 at 11:30 AM Paul Walmsley
> wrote:
>
> > Is drivers/platform/goldfish/goldfish_pipe.c required for the Goldfish RTC
> > driver or not?
>
> No, it's not required.
>
> > If not, then the firs
On Wed, 23 Oct 2019, Anup Patel wrote:
> On Wed, Oct 23, 2019 at 6:37 AM Paul Walmsley
> wrote:
>
> > Incidentally, just looking at drivers/platform/goldfish, that driver seems
> > to be some sort of Google-specific RPC driver. Are you all really sure
>
> Nopes, it
On Tue, 22 Oct 2019, Alistair Francis wrote:
> I think it makese sense for this to go into Linux first.
>
> The QEMU patches are going to be accepted, just some nit picking to do
> first :)
>
> After that we have to wait for a PR and then a QEMU release until most
> people will see the change in
On Tue, 22 Oct 2019, David Abdurachmanov wrote:
> Failed to compile Fedora/RISCV kernel (5.4-rc3+) with sparsemem enabled:
>
> fs/proc/kcore.c: In function 'read_kcore':
> fs/proc/kcore.c:510:8: error: implicit declaration of function
> 'kern_addr_valid'; did you mean 'virt_addr_valid'?
> [-Wer
Linus,
The following changes since commit 5bf4e52ff0317db083fafee010dc806f8d4cb0cb:
RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_START
(2019-10-15 22:47:41 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
t
On Mon, 14 Oct 2019, Anup Patel wrote:
> > -Original Message-
> > From: Palmer Dabbelt
> > Sent: Saturday, October 12, 2019 11:09 PM
> > To: Anup Patel
> > Cc: Paul Walmsley ; a...@eecs.berkeley.edu;
> > Greg KH ; r...@google.com; Atish Patra
&g
Hi Eric,
On Mon, 21 Oct 2019, Eric Biggers wrote:
> The kbuild test robot reported a build error on RISC-V in this patch:
>
> https://patchwork.kernel.org/patch/11182389/
>
> ... because of the line:
>
> if (!xchg(&mode->logged_impl_name, true)) {
>
> where logged_impl_name is a '
On Thu, 17 Oct 2019, Christoph Hellwig wrote:
> Many of the privileged CSRs exist in a supervisor and machine version
> that are used very similarly. Provide a new X-naming layer so that
> we don't have to ifdef everywhere for M-mode Linux support.
>
> Contains contributions from Damien Le Moal
On Fri, 18 Oct 2019, Christoph Hellwig wrote:
> On Thu, Oct 17, 2019 at 08:29:59PM -0700, Paul Walmsley wrote:
> > On Fri, 18 Oct 2019, Anup Patel wrote:
> >
> > > It will be really cool to have this series for Linux-5.4-rcX.
> >
> > It's way too big to
some confusion.
Greentime Hu (1):
RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_START
Paul Walmsley (2):
riscv: dts: HiFive Unleashed: add default chosen/stdout-path
riscv: tlbflush: remove confusing comment on local_flush_tlb_all()
On Fri, 18 Oct 2019, Atish Patra wrote:
> On Fri, 2019-10-18 at 01:43 -0700, Paul Walmsley wrote:
> > On Wed, 9 Oct 2019, Atish Patra wrote:
> >
> > > Currently, isa string is read and checked for correctness at
> > > multiple places.
> > >
> >
On Wed, 9 Oct 2019, Atish Patra wrote:
> Currently, isa string is read and checked for correctness at multiple
> places.
>
> Consolidate them into one function and use it only during early bootup.
> In case of a incorrect isa string, the cpu shouldn't boot at all.
>
> Signed-off-by: Atish Patra
On Wed, 9 Oct 2019, Atish Patra wrote:
> /proc/cpuinfo should just print all the isa string as an information
> instead of determining what is supported or not. ELF hwcap can be
> used by the userspace to figure out that.
>
> Simplify the isa string printing by removing the unsupported isa string
functional impact.
Signed-off-by: Paul Walmsley
Fixes: 007f5c358957 ("Refactor FPU code in signal setup/return procedures")
Cc: Alan Kao
---
arch/riscv/kernel/signal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/k
?
Fix by adding the missing prototypes to the appropriate header files.
This change should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/include/asm/irq.h | 3 +++
arch/riscv/include/asm/pgtable.h | 2 ++
arch/riscv/include/asm/processor.h | 4
arch/
mbol 'early_pmd' was not declared.
Should it be static?
arch/riscv/mm/sifive_l2_cache.c:145:12: warning: symbol 'sifive_l2_init' was
not declared. Should it be static?
Resolve these warnings by marking them as static.
Signed-off-by: Paul Walmsley
---
arch/riscv/kerne
; was
not declared. Should it be static?
arch/riscv/kernel/ptrace.c:175:6: warning: symbol 'do_syscall_trace_exit' was
not declared. Should it be static?
Based on a suggestion from Luc Van Oostenryck.
Signed-off-by: Paul Walmsley
Cc: Luc Van Oostenryck
---
arch/riscv/kernel/ptrac
lared.
Should it be static?
Fix by including the appropriate header files in the appropriate
source files.
This patch should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/include/asm/irq.h| 3 +++
arch/riscv/include/asm/switch_to.h | 1 +
arch/riscv/kernel/cp
patch should have no functional impact.
Signed-off-by: Paul Walmsley
Reviewed-by: Luc Van Oostenryck
Link:
https://lore.kernel.org/linux-riscv/caahsdy2nx2lweeazumtw_bygtkho6kauevvxrnba_enejmf...@mail.gmail.com/T/#mc1a58bc864f71278123d19a7abc083a9c8e37033
---
arch/riscv/mm/init.c | 3 +--
1 file
?
This change should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/kernel/head.h| 21 +
arch/riscv/kernel/setup.c | 2 ++
arch/riscv/kernel/smpboot.c | 2 ++
arch/riscv/mm/fault.c | 2 ++
arch/riscv/mm/init.c| 2 ++
5 files cha
warning: symbol 'trap_init' was not declared.
Should it be static?
This change should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/kernel/entry.h | 29 +
arch/riscv/kernel/signal.c | 2 ++
arch/riscv/kernel/traps.c | 2 ++
xes branch that is based on v5.4-rc3.
- Paul
Paul Walmsley (8):
riscv: add prototypes for assembly language functions from entry.S
riscv: add prototypes for assembly language functions from head.S
riscv: init: merge split string literals in preprocessor directive
riscv: add missing prototyp
On Fri, 18 Oct 2019, Luc Van Oostenryck wrote:
> I quickly checked and gcc also complain about the second line:
> $ cat y.c
> #ifndef __riscv_cmodel_medany
> #error "setup_vm() is called from head.S before relocate so it should "
>"not use absolute addressing."
> #endif
>
> $
On Fri, 18 Oct 2019, Luc Van Oostenryck wrote:
> On Thu, Oct 17, 2019 at 05:49:26PM -0700, Paul Walmsley wrote:
> > sparse identifies these missing prototypes when building arch/riscv:
> >
> > arch/riscv/kernel/cpu.c:149:29: warning: symbol 'cpuinfo_op' was not
&g
On Fri, 18 Oct 2019, Anup Patel wrote:
> It will be really cool to have this series for Linux-5.4-rcX.
It's way too big to go in via the -rc series. I'm hoping to have it ready
to go for v5.5-rc1.
- Paul
On Fri, 18 Oct 2019, Luc Van Oostenryck wrote:
> On Thu, Oct 17, 2019 at 05:49:25PM -0700, Paul Walmsley wrote:
> > Static analysis tools such as sparse don't set the RISC-V C model
> > preprocessor directives such as "__riscv_cmodel_medany", set by the C
> >
On Fri, 18 Oct 2019, Luc Van Oostenryck wrote:
> On Thu, Oct 17, 2019 at 05:49:24PM -0700, Paul Walmsley wrote:
> > sparse complains loudly when string literals associated with
> > preprocessor directives are split into multiple, separately quoted
> > strings a
On Thu, 17 Oct 2019, Paul Walmsley wrote:
> Add prototypes for assembly language functions defined in head.S,
> and include these prototypes into C source files that call those
> functions.
[ ... ]
> diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
> index 96add1427a7
lared.
Should it be static?
Fix by including the appropriate header files in the appropriate
source files.
This patch should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/include/asm/irq.h| 3 +++
arch/riscv/include/asm/switch_to.h | 1 +
arch/riscv/kernel/cp
mbol 'early_pmd' was not declared.
Should it be static?
arch/riscv/mm/sifive_l2_cache.c:145:12: warning: symbol 'sifive_l2_init' was
not declared. Should it be static?
Resolve these warnings by marking them as static.
Signed-off-by: Paul Walmsley
---
arch/riscv/kerne
functional impact.
Signed-off-by: Paul Walmsley
Fixes: 007f5c358957 ("Refactor FPU code in signal setup/return procedures")
Cc: Alan Kao
---
arch/riscv/kernel/signal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/k
arch/riscv/kernel/ptrace.c:151:6: warning: symbol 'do_syscall_trace_enter' was
not declared. Should it be static?
arch/riscv/kernel/ptrace.c:165:6: warning: symbol 'do_syscall_trace_exit' was
not declared. Should it be static?
Fix by adding the missing prototypes to the
warning: symbol 'trap_init' was not declared.
Should it be static?
This change should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/kernel/entry.h | 29 +
arch/riscv/kernel/signal.c | 2 ++
arch/riscv/kernel/traps.c | 2 ++
?
This change should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/kernel/head.h| 21 +
arch/riscv/kernel/setup.c | 2 ++
arch/riscv/kernel/smpboot.c | 2 ++
arch/riscv/mm/fault.c | 2 ++
arch/riscv/mm/init.c| 2 ++
5 files cha
h to outweigh the value of the 80-column
warning from checkpatch. Fix by concatenating the strings.
This patch should have no functional impact.
Signed-off-by: Paul Walmsley
---
arch/riscv/mm/init.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/riscv/mm/init.
C model macros in the static analyzer command lines.
Signed-off-by: Paul Walmsley
---
arch/riscv/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index f5e914210245..0247a90bd4d8 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
dback from
Christoph Hellwig .
Applies on the current riscv fixes branch that is based on v5.4-rc3.
- Paul
Paul Walmsley (8):
riscv: add prototypes for assembly language functions from entry.S
riscv: add prototypes for assembly language functions from head.S
riscv: init: merge split string l
by: Greentime Hu
Reviewed-by: Anup Patel
[paul.walms...@sifive.com: fixed patch description]
Signed-off-by: Paul Walmsley
---
arch/riscv/include/asm/pgtable.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/incl
On Tue, 3 Sep 2019, Christoph Hellwig wrote:
> Many of the privileged CSRs exist in a supervisor and machine version
> that are used very similarly. Provide a new X-naming layer so that
> we don't have to ifdef everywhere for M-mode Linux support.
>
> Contains contributions from Damien Le Moal .
he entry code over to use CONFIG_PREEMPTION.
>
> Cc: Paul Walmsley
> Cc: Palmer Dabbelt
> Cc: Albert Ou
> Cc: linux-ri...@lists.infradead.org
> Signed-off-by: Thomas Gleixner
> Signed-off-by: Sebastian Andrzej Siewior
Acked-by: Paul Walmsley # for arch/riscv
- Paul
Shuah,
Could you please take a quick look at this and ack it if you're OK with
the tools/testing change? We'd like to get this merged soon.
- Paul
On Fri, 4 Oct 2019, Paul Walmsley wrote:
> Hello Shuah,
>
> On Thu, 22 Aug 2019, David Abdurachmanov wrote:
>
> >
TLB" to better align with the language in
section 4.2.1 "Supervisor Memory-Management Fence Instruction" of the
RISC-V Privileged Specification v20190608.
Fixes: c901e45a999a1 ("RISC-V: `sfence.vma` orderes the instruction cache")
Reported-by: Alan Kao
Cc: Palmer Dabbelt
Linus,
The following changes since commit da0c9ea146cbe92b832f1b0f694840ea8eb33cce:
Linux 5.4-rc2 (2019-10-06 14:27:30 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv/for-v5.4-rc3
for you to fetch changes up to cd9e72
On Thu, 10 Oct 2019, Rob Herring wrote:
> On Wed, Oct 9, 2019 at 7:08 PM Paul Walmsley wrote:
> >
> > On Wed, 9 Oct 2019, Rob Herring wrote:
> >
> > > Fix the errors in the RiscV CPU DT schema:
> > >
> > > Documentation/devicetree/bindings/ris
ithub.com/riscv/riscv-isa-manual/releases/download/draft-20190608-f467e5d/riscv-spec.pdf
So the right thing is to require 'timebase-frequency' at /cpus, and forbid
it in the individual CPU nodes.
>
> Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema&qu
On Mon, 7 Oct 2019, Christoph Hellwig wrote:
> On Mon, Oct 07, 2019 at 09:08:23AM -0700, Paul Walmsley wrote:
> > force_sig_fault(SIGTRAP, TRAP_BRKPT,
> > (void __user *)(regs->sepc));
>
> No nee for the extra braces, which also
necessary, since the
kernel will use the stdout-path as the default.
Signed-off-by: Paul Walmsley
---
Tested on a HiFive Unleashed using BBL.
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b
Hi Geert,
On Wed, 9 Oct 2019, Geert Uytterhoeven wrote:
> On Wed, Oct 9, 2019 at 12:06 PM Andreas Schwab wrote:
> > On Okt 09 2019, Geert Uytterhoeven wrote:
> > > I believe risc-v is DT-only, so if chosen/stdout-path is set up
> >
> > If. Currently, it isn't.
>
> IC. So isn't it better to fi
On Mon, 23 Sep 2019, Valentin Schneider wrote:
> Since the enabling and disabling of IRQs within preempt_schedule_irq()
> is contained in a need_resched() loop, we don't need the outer arch
> code loop.
>
> Reviewed-by: Palmer Dabbelt
> Signed-off-by: Valentin Schneider
> Cc: Albert Ou
> Cc: l
tions/macros.
>
> For riscv a page is a leaf page when it has a read, write or execute bit
> set on it.
>
> CC: Palmer Dabbelt
> CC: Albert Ou
> CC: linux-ri...@lists.infradead.org
> Signed-off-by: Steven Price
Acked-by: Paul Walmsley # for arch/riscv
Alex has a goo
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0:
> > > compatible: ['riscv'] is too short
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0:
> > > 'timebase-frequency' is a required property
&g
On Tue, 8 Oct 2019, Vincent Chen wrote:
> Sorry, I missed the comment. Christoph's suggestion is also good to me.
> I will modify it as you suggested.
Thanks - no need to resend, I'll queue the modified patch up here.
- Paul
On Mon, 7 Oct 2019, Christoph Hellwig wrote:
> On Mon, Oct 07, 2019 at 09:08:23AM -0700, Paul Walmsley wrote:
> > force_sig_fault(SIGTRAP, TRAP_BRKPT,
> > (void __user *)(regs->sepc));
>
> No nee for the extra braces, which also
Vincent,
On Fri, 27 Sep 2019, Christoph Hellwig wrote:
> On Mon, Sep 23, 2019 at 08:45:17AM +0800, Vincent Chen wrote:
> > To make the code more straightforward, replacing the switch statement
> > with if statement.
> >
> > Suggested-by: Paul Walmsley
> > Signe
On Fri, 27 Sep 2019, Kees Cook wrote:
> On Wed, Aug 28, 2019 at 6:30 PM Paul Walmsley
> wrote:
> > On Mon, 26 Aug 2019, Kees Cook wrote:
> >
> > > On Mon, Aug 26, 2019 at 09:39:50AM -0700, David Abdurachmanov wrote:
> > > > I don't have the a build
Hello Shuah,
On Thu, 22 Aug 2019, David Abdurachmanov wrote:
> This patch was extensively tested on Fedora/RISCV (applied by default on
> top of 5.2-rc7 kernel for <2 months). The patch was also tested with 5.3-rc
> on QEMU and SiFive Unleashed board.
>
> libseccomp (userspace) was rebased:
> ht
TYPE_NONE ebreak exception issued in kernel space to die()
and will send a SIGTRAP to the trapped process only when the ebreak is
in userspace.
Signed-off-by: Vincent Chen
Reviewed-by: Christoph Hellwig
[paul.walms...@sifive.com: fixed checkpatch issue]
Signed-off-by: Paul Walmsley
---
arch/ris
On Mon, 23 Sep 2019, Vincent Chen wrote:
> On RISC-V, when the kernel runs code on behalf of a user thread, and the
> kernel executes a WARN() or WARN_ON(), the user thread will be sent
> a bogus SIGTRAP. Fix the RISC-V kernel code to not send a SIGTRAP when
> a WARN()/WARN_ON() is executed.
>
>
On Mon, 23 Sep 2019, Vincent Chen wrote:
> When the CONFIG_GENERIC_BUG is disabled by disabling CONFIG_BUG, if a
> kernel thread is trapped by BUG(), the whole system will be in the
> loop that infinitely handles the ebreak exception instead of entering the
> die function. To fix this problem, the
Commit 858805b336be1cabb3d9033adaa3676574d12e37 ("kbuild: add $(BASH) to
run scripts with bash-extension") breaks my kernel test flow that targets
the HiFive Unleashed board. The boot traps during BBL early boot and
stops. QEMU is unaffected. Reverting 858805b336be fixes the issue.
I haven
Linus,
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c:
Linux 5.4-rc1 (2019-09-30 10:35:40 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv/for-v5.4-rc2
for you to fetch changes up to 922b03
On Tue, 24 Sep 2019, Palmer Dabbelt wrote:
> This is almost entirely a comment. The bug is unlikely to manifest on
> existing hardware because there is a timeout on load reservations, but
> manifests on QEMU because there is no timeout.
>
> Signed-off-by: Palmer Dabbelt
Thanks, queued for v5.4
On Fri, 27 Sep 2019, Albert Ou wrote:
> This fixes an error with how the FDT blob is reserved in memblock.
> An incorrect physical address calculation exposed the FDT header to
> unintended corruption, which typically manifested with of_fdt_raw_init()
> faulting during late boot after fdt_totalsiz
Linus,
The following changes since commit b41dae061bbd722b9d7fa828f35d22035b218e18:
Merge tag 'xfs-5.4-merge-7' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux
(2019-09-18 18:32:43 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
Hi Christoph,
On Thu, 19 Sep 2019, Christoph Hellwig wrote:
> On Thu, Sep 19, 2019 at 01:26:38AM -0700, Paul Walmsley wrote:
> >
> > Resolve most of the warnings emitted by sparse. The objective here is
> > to keep arch/riscv as clean as possible with regards to sparse
Hi Anup,
Thanks for changing this to use a bitmap. A few comments below -
On Wed, 4 Sep 2019, Anup Patel wrote:
> This patch adds riscv_isa bitmap which represents Host ISA features
> common across all Host CPUs. The riscv_isa is not same as elf_hwcap
> because elf_hwcap will only have ISA feat
On Mon, 16 Sep 2019, Vincent Chen wrote:
> When the handle_exception function addresses an exception, the interrupts
> will be unconditionally enabled after finishing the context save. However,
> It may erroneously enable the interrupts if the interrupts are disabled
> before entering the handle_e
On Thu, 5 Sep 2019, Bin Meng wrote:
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> Signed-off-by: Bin Meng
Thanks, queued for v5.4-rc with Christoph's Reviewed-by:.
- Paul
On Thu, 5 Sep 2019, Bin Meng wrote:
> U-Boot expects this alias to be in place in order to fix up the mac
> address of the ethernet node.
>
> Signed-off-by: Bin Meng
Thanks, queued for v5.4-rc with Christoph's Reviewed-by.
- Paul
ed by kvm module. Without this, kvm cannot
be compiled as a module.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
[paul.walms...@sifive.com: updated to apply; clarified short patch
description]
Signed-of
On Wed, 4 Sep 2019, Anup Patel wrote:
> We will be using ONE_REG interface accessing VCPU registers from
> user-space hence we add KVM_REG_RISCV for RISC-V VCPU registers.
>
> Signed-off-by: Anup Patel
> Acked-by: Paolo Bonzini
> Reviewed-by: Paolo Bonzini
> Reviewed-by: Alexander Graf
Thank
On Thu, 19 Sep 2019, Anup Patel wrote:
> > From: Xiang Wang
> > Date: Fri, 6 Sep 2019 11:56:09 +0800
> > Subject: [PATCH] arch/riscv: disable excess harts before picking main boot
> > hart
> >
> > Harts with id greater than or equal to CONFIG_NR_CPUS need to be
> > disabled. But the kernel can
US need to be
disabled. But the kernel can pick any hart as the main hart. So,
before picking the main hart, the kernel must disable harts with ids
greater than or equal to CONFIG_NR_CPUS.
Signed-off-by: Xiang Wang
Reviewed-by: Palmer Dabbelt
[paul.walms...@sifive.com: updated to apply; cleaned
Resolve most of the warnings emitted by sparse. The objective here is
to keep arch/riscv as clean as possible with regards to sparse warnings,
and to maintain this bar for subsequent patches.
Signed-off-by: Paul Walmsley
---
arch/riscv/include/asm/entry.h | 29
On Wed, 4 Sep 2019, Anup Patel wrote:
> This patch enables more VIRTIO drivers (such as console, rpmsg, 9p,
> rng, etc.) which are usable on KVM RISC-V Guest and Xvisor RISC-V
> Guest.
>
> Signed-off-by: Anup Patel
> Acked-by: Paolo Bonzini
> Reviewed-by: Paolo Bonzini
> Reviewed-by: Alexander
ean ‘VMEMMAP_START’?
#define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE)
^
Fixes: d95f1a542c3d ("RISC-V: Implement sparsemem")
Signed-off-by: Greentime Hu
[paul.walms...@sifive.com: fix patch description]
Signed-off-by: Paul Walmsley
---
arch/riscv/includ
igned-off-by: Yash Shah
Cc: Palmer Dabbelt
[paul.walms...@sifive.com: added chip-specific compatible string;
dropped reg-names string from pwm1]
Signed-off-by: Paul Walmsley
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 18 ++
.../boot/dts/sifive/hifive-unleashed-a00.dts
I just recalled that YueHaibing already posted a patch to do this:
https://lore.kernel.org/linux-riscv/alpine.deb.2.21..1909041520130.13...@viisi.sifive.com/
- Paul
Aurobindo,
On Tue, 17 Sep 2019, Aurabindo Jayamohanan wrote:
> ‐‐‐ Original Message ‐‐‐
> On Tuesday, September 17, 2019 5:45 PM, Paul Walmsley
> wrote:
>
> > On Tue, 17 Sep 2019, Baolin Wang wrote:
> >
> > > On Tue, 17 Sep 2019 at 17:12, Aurabi
Just tested this on the SiFive HiFive Unleashed. Seems to work OK;
however I did not stress-test it.
Tested-by: Paul Walmsley # HiFive Unleashed
- Paul
# !cat
cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
1: 0 0 0 0
On Tue, 17 Sep 2019, Baolin Wang wrote:
> On Tue, 17 Sep 2019 at 17:12, Aurabindo Jayamohanan wrote:
> >
> > platform_get_resource() may return NULL. If it is so, return -ENXIO
> >
> > Signed-off-by: Aurabindo Jayamohanan
> > ---
> > drivers/spi/spi-sifive.c | 6 ++
> > 1 file changed, 6 in
On Tue, 17 Sep 2019, Aurabindo Jayamohanan wrote:
> platform_get_resource() may return NULL. If it is so, return -ENXIO
>
> Signed-off-by: Aurabindo Jayamohanan
Reviewed-by: Paul Walmsley
- Paul
semem
Mao Han (3):
riscv: Add perf callchain support
riscv: Add support for perf registers sampling
riscv: Add support for libdw
Masahiro Yamada (1):
riscv: add arch/riscv/Kbuild
Paul Walmsley (1):
Merge tag 'common/for-v5.4-rc1/cpu-topology' into for-v5.4-rc1
On Mon, 16 Sep 2019, Andreas Schwab wrote:
> On Sep 16 2019, Paul Walmsley wrote:
>
> > On Tue, 10 Sep 2019, Andreas Schwab wrote:
> >
> >> On Sep 10 2019, Christoph Hellwig wrote:
> >>
> >> > On Tue, Sep 10, 2019 at 08:57:37AM +0200, Andreas
On Tue, 10 Sep 2019, Andreas Schwab wrote:
> On Sep 10 2019, Christoph Hellwig wrote:
>
> > On Tue, Sep 10, 2019 at 08:57:37AM +0200, Andreas Schwab wrote:
> >> On Sep 10 2019, Christoph Hellwig wrote:
> >>
> >> > The sifive serial driver implements earlycon support,
> >>
> >> It should proba
On Tue, 10 Sep 2019, Christoph Hellwig wrote:
> The sifive serial driver implements earlycon support, but unless
> another driver is built in that supports earlycon support it won't
> be usable. Explicitly select SERIAL_EARLYCON instead.
>
> Signed-off-by: Christoph Hellwig
On Sat, 14 Sep 2019, Atish Patra wrote:
> Thanks for the quick fix. Is there a planned timeline when we can
> remove the deprecated magic ?
If Linus merges this patch, we should probably start the transition in the
bootloaders, QEMU, and user tools as quickly as possible. Probably the
key elem
erface.
It primarily involves ensuring that the RISC-V image header has
something useful in the same field as the ARM64 image header.
----
Paul Walmsley (1):
riscv: modify the Image header to improve compatibility with the ARM
tives in head.S to ensure that reserved fields are
properly zero-initialized.
Signed-off-by: Paul Walmsley
Reported-by: Palmer Dabbelt
Cc: Atish Patra
Cc: Karsten Merker
---
Will try to get this merged before v5.3, to minimize the delta with the
ARM64 header in the final release.
Documen
One other comment on this patch:
On Fri, 6 Sep 2019, Paul Walmsley wrote:
> On Sun, 18 Aug 2019, Christoph Hellwig wrote:
>
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> > index 200c04ce5b0e..9241b3e7a050 100644
> > --- a/drivers/edac/Kconfig
> &
On Mon, 19 Aug 2019, Christoph Hellwig wrote:
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > memory management. It is a little s
On Sun, 18 Aug 2019, Christoph Hellwig wrote:
> The sifive_l2_cache.c is in no way related to RISC-V architecture
> memory management. It is a little stub driver working around the fact
> that the EDAC maintainers prefer their drivers to be structured in a
> certain way that doesn't fit the SiFiv
On Thu, 5 Sep 2019, Mao Han wrote:
> This patch adds support for DWARF register mappings and libdw registers
> initialization, which is used by perf callchain analyzing when
> --call-graph=dwarf is given.
>
> Signed-off-by: Mao Han
> Cc: Paul Walmsley
> Cc: Greentime Hu
dump support.
>
> Signed-off-by: Mao Han
> Cc: Paul Walmsley
> Cc: Greentime Hu
> Cc: Palmer Dabbelt
> Cc: linux-riscv
> Cc: Christoph Hellwig
> Cc: Guo Ren
Thanks, queued for v5.4-rc1 with Greentime's Tested-by: (since the changes
from v6 to v7 had no functional impact).
- Paul
On Wed, 4 Sep 2019, YueHaibing wrote:
> Use devm_platform_ioremap_resource() to simplify the code a bit.
> This is detected by coccinelle.
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
Acked-by: Paul Walmsley
- Paul
Hello Mao Han,
On Thu, 29 Aug 2019, Mao Han wrote:
> This patch add support for DWARF register mappings and libdw registers
> initialization, which is used by perf callchain analyzing when
> --call-graph=dwarf is given.
> diff --git a/tools/arch/riscv/include/uapi/asm/perf_regs.h
> b/tools/arch
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