On 4/12/21 2:00 AM, Stephen Rothwell wrote:
> Hi all,
>
Hi!
> In commit
>
> 2cfebcb2a22f ("pinctrl: at91-pio4: Fix slew rate disablement")
>
> Fixes tag
>
> Fixes: 440b144978ba ("pinctrl: at91-pio4: add support for slew-rate")
>
> has these problem(s):
>
> - Target SHA1 does not exist
Michael,
Would you please resend this patch, together with the mtd-utils
and the SPI NOR patch in a single patch set? You'll help us all
having all in a single place.
For the new ioctl we'll need acks from all the mtd maintainers
and at least a tested-by tag.
Cheers,
ta
On 4/6/21 11:50 AM, YueHaibing wrote:
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> 765c37d87669 ("dmaengine: at_xdmac: rework slave configuration part")
> left behind this, so can remove it.
Checkpatch complains:
ERROR: Please use git commit
On 4/6/21 9:37 AM, Wan Jiabing wrote:
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> struct ubi_wl_entry is defined at 178th line.
> The declaration here is unnecessary. Remove it.
>
> Signed-off-by: Wan Jiabing
the subject of the patch shoul
On 4/5/21 6:07 PM, Michael Walle wrote:
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> Hi,
>
> Am 2021-04-05 15:11, schrieb tudor.amba...@microchip.com:
>> On 3/18/21 11:24 AM, Michael Walle wrote:
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Hi,
On 3/18/21 11:24 AM, Michael Walle wrote:
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> Due to possible mode switching to 8D-8D-8D, it might not be possible to
> read the SFDP after the initial probe. To be able to dump the SFDP via
> sysf
On 3/18/21 2:44 PM, Lee Jones wrote:
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> Fixes the following W=1 kernel build warning(s):
>
> drivers/crypto/atmel-ecc.c:41: warning: cannot understand function
> prototype: 'struct atmel_ecdh_ctx '
On 3/20/21 10:15 AM, Meng Yu wrote:
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> Fix kernel-doc warnings due to missing "struct" keyword.
>
> The warning likes:
> drivers/crypto/atmel-ecc.c:40: warning: cannot understand function prototype:
On 3/17/21 10:21 AM, Michael Walle wrote:
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> Am 2021-03-17 07:09, schrieb tudor.amba...@microchip.com:
>> On 3/15/21 8:23 AM, Vignesh Raghavendra wrote:
>>> EXTERNAL EMAIL: Do not click links or open a
On 3/15/21 8:23 AM, Vignesh Raghavendra wrote:
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> On 3/9/21 12:58 PM, tudor.amba...@microchip.com wrote:
>> On 3/8/21 7:28 PM, Vignesh Raghavendra wrote:
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On 3/15/21 8:53 AM, Joe Perches wrote:
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> On Mon, 2021-03-08 at 11:58 +0530, Pratyush Yadav wrote:
>> On 06/03/21 11:50AM, Tudor Ambarus wrote:
>>> else is not generally useful after a break or return.
On 3/15/21 11:39 AM, Tudor Ambarus - M18064 wrote:
> On 3/15/21 11:23 AM, Michael Walle wrote:
>
> cut
>
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
new file mode 100644
index ..4e301fd5156b
--- /dev/null
+++ b/drivers/mtd/spi-nor/otp.c
On 3/15/21 11:23 AM, Michael Walle wrote:
cut
>>> diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
>>> new file mode 100644
>>> index ..4e301fd5156b
>>> --- /dev/null
>>> +++ b/drivers/mtd/spi-nor/otp.c
>>> @@ -0,0 +1,218 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>
On 3/15/21 11:26 AM, Michael Walle wrote:
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> Am 2021-03-15 09:26, schrieb tudor.amba...@microchip.com:
>> On 3/6/21 2:05 AM, Michael Walle wrote:
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On 3/6/21 2:05 AM, Michael Walle wrote:
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> Winbond flashes with OTP support provide a command to erase the OTP
> data. This might come in handy during development.
>
> This was tested with a Winbond W
On 3/6/21 2:05 AM, Michael Walle wrote:
> + nor->dirmap.rdesc = NULL;
why can't we use dirmap?
> +
> + ret = spi_nor_read_data(nor, addr, len, buf);
On 3/6/21 2:05 AM, Michael Walle wrote:
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> With all the helper functions in place, add OTP support for the Winbond
> W25Q32JW and W25Q32FW.
>
> Both were tested on a LS1028A SoC with a NXP FSPI contro
On 3/6/21 2:05 AM, Michael Walle wrote:
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> Use the new OTP ops to implement OTP access on Winbond flashes. Most
> Winbond flashes provides up to four different OTP regions ("Security
> Registers").
>
Michael,
Just cosmetic suggestions this time.
On 3/6/21 2:05 AM, Michael Walle wrote:
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> SPI flashes sometimes have a special OTP area, which can (and is) used to
> store immutable properties like bo
On 3/6/21 1:19 PM, Michael Walle wrote:
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> Am 2021-03-06 10:50, schrieb Tudor Ambarus:
>> It makes the core file a bit smaller and provides better separation
>> between the Software Write Protection fe
On 3/12/21 3:32 PM, Michael Walle wrote:
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> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
>> The main problem here is telling the controller where to find the
>> pattern and how to read it. This RFC use
On 3/12/21 12:10 PM, Pratyush Yadav wrote:
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> On 12/03/21 09:09AM, tudor.amba...@microchip.com wrote:
>> On 3/11/21 9:12 PM, Pratyush Yadav wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachm
On 3/11/21 9:12 PM, Pratyush Yadav wrote:
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> Check if a read is eligible for PHY and if it is, enable PHY and DQS.
DQS as in data strobe? Shouldn't the upper layer inform the QSPI controller
whether D
On 3/11/21 9:12 PM, Pratyush Yadav wrote:
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> Hi,
>
> This series adds support for OSPI PHY calibration on the Cadence OSPI
> controller. This calibration procedure is needed to allow high clock
> spee
On 3/10/21 5:20 PM, nicolas.fe...@microchip.com wrote:
> From: Nicolas Ferre
>
> Fix the whole mux-mask table according to datasheet for the sam9x60
> product. Too much functions for pins were disabled leading to
> misunderstandings when enabling more peripherals or taking this table
> as an exa
On 3/10/21 12:59 AM, Michael Walle wrote:
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> Hi Tim,
>
> Am 2021-03-09 23:00, schrieb Tim Harvey:
>> Document the compatible value for the Fujitsu MB85RS4MT SPI
>> FRAM EEPROM device so that it can be
On 3/8/21 7:28 PM, Vignesh Raghavendra wrote:
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> On 3/6/21 3:20 PM, Tudor Ambarus wrote:
>> It makes the core file a bit smaller and provides better separation
>> between the Software Write Protection
On 2/9/21 1:11 PM, Md Sadre Alam wrote:
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> Add support for gd25lb256e. This device tested on IPQ5018
> platform with dd from/to the flash for read/write respectly,
typo: respectly
> and mtd erase for
On 2/19/21 9:50 AM, Mathieu Dubois-Briand wrote:
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> Hi,
>
> I just came across this commit (9166f4af32db) in spi-nor/for-5.12:
> https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git/commit/?h
Hi, Michael,
On 2/16/21 6:28 PM, Michael Walle wrote:
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> SPI flashes sometimes have a special OTP area, which can (and is) used to
> store immutable properties like board serial number or vendor assig
On 2/24/21 3:29 AM, yumeng wrote:
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> 在 2021/2/23 18:44, tudor.amba...@microchip.com 写道:
>> Hi,
>>
>> On 2/23/21 9:10 AM, Meng Yu wrote:
>>> --- a/drivers/crypto/atmel-ecc.c
>>> +++ b/drivers/crypto/atm
Hi,
On 2/23/21 9:10 AM, Meng Yu wrote:
> --- a/drivers/crypto/atmel-ecc.c
> +++ b/drivers/crypto/atmel-ecc.c
> @@ -104,7 +104,7 @@ static int atmel_ecdh_set_secret(struct crypto_kpp *tfm,
> const void *buf,
> return -EINVAL;
> }
>
> - ctx->n_sz = atmel_ecdh_supporte
Hi,
On 2/16/21 5:10 PM, mda...@codeaurora.org wrote:
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> On 2021-02-09 16:41, Md Sadre Alam wrote:
>> Add support for gd25lb256e. This device tested on IPQ5018
>> platform with dd from/to the flash for
On 2/10/21 10:54 AM, Saravana Kannan wrote:
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> On Wed, Feb 10, 2021 at 12:19 AM wrote:
>>
>> Hi, Saravana,
>>
>> On 2/6/21 12:26 AM, Saravana Kannan wrote:
>>> There are a lot of devices/drivers where
Hi, Saravana,
On 2/6/21 12:26 AM, Saravana Kannan wrote:
> There are a lot of devices/drivers where they never have a struct device
> created for them or the driver initializes the hardware without ever
> binding to the struct device.
>
> This series is intended to avoid any boot regressions due
Hi, Saravana,
On 2/9/21 9:06 PM, Saravana Kannan wrote:
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> On Tue, Feb 9, 2021 at 7:21 AM wrote:
>>
>> Hi, Saravana,
>>
>> On 2/9/21 11:11 AM, Saravana Kannan wrote:
>>> EXTERNAL EMAIL: Do not click
Hi, Saravana,
On 2/9/21 11:11 AM, Saravana Kannan wrote:
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> On Mon, Feb 8, 2021 at 11:55 PM Stephen Boyd wrote:
>>
>> Quoting Saravana Kannan (2021-01-28 09:01:41)
>>> On Thu, Jan 28, 2021 at 2:45 AM
Hi, Stephen,
On 2/9/21 9:55 AM, Stephen Boyd wrote:
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> Quoting Saravana Kannan (2021-01-28 09:01:41)
>> On Thu, Jan 28, 2021 at 2:45 AM Tudor Ambarus
>> wrote:
>>>
>>> The sama5d2 requires the clock
On 2/8/21 1:41 PM, Pratyush Yadav wrote:
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> On 05/02/21 03:52PM, Tudor Ambarus wrote:
>> Wait for the erase cmd to complete and then advance the erase.
>>
>> Signed-off-by: Tudor Ambarus
>> ---
>> dr
On 2/8/21 1:41 PM, Pratyush Yadav wrote:
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> On 05/02/21 03:52PM, Tudor Ambarus wrote:
>> Useful when debugging non-uniform erase.
>>
>> Signed-off-by: Tudor Ambarus
>> ---
>> drivers/mtd/spi-nor/core
Hi, George,
On 2/7/21 2:30 PM, George Brooke wrote:
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> Adds support for the Boya Microelectronics BY25Q128AS 128 Mbit flash.
> I tested this on the Creality WB-01 embedded device which uses this,
> al
Hi, Michael, Stephen,
Do you plan to take this patch for v5.12?
If fw_devlink will remain set to ON for v5.12, some of our boards will
no longer boot without this patch.
Cheers,
ta
On 2/3/21 5:43 PM, Tudor Ambarus wrote:
> These are all "early clocks" that require initialization just at
> of_clk
On 2/8/21 10:21 AM, nicolas.fe...@microchip.com wrote:
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> From: Nicolas Ferre
>
> Add Quad SPI driver to the sama5 defconfig. This driver is needed for
> sama5d2 SoC.
>
> Signed-off-by: Nicolas Ferr
On 2/5/21 11:54 AM, Claudiu Beznea wrote:
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> Enable drivers for sam9x60/sam9x60-ek:
> - shutdown controller
> - CAN
> - AT24 EEPROM (present on SAM9X60-EK)
> - MCP23S08 (present on SAM9X60-EK)
> - AES,
On 2/5/21 12:12 PM, tudor.amba...@microchip.com wrote:
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> On 2/5/21 11:54 AM, Claudiu Beznea wrote:
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>>
On 2/4/21 1:09 PM, Lee Jones wrote:
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> Fixes the following W=1 kernel build warning(s):
>
> drivers/crypto/atmel-ecc.c:41: warning: cannot understand function
> prototype: 'struct atmel_ecdh_ctx '
>
Hi, Saravana,
On 2/2/21 6:33 AM, Saravana Kannan wrote:
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> This patch series solves two general issues with fw_devlink=on
>
> Patch 1/3 and 3/3 addresses the issue of firmware nodes that look like
>
Hi, Saravana,
On 1/25/21 8:16 PM, Saravana Kannan wrote:
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> On Mon, Jan 25, 2021 at 9:05 AM wrote:
>>
>> Hi, Saravana,
>>
>> On 12/18/20 5:17 AM, Saravana Kannan wrote:
>>> Cyclic dependencies in som
Hi, Saravana,
On 12/18/20 5:17 AM, Saravana Kannan wrote:
> Cyclic dependencies in some firmware was one of the last remaining
> reasons fw_devlink=on couldn't be set by default. Now that cyclic
> dependencies don't block probing, set fw_devlink=on by default.
>
> Setting fw_devlink=on by default
Hi, Andreas,
On 12/21/20 12:43 AM, Andreas Rammhold wrote:
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> This adds support for the xt25f128b as found on the rockpi4b SBC.
>
> Signed-off-by: Andreas Rammhold
> ---
>
> This continues the effo
Hi, Sieng,
On 12/8/20 3:57 AM, Sieng Piaw Liew wrote:
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> Enable 4-bit Block Protect support for MX256405D and its variants using
> the same ID.
>
> Tested on Innacom W3400V6 router with MX25L6406E ch
On 1/20/21 7:00 AM, Pan Bian wrote:
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> The allocated master is not released. Goto error handling label rather
> than directly return.
>
> Fixes: 04242ca4e891 ("spi: atmel: Use SPI core DMA mapping fra
On 1/20/21 5:02 PM, Michael Walle wrote:
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> Am 2021-01-20 15:52, schrieb tudor.amba...@microchip.com:
>> On 1/20/21 4:05 PM, Michael Walle wrote:
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/m
On 1/20/21 6:47 PM, Michael Walle wrote:
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> Am 2021-01-20 17:25, schrieb tudor.amba...@microchip.com:
>> On 1/20/21 5:49 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachme
On 1/20/21 5:49 PM, Michael Walle wrote:
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> Am 2021-01-20 16:39, schrieb tudor.amba...@microchip.com:
>> On 1/20/21 5:02 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachme
On 1/20/21 4:05 PM, Michael Walle wrote:
>> diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
>> index 00e48da0744a..d6e1396abb96 100644
>> --- a/drivers/mtd/spi-nor/sst.c
>> +++ b/drivers/mtd/spi-nor/sst.c
>> @@ -8,6 +8,39 @@
>>
>> #include "core.h"
>>
>> +static int sst26vf_lock
On 1/20/21 2:29 PM, Pratyush Yadav wrote:
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> Hi Tudor,
Hi, Pratyush,
Thanks for reviewing this.
>
> On 20/01/21 12:54PM, Tudor Ambarus wrote:
>> The Global Block Unlock command has different names
On 1/20/21 2:29 PM, Pratyush Yadav wrote:
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> Hi Tudor,
>
> On 20/01/21 12:54PM, Tudor Ambarus wrote:
>> Even if sst26vf shares the SPINOR_OP_GBULK opcode with
>> Macronix (ex. MX25U12835F) and Winboun
On 1/4/21 1:02 PM, Greg KH wrote:
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> On Wed, Sep 23, 2020 at 08:19:18AM +, tudor.amba...@microchip.com wrote:
>> On 9/23/20 11:13 AM, tudor.amba...@microchip.com wrote:
>>> Hi, Pavel,
>>>
>>> On 9/
Hi, Shuhao,
On 11/11/20 3:45 AM, Shuhao Mai wrote:
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> Add support for w25q512jv. This is of the same series chip with
> w25q256jv, which is already supported, but with size doubled and
> different JED
On 12/15/20 11:46 PM, Bert Vermeulen wrote:
> This driver supports the spiflash core in all RTL838x/RTL839x SoCs,
> and likely some older models as well (RTL8196C).
>
Can we use SPIMEM and move this under drivers/spi/ instead?
Cheers,
ta
> Signed-off-by: Bert Vermeulen
> ---
> drivers/mtd/spi-
On 12/15/20 4:24 PM, Geert Uytterhoeven wrote:
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> Hi Mark, Tudor,
Hi, Geert,
>
> On Fri, Dec 11, 2020 at 8:02 PM Mark Brown wrote:
>> On Wed, 9 Dec 2020 19:35:14 +0200, Tudor Ambarus wrote:
>>> Mak
On 12/10/20 5:33 PM, Mark Brown wrote:
> On Thu, Dec 10, 2020 at 08:58:18AM +, tudor.amba...@microchip.com wrote:
>> On 12/9/20 10:30 PM, Serge Semin wrote:
>
>> Right, in general we aim to do this sort of fixup on the transfers
>> and messages rather than the devices, I guess we might
Hi, Serge, Mark,
On 12/9/20 10:30 PM, Serge Semin wrote:
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> On Wed, Dec 09, 2020 at 08:25:52PM +, Mark Brown wrote:
>> On Wed, Dec 09, 2020 at 11:15:35PM +0300, Serge Semin wrote:
>>> On Wed, Dec
Hi, Sieng,
On 12/7/20 4:46 AM, Sieng Piaw Liew wrote:
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>
> Enable 4-bit Block Protect support for MX256405D and its variants using
> the same ID.
>
> Tested on Innacom W3400V6 router with MX25L6406E ch
Hi, Lad,
On 10/16/20 2:55 PM, Lad Prabhakar wrote:
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>
> This chip is (nearly) identical to the Winbond w25m512jv which is
> already supported by Linux. Compared to the w25m512jv, the 'jw'
> has a differ
On 12/3/20 4:39 PM, Michael Walle wrote:
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> Am 2020-12-03 15:34, schrieb tudor.amba...@microchip.com:
>> On 12/3/20 1:00 AM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachme
On 12/3/20 1:00 AM, Michael Walle wrote:
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> Traditionally, linux unlocks the whole flash because there are legacy
> devices which has the write protections bits set by default at startup.
> If you actu
On 12/3/20 1:00 AM, Michael Walle wrote:
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>
> These flashes have some weird BP bits mapping which aren't supported in
> the current locking code. Just add a simple unlock op to unprotect the
> entire fla
On 12/3/20 1:00 AM, Michael Walle wrote:
> --- a/drivers/mtd/spi-nor/sst.c
> +++ b/drivers/mtd/spi-nor/sst.c
> @@ -18,7 +18,8 @@ static const struct flash_info sst_parts[] = {
> SECT_4K | SST_WRITE) },
> { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
>
On 12/3/20 1:00 AM, Michael Walle wrote:
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> Just try to unlock the whole SPI-NOR flash array. Don't abort the
> probing in case of an error. Justifications:
> (1) For some boards, this just works beca
On 12/3/20 1:00 AM, Michael Walle wrote:
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> This flash part actually has 4 block protection bits.
>
> Reported-by: Tudor Ambarus
> Cc: sta...@vger.kernel.org # v5.7+
While the patch is correct accor
On 12/2/20 1:25 PM, Michael Walle wrote:
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> Am 2020-12-02 12:10, schrieb tudor.amba...@microchip.com:
>> On 11/30/20 4:38 PM, Michael Walle wrote:
> [..]
> + * indicated by SNOR_F_WP_IS_VOLA
On 11/30/20 5:24 PM, Jonathan Neuschäfer wrote:
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> There are a few typos in comments in the SPI NOR framework; fix them.
>
> Signed-off-by: Jonathan Neuschäfer
> ---
> drivers/mtd/spi-nor/core.c |
On 11/30/20 4:38 PM, Michael Walle wrote:
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>
> Am 2020-11-28 11:17, schrieb tudor.amba...@microchip.com:
>> On 11/26/20 10:26 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attac
On 11/30/20 4:16 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Am 2020-11-28 09:25, schrieb tudor.amba...@microchip.com:
>> On 11/26/20 10:26 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attac
On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Some flashes like the Cypress S28 family use ECC. Under this ECC scheme,
> multi-pass writes to an ECC block is not allowed. In other words, once
> data is
On 11/18/20 8:24 PM, Pratyush Yadav wrote:
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> content is safe
>
> For NOR flashes EC and VID are zeroed out before an erase is issued to
> make sure UBI does not mistakenly treat the PEB as used and associate it
> with an
On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The S28 flash family uses 2-bit ECC by default with each ECC block being
> 16 bytes. Under this scheme multi-pass programming to an ECC block is
> not allo
On 11/26/20 10:26 PM, Michael Walle wrote:
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> content is safe
>
> Traditionally, linux unlocks the whole flash because there are legacy
> devices which has the write protections bits set by default at startup.
> If you ac
On 11/26/20 10:26 PM, Michael Walle wrote:
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>
> These flashes have some weird BP bits mapping which aren't supported in
> the current locking code. Just add a simple unlock op to unprotect the
> entire f
On 11/26/20 10:26 PM, Michael Walle wrote:
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> For the Atmel and SST parts this flag was already moved to individual
> flash parts because it is considered bad esp. because newer flash chips
> will auto
On 11/25/20 8:17 PM, Michael Walle wrote:
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> Am 2020-11-24 20:09, schrieb tudor.amba...@microchip.com:
>> On 10/3/20 6:32 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachm
On 11/25/20 8:52 PM, Michael Walle wrote:
>> Looks like BP3 is needed here.
>
> https://ww1.microchip.com/downloads/en/DeviceDoc/20005036C.pdf
>
> agreed. But again cannot test it. Would add it as a seperate patch
> to this series. (or leave it like it is)
Separate patch for the TB/BP3 bits is f
On 11/26/20 2:45 PM, Tudor Ambarus - M18064 wrote:
> On 11/25/20 8:17 PM, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> Am 2020-11-24 20:09, schrieb tudor.amba...@microchip.com:
>>> On 10/3/20 6:32 PM, Michael Walle wrot
On 11/25/20 8:17 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Am 2020-11-24 20:09, schrieb tudor.amba...@microchip.com:
>> On 10/3/20 6:32 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachm
On 10/3/20 6:32 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Traditionally, linux unlocks the whole flash because there are legacy
> devices which has the write protections bits set by default at startup.
> If you actu
On 10/3/20 6:32 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> This is considered bad for the following reasons:
> (1) We only support the block protection with BPn bits for write
> protection. Not all SST parts su
On 10/3/20 6:32 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> This is considered bad for the following reasons:
> (1) We only support the block protection with BPn bits for write
> protection. Not all Atmel parts
On 11/7/20 9:58 AM, Vignesh Raghavendra wrote:
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>
> Hi,
>
> [...]
>
> On 10/5/20 9:01 PM, Pratyush Yadav wrote:
>> +static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool
>> enable)
>>
On 11/4/20 7:45 PM, Claudiu Beznea wrote:
> pmc_data_allocate() has been changed. pmc_data_free() was removed.
> Adapt the code taking this into consideration. With this the programmable
> clocks were also saved in sama7g5_pmc so that they could be later
> referenced.
>
> Fixes: cb783bbbcf54 ("clk
Hi, Mason, YC Lin,
On 5/29/20 10:36 AM, Mason Yang wrote:
> A set of simple command sequences is provided which can be executed
> directly by the host controller to enable octal DTR mode.
>
> Each command sequence is 8 per byte for single SPI mode.
>
> Signed-off-by: Mason Yang
> ---
> drivers
Hi, Pratyush,
On 10/5/20 6:31 PM, Pratyush Yadav wrote:
> Tested on Micron MT35X and S28HS flashes for Octal DTR.
Do these flashes define the "Command Sequences to Change to
Octal DDR (8D-8D-8D) mode" table? Can't we use that table
instead of defining our own octal dtr enable functions?
I see t
Hi, Mason, YC Lin,
On 5/29/20 10:36 AM, Mason Yang wrote:
> Macronix mx25uw51245g is a SPI NOR that supports 1-1-1/8-8-8 mode.
>
> Correct the dummy cycles to device for various frequencies
> after xSPI profile 1.0 table parsed.
>
> Enable mx25uw51245g to Octal DTR mode by executing the command
On 10/28/20 2:49 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Tudor,
>
> On 28/10/20 07:53AM, tudor.amba...@microchip.com wrote:
>> Hi, Pratyush,
>>
>> On 10/5/20 6:31 PM, Pratyush Yadav wrote:
>>> Tested on Micro
Hi, Mason, YC Lin,
On 5/29/20 10:36 AM, Mason Yang wrote:
> Configuration register 2 is to set the device operation condition like
> STR or DTR mode at address offset 0 and DQS mode at address offset 0x200.
>
> Each device has various address offset for it's specific operatoin
> setting.
>
> Sig
Hi, Mason, YC Lin,
We'll have to figure out how we can best use the "Command Sequences
to Change to Octal DDR" table.
Would be great if you continue to work on this. One has to
rebase this series on top of v5.10-rc1 with Pratyush's series [1]
applied in advance. Please let me know about your plan
Hi, Mason, YC Lin,
On 5/29/20 10:36 AM, Mason Yang wrote:
> JESD251, xSPI profile 1.0 table supports octal DTR mode.
> Extract information like the fast read opcode, dummy cycles for various
> frequencies, the number of dummy cycles needed for a Read Status
> Register command, the number of addres
Hi, Mason, YC Lin,
On 5/29/20 10:36 AM, Mason Yang wrote:
> Get maximum operation speed of device in octal mode from
> BFPT 20th DWORD.
>
I would like to understand how would we use the max speed value
at the SPI NOR level. The maximum operation speed is typically used
to determine the number of
On 10/5/20 6:31 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> This table is indication that the flash is xSPI compliant and hence
> supports octal DTR mode. Extract information like the fast read opcode,
> dummy cycles
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