[PATCH v1] clk: mediatek: mt8183: Register 13MHz clock earlier for clocksource

The 13MHz clock should be registered before clocksource driver is initialized. Use CLK_OF_DECLARE_DRIVER() to guarantee. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mt8183.c | 49 ++- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a

[PATCH v1] clk: mediatek: fix clk-gate flag setting

CLK_SET_RATE_PARENT would be dropped. Merge two flag setting together to correct the error. Fixes: 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate") Cc: Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-gate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

Re: [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data

On Thu, 2019-04-11 at 13:19 -0700, Stephen Boyd wrote: > Quoting Weiyi Lu (2019-03-04 21:05:43) > > On some Mediatek platforms, there are critical clocks of > > clock gate type. > > To register clock gate with flags CLK_IS_CRITICAL, > > we need to add the flags field in

Re: [PATCH v5 0/9] Mediatek MT8183 clock support

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: Hi Stephen, Just gentle ping. Many thanks. > Resend clock patches from v4 based on v5.0-rc1. > > The whole series now is composed of > a fix for PLL tuner (PATCH 1), > clock common changes for both MT8183 & MT6765 (PATCH 2-

[PATCH v5 06/14] soc: mediatek: Refactor clock control

Put clock enable and disable control in separate function. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 49 --- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c

[PATCH v5 05/14] soc: mediatek: Refactor regulator control

Put regulator enable and disable control in separate functions. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 32 ++- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk

[PATCH v5 02/14] dt-bindings: soc: Add MT8183 power dt-bindings

ntrol with clock name [a-z]+-[0-9]+, e.g. isp-0, cam-1. Signed-off-by: Weiyi Lu --- .../bindings/soc/mediatek/scpsys.txt | 14 ++ include/dt-bindings/power/mt8183-power.h | 26 +++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/power/mt

[PATCH v5 01/14] dt-bindings: mediatek: Add property to mt8183 smi-common

For scpsys driver using regmap based syscon driver API. Signed-off-by: Weiyi Lu --- .../bindings/memory-controllers/mediatek,smi-common.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt

[PATCH v5 10/14] soc: mediatek: Add multiple step bus protection control

Both MT8183 & MT6765 have more control steps of bus protection than previous project. And there add more bus protection registers reside at infracfg & smi-common. Also add new APIs for multiple step bus protection control with more customize arguments. Signed-off-by: Weiyi Lu --- dri

[PATCH v5 09/14] soc: mediatek: Add basic_clk_name to scp_power_data

Try to stop extending the clk_id or clk_names if there are more and more new BASIC clocks. To get its own clocks by the basic_clk_name of each power domain. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 27 +++ 1 file changed, 19 insertions(+), 8

[PATCH v5 07/14] soc: mediatek: Refactor sram control

Put sram enable and disable control in separate functions. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 79 --- 1 file changed, 51 insertions(+), 28 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c

[PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation

Use USEC_PER_SEC to indicate the polling timeout directly. And add documentation of scp_domain_data. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc

[PATCH v5 08/14] soc: mediatek: Refactor bus protection control

Put bus protection enable and disable control in separate functions. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 48 ++- 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk

[PATCH v5 14/14] arm64: dts: Add power controller device node of MT8183

Add power controller node and smi-common node for MT8183 In scpsys node, it contains clocks and regmapping of infracfg and smi-common for bus protection. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 1 file changed, 62 insertions(+) diff

[PATCH v5 00/14] Mediatek MT8183 scpsys support

property to mt8183 smi-common - seperate refactor patches and new add function - add power controller device node Weiyi Lu (14): dt-bindings: mediatek: Add property to mt8183 smi-common dt-bindings: soc: Add MT8183 power dt-bindings soc: mediatek: Switch to SPDX license identifier soc: mediatek

[PATCH v5 13/14] soc: mediatek: Add MT8183 scpsys support

Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 226 ++ 1 file changed, 226 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 94c10f69655d..f1d82cdb219e 100644 --- a

[PATCH v5 12/14] soc: mediatek: Add extra sram control

For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu --- drivers/soc/me

[PATCH v5 03/14] soc: mediatek: Switch to SPDX license identifier

Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 5b24bb4bfbf6..9f52f501178b 100644 --- a/drivers/soc/mediatek/mtk

[PATCH v5 11/14] soc: mediatek: Add subsys clock control for bus protection

Add subsys CG control flow before/after the bus protect control due to bus protection need SMI bus relative CGs enabled to feedback its ack. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 72 ++- 1 file changed, 70 insertions(+), 2 deletions(-) diff

[PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off

d because its enable bit is 0. Signed-off-by: James Liao Acked-by: Michael Turquette Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.

[PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data

or using the default control register CON1 if without setting in pll data. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mtk.h | 1 + drivers/clk/mediatek/clk-pll.c | 17 +++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b

[PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data

On some Mediatek platforms, there are critical clocks of clock gate type. To register clock gate with flags CLK_IS_CRITICAL, we need to add the flags field in mtk_gate data and register APIs. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-gate.c | 5 +++-- drivers/clk/mediatek/clk-gate.h

[PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate

: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) Cc: Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 48 -- 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk

[PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

Signed-off-by: Weiyi Lu Acked-by: Sean Wang --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 15 +++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e

[PATCH v5 5/9] clk: mediatek: Add dt-bindings for MT8183 clocks

Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt8183-clk.h | 422 + 1 file changed, 422 insertions(+) create mode 100644 include/dt

[PATCH v5 4/9] dt-bindings: ARM: Mediatek: Document bindings for MT8183

This patch adds the binding documentation for apmixedsys, audiosys, camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys, vencsys and ipu for Mediatek MT8183. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring Acked-by: Stephen Boyd --- .../arm/mediatek/mediatek,apmixedsys.txt

[PATCH v5 8/9] clk: mediatek: Add MT8183 clock support

Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Kconfig | 75 ++ drivers/clk/mediatek/Makefile | 12 + drivers/clk/mediatek/clk-gate.h| 14 + drivers/clk

[PATCH v5 2/9] clk: mediatek: Add new clkmux register API

lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Makefile | 3 +- drivers/clk/mediatek/clk-mux.c | 223 + drivers/clk/mediatek/clk-mux.h | 89

[PATCH v5 0/9] Mediatek MT8183 clock support

Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu (5): dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add dt-bindings for MT8183 clocks clk: mediatek: Add flags support for mtk_gate data clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek:

[PATCH v5 0/9] Mediatek MT8183 clock support

Resend clock patches from v4 based on v5.0-rc1. The whole series now is composed of a fix for PLL tuner (PATCH 1), clock common changes for both MT8183 & MT6765 (PATCH 2-3), clock support of MT8183 (PATCH 4-8) and resend a clock patch long time ago(PTACH 9). changes since v4: - refine for the fix

Re: [PATCH v4 01/12] clk: mediatek: Disable tuner_en before change PLL rate

On Wed, 2019-02-27 at 11:51 +0800, Weiyi Lu wrote: > On Tue, 2019-02-26 at 16:59 +0100, Matthias Brugger wrote: > > > > On 01/02/2019 09:30, Weiyi Lu wrote: > > > From: Owen Chen > > > > > > PLLs with tuner_en bit, such as APLL1, need to disable

Re: [PATCH v4 01/12] clk: mediatek: Disable tuner_en before change PLL rate

On Tue, 2019-02-26 at 16:59 +0100, Matthias Brugger wrote: > > On 01/02/2019 09:30, Weiyi Lu wrote: > > From: Owen Chen > > > > PLLs with tuner_en bit, such as APLL1, need to disable > > tuner_en before apply new frequency settings, or the new frequency > >

Re: [PATCH v4 08/12] clk: mediatek: Add MT8183 clock support

On Tue, 2019-02-26 at 09:50 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2019-02-01 00:30:12) > > diff --git a/drivers/clk/mediatek/clk-mt8183.c > > b/drivers/clk/mediatek/clk-mt8183.c > > new file mode 100644 > > index ..e9de9fe774ca > > --- /dev/nu

Re: [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support

On Thu, 2019-02-21 at 23:48 -0800, Stephen Boyd wrote: > Quoting Matthias Brugger (2019-02-21 00:36:24) > > > > > > On 20/02/2019 20:18, Stephen Boyd wrote: > > > > > > What's the merge plan here? Do you want me to apply these patches to clk > > > tree? Will someone be sending me a pull request

[PATCH v4 12/12] clk: mediatek: Allow changing PLL rate when it is off

d because its enable bit is 0. Signed-off-by: James Liao Acked-by: Michael Turquette Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index cf4440

[PATCH v4 02/12] clk: mediatek: add new clkmux register API

lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Makefile | 3 +- drivers/clk/mediatek/clk-mux.c | 223 + drivers/clk/mediatek/clk-mux.h | 89

[PATCH v4 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks

Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt8183-clk.h | 422 + 1 file changed, 422 insertions(+) create mode 100644 include/dt

[PATCH v4 07/12] clk: mediatek: Add flags support for mtk_gate data

On some Mediatek platforms, there are critical clocks of clock gate type. To register clock gate with flags CLK_IS_CRITICAL, we need to add the flags field in mtk_gate data and register APIs. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-gate.c | 5 +++-- drivers/clk/mediatek/clk-gate.h

[PATCH v4 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183

This patch adds the binding documentation for apmixedsys, audiosys, camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys, vencsys and ipu for Mediatek MT8183. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring Acked-by: Stephen Boyd --- .../arm/mediatek/mediatek,apmixedsys.txt

[PATCH v4 01/12] clk: mediatek: Disable tuner_en before change PLL rate

From: Owen Chen PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Another minor change

[PATCH v4 00/12] Mediatek MT8183 clock and scpsys support

Owen Chen (4): clk: mediatek: Disable tuner_en before change PLL rate clk: mediatek: add new clkmux register API clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data soc: mediatek: add new flow for mtcmos power. Weiyi Lu (7): dt-bindings: ARM: Mediatek: Document bindings for

[PATCH v4 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings

fix incorrect IC name that will affect the MT8183 power dt-bindings Signed-off-by: Weiyi Lu --- include/dt-bindings/power/mt8173-power.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h

[PATCH v4 11/12] soc: mediatek: Add MT8183 scpsys support

Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 226 ++ 1 file changed, 226 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 53a16fa327cf..09795caf4547 100644 --- a

[PATCH v4 10/12] dt-bindings: soc: Add MT8183 power dt-bindings

Add power dt-bindings for MT8183. Signed-off-by: Weiyi Lu --- .../bindings/soc/mediatek/scpsys.txt | 14 ++ include/dt-bindings/power/mt8183-power.h | 26 +++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/power/mt8183-power.h

[PATCH v4 08/12] clk: mediatek: Add MT8183 clock support

Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Kconfig | 75 ++ drivers/clk/mediatek/Makefile | 12 + drivers/clk/mediatek/clk-gate.h| 14 + drivers/clk

[PATCH v4 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data

Signed-off-by: Weiyi Lu Acked-by: Sean Wang --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 15 +++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e

[PATCH v4 00/12] Mediatek MT8183 clock and scpsys support

This series is based on v5.0-rc1 and most of changes are extracted from series below (clock/scpsys common changes for both MT8183 & MT6765) https://patchwork.kernel.org/patch/10528495/ (clock support of MT8183) https://patchwork.kernel.org/patch/10549891/ The whole series is composed of clock com

[PATCH v4 04/12] soc: mediatek: add new flow for mtcmos power.

d to do clock and internal isolation while power on/off sram. We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to do the extra sram isolation control or not. Signed-off-by: Owen Chen Signed-off-by: Mars Cheng Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/M

Re: [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support

On Tue, 2018-12-11 at 09:00 +0800, Nicolas Boichat wrote: > On Mon, Dec 10, 2018 at 3:32 PM Weiyi Lu wrote: > > > > Add MT8183 clock support, include topckgen, apmixedsys, > > infracfg, mcucfg and subsystem clocks. > > > > Signed-off-by: Weiyi Lu > >

Re: [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data

On Fri, 2018-12-14 at 14:02 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2018-12-09 23:32:31) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > > index f0ff5f535c7e..81400601f107 100644 > > --- a/drivers/clk/mediatek/clk-pll.c > > +++

Re: [PATCH v3 01/12] clk: mediatek: fixup: Disable tuner_en before change PLL rate

On Fri, 2018-12-14 at 13:57 -0800, Stephen Boyd wrote: > Why is "fixup" in the subject of this patch? > I'll fix in next version. > Quoting Weiyi Lu (2018-12-09 23:32:29) > > From: Owen Chen > > > > PLLs with tuner_en bit, such as APLL1, nee

Re: [PATCH v3 02/12] clk: mediatek: add new clkmux register API

On Mon, 2018-12-10 at 20:30 +0800, Nicolas Boichat wrote: > On Mon, Dec 10, 2018 at 3:33 PM Weiyi Lu wrote: > > > > From: Owen Chen > > > > On both MT8183 & MT6765, there add "set/clr" register for > > each clkmux setting, and one update register

Re: [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support

On Fri, 2018-12-14 at 13:59 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2018-12-09 23:32:36) > > + "apll2_ck" > > +}; > > + > > +static const struct mtk_mux top_muxes[] = { > > + /* CLK_CFG_0 */ > > + MUX

Re: [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off

On Fri, 2018-12-14 at 14:01 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2018-12-09 23:32:40) > > From: James Liao > > > > Some modules may need to change its clock rate before turn on it. > > So changing PLL's rate when it is off should be allowed. > >

[resend PATCH v1 0/2] update Mediatek MT2712 clock

This series is based on v4.20-rc1. Basically, this series is for the 3rd ECO design change of MT2712.

[resend PATCH v1 0/2] update Mediatek MT2712 clock

This series is based on v4.20-rc1. Basically, this series is for the 3rd ECO design change of MT2712. Weiyi Lu (2): dt-bindings: clock: add clock for MT2712 clk: mediatek: update clock driver of MT2712 drivers/clk/mediatek/clk-mt2712.c | 8 ++-- include/dt-bindings/clock/mt2712

[resend PATCH v1 2/2] clk: mediatek: update clock driver of MT2712

According to 3rd ECO design change, 1. Add new fixed factor clock of audio. 2. Add the parent clocks for audio clock mux. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mt2712.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c

[resend PATCH v1 1/2] dt-bindings: clock: add clock for MT2712

Add new clock according to 3rd ECO design change. It's the parent clock of audio clock mux. Signed-off-by: Weiyi Lu --- include/dt-bindings/clock/mt2712-clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bin

[PATCH v3 01/12] clk: mediatek: fixup: Disable tuner_en before change PLL rate

From: Owen Chen PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Another minor change

[PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data

Signed-off-by: Weiyi Lu Acked-by: Sean Wang --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 12 +--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e

[PATCH v3 07/12] clk: mediatek: Add flags support for mtk_gate data

On some Mediatek platforms, there are critical clocks of clock gate type. To register clock gate with flags CLK_IS_CRITICAL, we need to add the flags field in mtk_gate data and register APIs. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-gate.c | 5 +++-- drivers/clk/mediatek/clk-gate.h

[PATCH v3 11/12] soc: mediatek: Add MT8183 scpsys support

Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 226 ++ 1 file changed, 226 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 98ccef566ce1..58d84fe33d2a 100644 --- a

[PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off

d because its enable bit is 0. (am from https://patchwork.kernel.org/patch/9411983/) Signed-off-by: James Liao Acked-by: Michael Turquette Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek

[PATCH v3 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks

Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt8183-clk.h | 422 + 1 file changed, 422 insertions(+) create mode 100644 include/dt

[PATCH v3 02/12] clk: mediatek: add new clkmux register API

lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Makefile | 3 +- drivers/clk/mediatek/clk-mux.c | 229 + drivers/clk/mediatek/clk-mux.h | 101 ++

[PATCH v3 08/12] clk: mediatek: Add MT8183 clock support

Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Kconfig | 75 ++ drivers/clk/mediatek/Makefile | 12 + drivers/clk/mediatek/clk-gate.h| 14 + drivers/clk

[PATCH v3 00/11] Mediatek MT8183 clock and scpsys support

This series is based on v4.20-rc1 and most of changes are extracted from series below (clock/scpsys common changes for both MT8183 & MT6765) https://patchwork.kernel.org/patch/10528495/ (clock support of MT8183) https://patchwork.kernel.org/patch/10549891/ The whole series is composed of clock co

[PATCH v3 04/12] soc: mediatek: add new flow for mtcmos power.

d to do clock and internal isolation while power on/off sram. We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to do the extra sram isolation control or not. Signed-off-by: Owen Chen Signed-off-by: Mars Cheng Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/M

[PATCH v3 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183

This patch adds the binding documentation for apmixedsys, audiosys, camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys, vencsys and ipu for Mediatek MT8183. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings

[PATCH v3 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings

fix incorrect IC name that will affect the MT8183 power dt-bindings Signed-off-by: Weiyi Lu --- include/dt-bindings/power/mt8173-power.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h

[PATCH v3 10/12] dt-bindings: soc: Add MT8183 power dt-bindings

Add power dt-bindings for MT8183. Signed-off-by: Weiyi Lu --- .../bindings/soc/mediatek/scpsys.txt | 14 ++ include/dt-bindings/power/mt8183-power.h | 26 +++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/power/mt8183-power.h

[PATCH v3 00/12] Mediatek MT8183 clock and scpsys support

iatek: Allow changing PLL rate when it is off Owen Chen (4): clk: mediatek: fixup: Disable tuner_en before change PLL rate clk: mediatek: add new clkmux register API clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data soc: mediatek: add new flow for mtcmos power. Weiyi Lu (7):

[PATCH v2 09/11] dt-bindings: soc: fix typo of MT8173 power dt-bindings

fix incorrect IC name that will affect the MT8183 power dt-bindings Signed-off-by: Weiyi Lu --- include/dt-bindings/power/mt8173-power.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h

[PATCH v2 11/11] soc: mediatek: Add MT8183 scpsys support

Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 227 +- 1 file changed, 226 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 80be2e05e4e0..aac76c45a681

[PATCH v2 10/11] dt-bindings: soc: Add MT8183 power dt-bindings

Add power dt-bindings for MT8183. Signed-off-by: Weiyi Lu --- .../bindings/soc/mediatek/scpsys.txt | 14 ++ include/dt-bindings/power/mt8183-power.h | 26 +++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/power/mt8183-power.h

[PATCH v2 03/11] clk: mediatek: Disable tuner_en before change PLL rate

From: Owen Chen PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Signed-off-by: Owen

[PATCH v2 00/11] Mediatek MT8183 clock and scpsys support

rect control address and missing clocks. Owen Chen (4): clk: mediatek: add new clkmux register API clk: mediatek: add new member to mtk_pll_data clk: mediatek: Disable tuner_en before change PLL rate soc: mediatek: add new flow for mtcmos power. Weiyi Lu (7): dt-bindings: ARM: Mediat

[PATCH v2 08/11] clk: mediatek: Add MT8183 clock support

Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Kconfig | 75 ++ drivers/clk/mediatek/Makefile | 12 + drivers/clk/mediatek/clk-gate.h| 14 + drivers/clk

[PATCH v2 02/11] clk: mediatek: add new member to mtk_pll_data

Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 12 +--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e..11b5517903d0 100644 --- a

[PATCH v2 05/11] dt-bindings: ARM: Mediatek: Document bindings for MT8183

This patch adds the binding documentation for apmixedsys, audiosys, camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys, vencsys and ipu for Mediatek MT8183. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings

[PATCH v2 06/11] clk: mediatek: Add dt-bindings for MT8183 clocks

Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt8183-clk.h | 422 + 1 file changed, 422 insertions(+) create mode 100644 include/dt

[PATCH v2 01/11] clk: mediatek: add new clkmux register API

lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mux.c | 240 + drivers/clk/mediatek/clk-mux.h | 101 +

[PATCH v2 07/11] clk: mediatek: Add flags support for mtk_gate data

On some Mediatek platforms, there are critical clocks of clock gate type. To register clock gate with flags CLK_IS_CRITICAL, we need to add the flags field in mtk_gate data and register APIs. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-gate.c | 5 +++-- drivers/clk/mediatek/clk-gate.h

[PATCH v2 00/11] Mediatek MT8183 clock and scpsys support

This series is based on v4.20-rc1 and most of changes are extracted from series below (clock/scpsys common changes for both MT8183 & MT6765) https://patchwork.kernel.org/patch/10528495/ (clock support of MT8183) https://patchwork.kernel.org/patch/10549891/ The whole series is composed of clock com

[PATCH v2 04/11] soc: mediatek: add new flow for mtcmos power.

d to do clock and internal isolation while power on/off sram. We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to do the extra sram isolation control or not. Signed-off-by: Owen Chen Signed-off-by: Mars Cheng Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/M

Re: [PATCH v1 04/11] soc: mediatek: add new flow for mtcmos power.

On Wed, 2018-11-21 at 00:07 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2018-11-19 18:37:34) > > On Tue, 2018-11-13 at 11:31 -0800, Nicolas Boichat wrote: > > > On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote: > > > > > @@ -226,6 +397,7 @@ static int scpsys_

Re: [PATCH v1 01/11] clk: mediatek: add new clkmux register API

On Tue, 2018-11-13 at 08:00 -0800, Nicolas Boichat wrote: > On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote: > > > > From: Owen Chen > > > > On both MT8183 & MT6765, there add "set/clr" register for > > each clkmux setting, and one update register

Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data

On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote: > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote: > > > > From: Owen Chen > > > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > >add a variable to indicate this change and > &

Re: [PATCH v1 04/11] soc: mediatek: add new flow for mtcmos power.

On Tue, 2018-11-13 at 11:31 -0800, Nicolas Boichat wrote: > (not a complete review...) > > On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote: > > > > From: Owen Chen > > > > Both MT8183 & MT6765 add more bus protect node than previous project, > > there

Re: [PATCH v1 08/11] clk: mediatek: Add MT8183 clock support

On Tue, 2018-11-13 at 22:25 -0800, Nicolas Boichat wrote: > On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote: > > > > Add MT8183 clock support, include topckgen, apmixedsys, > > infracfg, mcucfg and subsystem clocks. > > > > Signed-off-by: Weiyi Lu > >

Re: [PATCH v1 11/11] soc: mediatek: Add MT8183 scpsys support

On Tue, 2018-11-13 at 11:35 -0800, Nicolas Boichat wrote: > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote: > > > > Add scpsys driver for MT8183 > > > > Signed-off-by: Weiyi Lu > > --- > > drivers/soc/mediatek/mtk-scpsys.c | 226 +++

[PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data

From: Owen Chen 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, add a variable to indicate this change and backward-compatible. 2. fmin: The pll freqency lower-bound is vary from 1GMhz to 1.5Ghz, add a variable to indicate platform-dependent. Signed-off-by: Owen Chen

[PATCH v1 03/11] clk: mediatek: Disable tuner_en before change PLL rate

From: Owen Chen PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Signed-off-by: Owen

[PATCH v1 07/11] clk: mediatek: Add flags support for mtk_gate data

On some Mediatek platforms, there are critical clocks of clock gate type. To register clock gate with flags CLK_IS_CRITICAL, we need to add the flags field in mtk_gate data and register APIs. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-gate.c | 5 +++-- drivers/clk/mediatek/clk-gate.h

[PATCH v1 11/11] soc: mediatek: Add MT8183 scpsys support

Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 226 ++ 1 file changed, 226 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 80be2e05e4e0..57b9f04a69de 100644 --- a

[PATCH v1 01/11] clk: mediatek: add new clkmux register API

lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mux.c | 252 + drivers/clk/mediatek/clk-mux.h | 101

[PATCH v1 08/11] clk: mediatek: Add MT8183 clock support

Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Kconfig | 75 ++ drivers/clk/mediatek/Makefile | 12 + drivers/clk/mediatek/clk-mt8183-audio.c| 112 ++ drivers/clk

[PATCH v1 09/11] dt-bindings: soc: fix typo of MT8173 power dt-bindings

fix incorrect IC name that will affect the MT8183 power dt-bindings Signed-off-by: Weiyi Lu --- include/dt-bindings/power/mt8173-power.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h

[PATCH v1 06/11] clk: mediatek: Add dt-bindings for MT8183 clocks

Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt8183-clk.h | 421 + 1 file changed, 421 insertions(+) create mode 100644 include/dt

[PATCH v1 05/11] dt-bindings: ARM: Mediatek: Document bindings for MT8183

This patch adds the binding documentation for apmixedsys, audiosys, camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys, vencsys and ipu for Mediatek MT8183. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings

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