no other source of information about this available (except
directly comparing two datasheets...).
Better get the DT stuff correctly right from the start. That's why I'm asking
what chips contains the IP block, so we can guess the right name.
Best regards,
Marek Vasut
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On Sunday, May 25, 2014 at 01:58:39 PM, Corentin LABBE wrote:
[...]
This is one IP block and it provides 5 algorithms. Put it under one
config option please.
I want to let the user choose what it want to be used. Someone could want
only to accelerate md5 and to not use the PRNG. Lots of
+ drivers/crypto/Makefile
| 1 +
2 files changed, 92 insertions(+)
This should be part of 1/4, otherwise 1/4 just adds dead code.
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On Tuesday, June 10, 2014 at 02:43:14 PM, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE Corentin
/types.h
index 084d882..675c2d8 100644
--- a/include/linux/iio/types.h
+++ b/include/linux/iio/types.h
@@ -30,6 +30,7 @@ enum iio_chan_type {
IIO_CCT,
IIO_PRESSURE,
IIO_HUMIDITYRELATIVE,
+ IIO_DISTANCE,
};
enum iio_modifier {
Best regards,
Marek Vasut
On Friday, January 31, 2014 at 04:38:23 PM, Matt Ranostay wrote:
[...]
diff --git a/Documentation/devicetree/bindings/iio/distance/as3935.txt
b/Documentation/devicetree/bindings/iio/distance/as3935.txt new file mode
100644
index 000..af35827
--- /dev/null
+++
against concurent execution so the chip won't
be confused if a user were to poke something via SYSFS twice.
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...@free-electrons.com
---
drivers/staging/iio/adc/mxs-lradc.c | 4
1 file changed, 4 deletions(-)
Changelog's missing ;-)
Acked-by: Marek Vasut ma...@denx.de
diff --git a/drivers/staging/iio/adc/mxs-lradc.c
b/drivers/staging/iio/adc/mxs-lradc.c index 7fc66a6a6e36..d304156ca2f7
100644
/+bug/1258332
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On Wednesday, December 18, 2013 at 05:16:13 PM, Luis Henriques wrote:
Hi Marek,
On Tue, Dec 17, 2013 at 08:39:03PM +0100, Marek Vasut wrote:
On Tuesday, December 17, 2013 at 07:12:46 PM, Luis Henriques wrote:
3.5.7.28 -stable review patch. If anyone has any objections, please
let me
of
trying to clear the outstanding stuff in my in box ;)
Applied to the togreg branch of iio.git
Thanks,
I dont mind, thanks for geting these in. And happy new year to you guys :)
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requested, thanks!
Whole series otherwise:
Acked-by: Marek Vasut ma...@denx.de
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is obvious. The device
probably works anyway since the device/driver will use default values.
Full agreement here.
Reviewed-by: Marek Vasut ma...@denx.de
btw. I plan to rework the STMPE TS as it doesn't work nicely on my device at
all. I am seriously lacking time, but I will try! ;-)
Best regards
of PXA27x board.
I don't have any either right now ...
On VPAC270
Tested-by: Marek Vasut ma...@denx.de
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a flag
to the chip specific data to solve this. Also some unnecessary ifdefs
are removed.
Sascha
Went through the whole series,
Acked-by: Marek Vasut ma...@denx.de
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) },
+ { cat25128, CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE) },
{ },
};
MODULE_DEVICE_TABLE(spi, m25p_ids);
I can't say I like the growing macro magic (voodoo?) in this file, but your
patch doesn't break anything and I don't feel like reworking this, so:
Acked-by: Marek Vasut ma
driver in 47 patches ? Whoa ;-)
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.
Then for the second question, maybe there are some other ways, But I think
it is more tidy and easier understanding for using a separate variable,
for this purpose.
You are just wasting space and duplicating data, unless I am wrong.
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On Wednesday, March 26, 2014 at 06:56:34 AM, Yao Yuan wrote:
On Wednesday, March 26, 2014 at 11:43:27 AM, Marek Vasut wrote:
On Wednesday, March 26, 2014 at 04:08:27 AM, Yao Yuan wrote:
[...]
+ i2c_imx-use_dma = false;
+ } else if (i2c_imx_dma_request(i2c_imx
On Wednesday, March 26, 2014 at 08:08:28 AM, Yao Yuan wrote:
On Wednesday, March 26, 2014 at 02:27:46 PM, Marek Vasut wrote:
On Wednesday, March 26, 2014 at 06:56:34 AM, Yao Yuan wrote:
On Wednesday, March 26, 2014 at 11:43:27 AM, Marek Vasut wrote:
On Wednesday, March 26, 2014 at 04:08
as 0x000_. Whenever we try to write to
say 0x2000_, it will be translated to whatever we have programmed in
the translation window with base as 0x000_.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
(+cc Pratyush Anand, Marek Vasut, Richard Zhu)
Thanks.
Acked-by: Jingoo Han jg1
On Saturday, April 26, 2014 at 05:10:13 AM, Huang Shijie wrote:
On Sat, Apr 26, 2014 at 12:12:24AM +0200, Marek Vasut wrote:
the drivers may fills this hook itself, so the code should like this:
--
if ((info-flags
which has unmet direct dependencies (CRYPTO)
Fix this in the Kconfig by depending on CRYPTO.
Reported-by: Fengguang Wu fengguang...@intel.com
Signed-off-by: Jason Cooper ja...@lakedaemon.net
Reviewed-by: Marek Vasut ma...@denx.de
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On Tuesday, May 06, 2014 at 03:33:51 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
[...]
+#define to_dra7xx_pcie(x)container_of((x), struct dra7xx_pcie, pp)
+
+static inline
channel request failed\n);
+ ret = -ENODEV;
+ goto fail_al;
+ }
[...]
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than those two things,
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to read status register until
ready, or timeout occurs. * Returns non-zero if error.
*/
-static int wait_till_ready(struct m25p *flash)
+static int _wait_till_ready(struct m25p *flash)
Please avoid using function names that start with underscore .
[...]
Thanks!
Best regards,
Marek Vasut
have a
single standard for all the SF chips which won't need all these crappy quirks
:-(
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On Wednesday, April 23, 2014 at 07:43:35 PM, Christian Engelmayer wrote:
On Wed, 23 Apr 2014 01:33:05 +0200, Marek Vasut ma...@denx.de wrote:
On Monday, April 21, 2014 at 08:45:59 PM, Christian Engelmayer wrote:
+ if (aad_size = PAGE_SIZE) {
On an unrelated note ... Won't if (aad_size
On Friday, April 25, 2014 at 03:34:36 AM, Huang Shijie wrote:
On Tue, Apr 22, 2014 at 09:03:16AM -0500, Graham Moore wrote:
Some new Micron flash chips require reading the flag
status register to determine when operations have completed.
Furthermore, chips with multi-die stacks of the
On Friday, April 25, 2014 at 06:47:04 AM, Huang Shijie wrote:
On Tue, Apr 22, 2014 at 01:48:21PM -0500, Graham Moore wrote:
On Tue, Apr 22, 2014 at 11:55 AM, Marek Vasut ma...@denx.de wrote:
Are you sure the n25q512a doesn't use FSR ? Do n25q512a{1,8}3 share the
same IDs?
I looked
On Friday, April 25, 2014 at 03:52:46 AM, Huang Shijie wrote:
On Fri, Apr 25, 2014 at 04:42:33AM +0200, Marek Vasut wrote:
On Friday, April 25, 2014 at 03:34:36 AM, Huang Shijie wrote:
On Tue, Apr 22, 2014 at 09:03:16AM -0500, Graham Moore wrote:
Some new Micron flash chips require
libraries.
It did look like a library to me at first, but it's rather a subsystem that
contains a small library in it. Thus, I retract my previous comment about using
'select' and add :
Acked-by: Marek Vasut ma...@denx.de
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n25q512a{1,8}3 share the same
IDs?
[...]
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On Tuesday, April 22, 2014 at 08:48:21 PM, Graham Moore wrote:
On Tue, Apr 22, 2014 at 11:55 AM, Marek Vasut ma...@denx.de wrote:
Are you sure the n25q512a doesn't use FSR ? Do n25q512a{1,8}3 share the
same IDs?
I looked at the datasheet and the n25q512a *does* have the same FSR
usage
Reviewed-by: Marek Vasut ma...@denx.de
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On Monday, April 21, 2014 at 08:45:59 PM, Christian Engelmayer wrote:
Fix a potential memory leak in the error handling of test_aead_speed(). In
case the size check on the associate data length parameter fails, the
function goes through the wrong exit label. Reported by Coverity - CID
1163870.
-off-by: Christian Engelmayer cenge...@gmx.at
Looks OK to me, thanks.
Reviewed-by: Marek Vasut ma...@denx.de
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On Wednesday, April 16, 2014 at 02:26:41 PM, Austin Boyle wrote:
On Sun, 13 Apr 2014, Marek Vasut wrote:
This portion of code looks like a duplicate of ...
+ for (lock_bits = 1; lock_bits 7; lock_bits++) {
+ protected_area_start = flash-mtd.size
.
From: Austin Boyle boyle.aus...@gmail.com
Signed-off-by: Austin Boyle boyle.aus...@gmail.com
Acked-by: Marek Vasut ma...@denx.de
Thanks!
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More
just select the SPI NOR framework? Then you won't
need the adjustment to defconfigs at all I think.
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: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
mxs_defconfig is
Reviewed-by: Marek Vasut ma...@denx.de
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(*sha512_transform_asm)(const char *, u64 *, ^
Drop asmlinkage here to avoid such warnings.
Also see Commit 8783dd3a37a5853689e1(irqchip: Remove asmlinkage from
static functions)
Signed-off-by: Jianyu Zhan nasa4...@gmail.com
Makes sense, please add my humble
Reviewed-by: Marek Vasut ma
On Wednesday, April 09, 2014 at 08:14:49 PM, Graham Moore wrote:
On Wed, Apr 9, 2014 at 6:09 AM, Gerhard Sittig g...@denx.de wrote:
On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
From: Graham Moore grmo
,
Marek Vasut
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On Sunday, April 06, 2014 at 01:19:59 PM, Austin Boyle wrote:
[...]
@@ -752,24 +773,18 @@ static int m25p80_lock(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
status_old = read_sr(flash);
- if (offset flash-mtd.size-(flash-mtd.size/2))
- status_new = status_old |
On Monday, April 14, 2014 at 06:19:24 PM, Graham Moore wrote:
On Sun, Apr 13, 2014 at 12:18 PM, Marek Vasut ma...@denx.de wrote:
[...]
+#define OPCODE_RDFSR0x70 /* read flag status register
*/
I know this is not your fault, but can you please indent this properly
string.
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of
discussing it all around !?
Only one question comes to mind with this email -- what do LRADC and I2C have
to
do with each other here ?
It'd be nice if someone could summarize on what I should focus and possibly
prepare a testcase.
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, for
example by switching to software operations or such in some sane way ?
I presume that's the concern here.
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On Wednesday, July 09, 2014 at 05:24:26 PM, Andy Shevchenko wrote:
The new seq_hex_dump() is a complete analogue of print_hex_dump().
We have few users of this functionality already. It allows to reduce their
codebase.
Signed-off-by: Andy Shevchenko andriy.shevche...@linux.intel.com
---
On Thursday, July 10, 2014 at 01:05:39 AM, Dmitry Kasatkin wrote:
On 10 July 2014 00:00, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 08, 2014 at 10:07:16 AM, Dmitry Kasatkin wrote:
[...]
Right, but my concern is not about unloading the kernel module, but
about the IMA module
On Wednesday, July 09, 2014 at 11:21:08 PM, Joe Perches wrote:
On Wed, 2014-07-09 at 22:39 +0200, Marek Vasut wrote:
The above function looks like almost verbatim copy of print_hex_dump().
The only difference I can spot is that it's calling seq_printf() instead
of printk(). Can you
fallback will be used.
Ah, thank you for clearing this!
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will consume quite
a
lot of CPU time to do that, can you not implement DMA here ?
[...]
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On Sunday, June 22, 2014 at 01:58:38 PM, Corentin LABBE wrote:
Le 14/06/2014 21:01, Marek Vasut a écrit :
On Tuesday, June 10, 2014 at 02:43:15 PM, LABBE Corentin wrote:
Add necessary changes for configuring and compiling the Security System
driver.
Signed-off-by: LABBE Corentin
On Sunday, June 22, 2014 at 02:33:35 PM, Russell King - ARM Linux wrote:
On Sun, Jun 22, 2014 at 02:23:15PM +0200, Marek Vasut wrote:
On Sunday, June 22, 2014 at 01:58:08 PM, Corentin LABBE wrote:
[...]
+ * This program is free software; you can redistribute it and/or
modify
only ever be in L1 and never in lower
levels of the page table ?
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Please read
(softint,
+gic_data_dist_base(gic_data[0]) + GIC_DIST_SOFTINT);
raw_spin_unlock_irqrestore(irq_controller_lock, flags);
}
[...]
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rickard_strandqv...@spectrumdigital.se
Makes perfect sense.
Acked-by: Marek Vasut ma...@denx.de
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/input/serio/olpc_apsp.ko] undefined!
ERROR: devm_ioremap_resource [drivers/input/serio/arc_ps2.ko] undefined!
This stuff should go through different trees, so I'd suggest to split this into
multiple patches. Thanks for catching this stuff !
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-by: Chen Gang gang.chen.5...@gmail.com
Acked-by: Marek Vasut ma...@denx.de
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On Tuesday, July 15, 2014 at 11:41:25 AM, Daniel Thompson wrote:
On 14/07/14 14:51, Harro Haan wrote:
On 10 July 2014 10:03, Daniel Thompson daniel.thomp...@linaro.org wrote:
This patchset makes it possible to use kgdb's NMI infrastructure on ARM
platforms.
The patches have been
iio: mxs-lradc: add scale_available file to channels
iio: mxs-lradc: add write_raw function to modify scale
drivers/staging/iio/adc/mxs-lradc.c | 222
+++- 1 file changed, 219 insertions(+), 3
deletions(-)
Why is there a resend please ?
Best regards,
Marek
On Monday, December 23, 2013 at 08:22:04 PM, Alexandre Belloni wrote:
On 23/12/2013 19:54, Marek Vasut wrote:
On Monday, December 23, 2013 at 06:48:00 PM, Alexandre Belloni wrote:
Hello,
This is v5 of the patchset that adds support to the optional
divider_by_two of LRADC channels
On Thursday, February 06, 2014 at 09:26:26 AM, Jingoo Han wrote:
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han jg1@samsung.com
Acked-by: Marek Vasut ma...@denx.de
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Marek Vasut
,
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On Tuesday, August 26, 2014 at 09:17:59 AM, Robin Gong wrote:
On Mon, Aug 25, 2014 at 10:07:22AM +0200, Marek Vasut wrote:
On Saturday, August 23, 2014 at 02:13:55 AM, Robin Gong wrote:
After enable DMA
Please also add a commit message which describes the change, not only
some test
On Wednesday, July 23, 2014 at 10:24:41 AM, Yuan Yao wrote:
Changed in v5:
- add *chan_dev = dma-chan_using-device-dev for reduce the call time.
Did you check if the compiler generates different code ?
- add the test logs.
[...]
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On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu wrote:
On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
+ }
+#endif
+
+#ifdef CONFIG_CRYPTO_DEV_SUNXI_SS_MD5
+ err = crypto_register_shash(sunxi_md5_alg);
Do not use shash for such device. This is clearly
On Wednesday, July 23, 2014 at 04:13:09 PM, Herbert Xu wrote:
On Wed, Jul 23, 2014 at 04:07:20PM +0200, Marek Vasut wrote:
On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu wrote:
On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
+ }
+#endif
+
+#ifdef
is exected to be DMA capable, it means something
is
wrong anyway.
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Please read
On Wednesday, July 23, 2014 at 08:52:12 PM, Corentin LABBE wrote:
Le 23/07/2014 17:51, Marek Vasut a écrit :
On Wednesday, July 23, 2014 at 04:13:09 PM, Herbert Xu wrote:
On Wed, Jul 23, 2014 at 04:07:20PM +0200, Marek Vasut wrote:
On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu
. At that time I have no device to debug it. Now, I'm come
back and I will try my best to finish it. I have sent the patch for V5.
Thanks for your review.
So you have no means to test this ? Can this be tested on MX5 ? MX6 ?
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On Thursday, July 24, 2014 at 05:36:34 AM, Yao Yuan wrote:
Hi,
Marek Vasut wrote:
On Wednesday, July 23, 2014 at 10:24:41 AM, Yuan Yao wrote:
Changed in v5:
- add *chan_dev = dma-chan_using-device-dev for reduce the call
time.
Did you check if the compiler generates different
On Tuesday, October 14, 2014 at 08:36:21 AM, Chao Fu wrote:
From: Chao Fu b44...@freescale.com
FSL Quadspi module register bitwise is big-endian, but on ohter paltform
is little endian.
Add functions for Quadspi register read/write for bitwise:
qspi_readl
qpsi_writel
The commit message
in case the newly added condition isn't
met ? The old code initialized $info to a certain value always, the new code
does not do that.
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More
Simek michal.si...@xilinx.com
Acked-by: Marek Vasut ma...@denx.de
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Please read
already support
plenty of SST flashes without this patch, don't we?
This change is so trivial that saying we're adding this new flash chip ID to
the ID table, which is what Michal did, is completely sufficient in my opinion.
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On Friday, September 05, 2014 at 12:32:40 PM, Yao Yuan wrote:
[...]
+static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
+ struct i2c_msg *msgs)
+{
+ int result;
+ unsigned int temp = 0;
+ unsigned long orig_jiffies = jiffies;
+ struct
pointless things ? Please stop me if you
think I do.
[...]
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Please read the FAQ
my commit message and sumbit it again.thanks.
Thank you. I didn't mean to grind you unnecessarily or be outright bitch, sorry
if it did sound like so.
Best regards,
Marek Vasut
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. When EVCR bit 7 is reset to 0, the SPI NOR flash will
operate in quad I/O mode.
Signed-off-by: bean huo bean...@micron.com
I don't see anything obviously wrong.
Acked-by: Marek Vasut ma...@denx.de
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for the patch Stephan!
Marek Vasut ma...@denx.de has also been working on a set of
documentation for the crypto API so he might have some comments
on this.
Sorry for the late reply, thanks for keeping me in the loop.
I can share the last state of the document I wrote. Currently,
it is not possible
On Friday, October 31, 2014 at 08:23:53 AM, Herbert Xu wrote:
On Fri, Oct 31, 2014 at 04:01:04AM +0100, Marek Vasut wrote:
I can share the last state of the document I wrote. Currently,
it is not possible for me to keep up with my workload and do
anything else, so that's all I can do
On Thursday, September 18, 2014 at 05:46:04 PM, Yao Yuan wrote:
Marek Vasut wrote:
On Wednesday, September 17, 2014 at 04:50:34 PM, Yao Yuan wrote:
[...]
Would that mean that the crashed DMA would be running until the
next transmission is scheduled ?
[Yuan Yao
applies to all other socfpga patches across all MLs).
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* 1024, 128, SECT_4K) },
Looks OK,
Acked-by: Marek Vasut ma...@denx.de
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Please
On Wednesday, August 13, 2014 at 11:46:54 AM, Yuan Yao wrote:
Add dma support for i2c. This function depend on DMA driver.
You can turn on it by write both the dmas and dma-name properties in dts
node. DMA is optional, even DMA request unsuccessfully, i2c can also work
well.
Signed-off-by:
On Wednesday, September 10, 2014 at 04:48:01 PM, Yao Yuan wrote:
On Friday, September 05, 2014 6:41 PM, Marek Vasut wrote:
On Friday, September 05, 2014 at 12:32:40 PM, Yao Yuan wrote:
[...]
+static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx
, spi will use PIO mode. This patch only
validate on i.mx6, not i.mx5, but encourage ones to apply this patch
on i.mx5 since they share the same IP.
Adding Maerk (who I had to add to earlier versions of this patch).
Looks OK to me.
Acked-by: Marek Vasut ma...@denx.de
Thank you!
Best
to prove that my design is acceptable.
So if you are sure it's flawed, I will change it in the next version(V8).
I'm just trying to understand it.
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Marek Vasut
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do
you
think ?
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On Sunday, September 28, 2014 at 03:59:42 AM, bpqw wrote:
For Micron spi norflash,you can enable
Quad spi transfer by clear EVCR(Enhanced
Volatile Configuration Register) Quad I/O
protocol bit.
OK, this information is nice and all, but what does this patch do? I can't
learn
this information
if I want to just get the
high-level
overview of what the patch does. If I want to know the details, I will look
into
the code.
Do you know what I'm getting at ?
[...]
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wrong with the patch I think.
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On Thursday, September 25, 2014 at 10:11:27 AM, Yuan Yao wrote:
Changed in v8:
- some minor fixes for coding style.
- unsetting I2CR_DMAEN immediatelly when failed in DMA mode.
Brief skim over the patch doesn't show any dangling problems.
Reviewed-by: Marek Vasut ma...@denx.de
btw. the U
,
Reviewed-by: Marek Vasut ma...@denx.de
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\n, ssrc);
+ return;
+ }
/*
* If there is no further error handling function, just
This indeed makes sense.
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On Sunday, December 14, 2014 at 04:28:53 PM, Stefan Wahren wrote:
According to i.MX23 and i.MX28 reference manual the fractional
clock control registers must be addressed by byte instructions.
This patch fixes the erroneous 32-bit access to these registers.
The changes has been tested only
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