On Wed, Oct 28, 2020 at 01:30:32PM +, Dave Stevenson wrote:
> Hi Maxime
>
> On Wed, 8 Jul 2020 at 15:46, Maxime Ripard wrote:
> >
> > Since the components for a given device in ASoC are identified by their
> > name, it makes sense to add one even though
nner H6 IOMMU driver")
> Signed-off-by: Yu Kuai
Acked-by: Maxime Ripard
Thanks!
Maxime
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ed-off-by: Dinghao Liu
Acked-by: Maxime Ripard
Maxime
Hi Frank,
On Mon, Oct 19, 2020 at 07:58:36PM +0800, Frank Lee wrote:
> From: Yangtao Li
>
> Thw bitmap_* API is the standard way to access data in the bitfield.
>
> Signed-off-by: Yangtao Li
> ---
> drivers/thermal/sun8i_thermal.c | 35 +
> 1 file changed, 18
On Tue, Oct 27, 2020 at 11:15:58AM +0100, Maxime Ripard wrote:
> When running the trigger hook, ALSA by default will take a spinlock, and
> thus will run the trigger hook in atomic context.
>
> However, our HDMI driver will send the infoframes as part of the trigger
>
On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 26 Oct 20, 17:14, Maxime Ripard wrote:
> > i2c? :)
>
> Oops, good catch!
>
> > On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> > > This introduces
On Tue, Oct 27, 2020 at 10:31:19AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 26 Oct 20, 17:00, Maxime Ripard wrote:
> > On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> > > Bits related to the interface data width do not have any effect when
Hi,
On Tue, Oct 27, 2020 at 10:23:26AM +0100, Paul Kocialkowski wrote:
> On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> > On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> >
e ASoC core has a
> runtime PM reference to the device.
>
> Signed-off-by: Samuel Holland
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Clément Péron
Acked-by: Maxime Ripard
Maxime
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s distorted.
>
> Set sign extend sample for all the sunxi generations even if they
> are not affected. This will keep consistency and avoid relying on
> default.
>
> Signed-off-by: Marcus Cooper
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Clément Péron
Acked-by: Maxime Ripard
Maxime
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wed-by: Chen-Yu Tsai
> Signed-off-by: Clément Péron
Acked-by: Maxime Ripard
Maxime
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frame +
> + * padding slots, regardless of format. "slot_width" means bits
> + * per sample + padding bits, regardless of format.
> + */
> unsigned int slots = channels;
> + unsigned int slot_width = params_physical_width(params);
> +
what I meant was to put that comment next to the function pointer in the
structure sun4i_i2s_quirks, it would be fairly easy to miss here.
With that fixed,
Acked-by: Maxime Ripard
Maxime
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igned-off-by: Clément Péron
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Maxime
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Hi,
On Tue, Oct 27, 2020 at 01:14:42PM +0900, Hoegeun Kwon wrote:
> There is a problem that if vc4_drm bind fails, a memory leak occurs on
> the drm_property_create side. Add error handding for drm_mode_config.
>
> Signed-off-by: Hoegeun Kwon
Applied, thanks!
Maxime
signature.asc
Hi Stephen,
On Tue, Oct 27, 2020 at 10:42:20AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the sunxi tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> arch/arm/boot/dts/sun8i-h3-zeropi.dts:53.25-63.4: ERROR (phandle_references):
> /gmac-3v3:
On Tue, Oct 27, 2020 at 06:12:58PM +0800, Yu-Tung Chang wrote:
> Signed-off-by: Yu-Tung Chang
Ah so it was to fix the build breakage in next. I've squashed it into
your previous patch.
Generally speaking though, a commit log is needed
Thanks!
Maxime
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is where the audio parameters that end up
in the infoframes are setup, this also makes a bit more sense.
Fixes: bb7d78568814 ("drm/vc4: Add HDMI audio support")
Suggested-by: Mark Brown
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 5 +++--
1 file changed, 3 insert
slot
> - 10/100/1000Mbps Ethernet
> - Debug Serial Port
> - DC 5V/2A power-supply
>
> Signed-off-by: Yu-Tung Chang
> Signed-off-by: Maxime Ripard
> Link: https://lore.kernel.org/r/20201026073536.13617-2-mtw...@gmail.com
Isn't it the patch that you sent and I merged yesterday? If y
ixes compile warning:
>
> drivers/mmc/host/sunxi-mmc.c:1181:34: warning: ‘sunxi_mmc_of_match’
> defined but not used [-Wunused-const-variable=]
>
> Reported-by: kernel test robot
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Maxime Ripard
Maxime
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On Fri, Oct 23, 2020 at 07:45:32PM +0200, Paul Kocialkowski wrote:
> This series introduces support for MIPI CSI-2, with the A31 controller that is
> found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific
> controller. While the former uses the same MIPI D-PHY that is already
On Fri, Oct 23, 2020 at 07:45:44PM +0200, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering both the
> protocol logic and the D-PHY implementation. This controller seems to be found
> on the A83T only and probably was abandonned since.
>
> This
On Fri, Oct 23, 2020 at 07:45:46PM +0200, Paul Kocialkowski wrote:
> The A83T MIPI CSI-2 apparently produces interrupts regardless of the mask
> registers, for example when a transmission error occurs.
>
> This generates quite a flood when unsolicited interrupts are received on
> each received
On Fri, Oct 23, 2020 at 07:45:43PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A83T MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
What is the difference with the a31/v3s one?
> ---
> .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 158
On Fri, Oct 23, 2020 at 07:45:42PM +0200, Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the V3s with an A31 controller, which seems
> to be used on all Allwinner chips supporting it, except for the A83T.
> The controller is connected to CSI0 through fwnode endpoints.
> The mipi_csi2_in
On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY block on
i2c? :)
On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++
> 1 file changed,
On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> Bits related to the interface data width do not have any effect when
> the CSI controller is taking input from the MIPI CSI-2 controller.
I guess it would be clearer to mention that the data width is only
applicable for parallel
On Fri, Oct 23, 2020 at 07:45:35PM +0200, Paul Kocialkowski wrote:
> This allows selecting a dedicated CMA memory pool (specified via
> device-tree) instead of the default one.
>
> Signed-off-by: Paul Kocialkowski
Why would that be needed?
> ---
>
On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> is already supported and used for MIPI DSI this adds support for the
> former, to be used with MIPI CSI-2.
>
> This implementation is inspired by the
Hi,
On Mon, Oct 26, 2020 at 08:54:21AM +1100, Stephen Rothwell wrote:
> On Thu, 8 Oct 2020 15:20:17 +0200 Maxime Ripard wrote:
> >
> > On Tue, Oct 06, 2020 at 02:56:37PM +1100, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > Today's linux-n
Hi,
On Mon, Oct 26, 2020 at 03:35:36PM +0800, Yu-Tung Chang wrote:
> The ZeroPi is another fun board developed
> by FriendlyELEC for makers,
> hobbyists and fans.
>
> ZeroPi key features
> - Allwinner H3, Quad-core Cortex-A7@1.2GHz
> - 256MB/512MB DDR3 RAM
> - microsd slot
> - 10/100/1000Mbps
On Sun, Oct 25, 2020 at 12:25:15AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> The Ethernet PHY on the Bananapi M64 has the RX and TX delays
> enabled on the PHY, using pull-ups on the RXDLY and TXDLY pins.
>
> Fix the phy-mode description to correct reflect this so that the
>
On Sun, Oct 25, 2020 at 09:19:49AM +0100, Jernej Skrabec wrote:
> Ethernet PHY on BananaPi M2 Ultra provides RX and TX delays. Fix
> ethernet node to reflect that fact.
>
> Fixes: c36fd5a48bd2 ("ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable GMAC
> ethernet controller")
> Signed-off-by: Jernej
On Fri, Oct 23, 2020 at 09:49:02PM +0200, Jernej Skrabec wrote:
> Ethernet PHY provides RX and TX delay on both models, A and B. Although
> schematic for model A suggests only TX delay, network never worked with
> such configuration.
>
> Fix ethernet node to reflect PHY delays.
>
> Fixes:
On Fri, Oct 23, 2020 at 08:48:58PM +0200, Jernej Skrabec wrote:
> RX and TX delay are provided by ethernet PHY. Reflect that in ethernet
> node.
>
> Fixes: 44a94c7ef989 ("arm64: dts: allwinner: H5: Restore EMAC changes")
> Signed-off-by: Jernej Skrabec
Applied, thanks
Maxime
signature.asc
Hi,
Thanks for your patch
On Fri, Oct 23, 2020 at 05:09:08PM +0800, Yu-Tung Chang wrote:
> The ZeroPi is another fun board developed
> by FriendlyELEC for makers,
> hobbyists and fans.
>
> ZeroPi key features
> - Allwinner H3, Quad-core Cortex-A7@1.2GHz
> - 256MB/512MB DDR3 RAM
> - microsd slot
On Thu, Oct 22, 2020 at 08:58:39PM +0200, Jernej Skrabec wrote:
> RX/TX delay on OrangePi Win board is set on PHY. Reflect that in
> ethernet node.
>
> Fixes: 93d6a27cfcc0 ("arm64: dts: allwinner: a64: Orange Pi Win: Add Ethernet
> node")
> Signed-off-by: Jernej Skrabec
Queued as a fix for
On Thu, Oct 22, 2020 at 11:13:01PM +0200, Jernej Skrabec wrote:
> According to board schematic, PHY provides both, RX and TX delays.
> However, according to "fix" Realtek provided for this board, only TX
> delay should be provided by PHY.
> Tests show that both variants work but TX only PHY delay
On Tue, Oct 20, 2020 at 02:59:54PM +0300, Serge Semin wrote:
> In accordance with the DWC USB3 bindings the corresponding node
> name is suppose to comply with the Generic USB HCD DT schema, which
> requires the USB nodes to have the name acceptable by the regexp:
> "^usb(@.*)?" . Make sure the
On Mon, Oct 19, 2020 at 06:34:49AM +, Corentin Labbe wrote:
> Since commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay
> config"),
> the network is unusable on PineH64 model A.
>
> This is due to phy-mode incorrectly set to rgmii instead of rgmii-id.
>
> Fixes: 729e1ffcf47e
On Sun, Oct 18, 2020 at 07:24:09PM +0200, Clément Péron wrote:
> Before the commit:
> net: phy: realtek: fix rtl8211e rx/tx delay config
>
> The software overwrite for RX/TX delays of the RTL8211e were not
> working properly and the Beelink GS1 had both RX/TX delay of RGMII
> interface set using
smaller data size PIO mode will be used. In PIO mode whole buffer will
> be loaded into FIFO.
>
> If driver failed to request DMA channels then it fallback for PIO mode.
>
> Tested on SOPINE (https://www.pine64.org/sopine/)
>
> Signed-off-by: Alexander Kochetkov
Hi Mark
On Thu, Oct 22, 2020 at 02:50:53PM +0100, Mark Brown wrote:
> On Thu, Oct 22, 2020 at 11:50:41AM +0200, Maxime Ripard wrote:
>
> > This is caused by the HDMI driver polling some status bit that reports
> > that the infoframes have been properly sent, and calling usleep
Hi Takashi,
On Thu, Oct 22, 2020 at 03:20:49PM +0200, Takashi Iwai wrote:
> On Thu, 22 Oct 2020 14:57:41 +0200,
> Maxime Ripard wrote:
> >
> > On Thu, Oct 22, 2020 at 12:03:19PM +0200, Jaroslav Kysela wrote:
> > > Dne 22. 10. 20 v 11:50 Maxime Ripard napsal(a):
> &
On Thu, Oct 22, 2020 at 12:03:19PM +0200, Jaroslav Kysela wrote:
> Dne 22. 10. 20 v 11:50 Maxime Ripard napsal(a):
>
> > So, I'm not really sure what I'm supposed to do here. The drivers
> > involved don't appear to be doing anything extraordinary, but the issues
> > lockd
Hi!
We currently have an issue reported by lockdep on the RaspberryPi and
its HDMI audio output where, at startup, we end up scheduling in atomic
context.
This is caused by the HDMI driver polling some status bit that reports
that the infoframes have been properly sent, and calling usleep_range
On Wed, Oct 21, 2020 at 10:33:25PM +0200, Jernej Skrabec wrote:
> If scaling matrix control is present, VPU should not use default matrix.
> Fix that.
>
> Fixes: b3a23db0e2f8 ("media: cedrus: Use H264_SCALING_MATRIX only when
> required")
> Signed-off-by: Jernej Skrab
Hi,
On Mon, Oct 19, 2020 at 04:17:18PM +0300, Alexander Kochetkov wrote:
> >> +static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
> >> + struct spi_transfer *tfr)
> >> +{
> >> + struct dma_async_tx_descriptor *rxdesc, *txdesc;
> >> + struct spi_master *master =
On Tue, Oct 20, 2020 at 11:52:34AM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 20, 2020 at 1:43 AM Alexander Kochetkov
> wrote:
> >
> >
> >
> > > 19 окт. 2020 г., в 11:21, Maxime Ripard написал(а):
> > >
> > > Hi!
> > >
> > >
obe() returns.
>
> Signed-off-by: Alexander Kochetkov
Acked-by: Maxime Ripard
Thanks!
Maxime
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On Sun, Oct 18, 2020 at 07:25:10PM +0200, Clément Péron wrote:
> HI Maxime,
>
> On Mon, 12 Oct 2020 at 13:22, Maxime Ripard wrote:
> >
> > Hi!
> >
> > On Sun, Oct 11, 2020 at 11:22:37PM +0200, Clément Péron wrote:
> > > Beelink GS1 LED
Hi Samuel,
On Mon, Oct 12, 2020 at 08:15:30PM -0500, Samuel Holland wrote:
> On 10/12/20 7:15 AM, Maxime Ripard wrote:
> > Hi,
> >
> > On Mon, Oct 05, 2020 at 03:23:12PM +0200, Clément Péron wrote:
> >> On Mon, 5 Oct 2020 at 14:13, Maxime Ripard wrote:
> >&g
On Mon, Oct 12, 2020 at 07:03:25PM +0200, Michal Suchánek wrote:
> > > >
> > > > > Also the boards that do not have the flsh are either broken or
> > > > > obsolete.
> > > >
> > > > Making general statements without arguments doesn't really make it true
> > > > though. Plenty of boards to have
Hi!
On Sat, Oct 10, 2020 at 06:46:03PM +0800, wuyan wrote:
> Signed-off-by: wuyan
A commit log would be welcome here. Also, the last time you contributed
you used the name Martin Wu in your Signed-off-by, it would be nice to
be consistent there.
> Change-Id:
> and use the DAI ID to select the correct register address.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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Wouldn't a depends on make more sense here? It's kind of weird to pull
it from a driver when the platform that would run it has no CCF support.
With this changed,
Acked-by: Maxime Ripard
Maxime
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on.
>
> Since the sample rate is tied to active AIF paths, disabling pmdown_time
> allows switching to the optimal sample rate immediately, instead of
> after a 5 second delay.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Thanks!
Maxime
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lect between DSP_A and DSP_B. Extend the driver to support this.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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Hi!
On Thu, Oct 15, 2020 at 06:47:40PM +0300, Alexander Kochetkov wrote:
> DMA-based transfer will be enabled if data length is larger than FIFO size
> (64 bytes for A64). This greatly reduce number of interrupts for
> transferring data.
>
> For smaller data size PIO mode will be used. In PIO
Hi,
On Sun, Oct 18, 2020 at 03:28:10PM +0800, Dinghao Liu wrote:
> When clk_hw_register_fixed_rate_with_accuracy() fails,
> clk_data should be freed. It's the same for the subsequent
> two error paths, but we should also unregister the already
> registered clocks in them.
>
> Signed-off-by:
Hi,
On Fri, Oct 16, 2020 at 11:38:26AM +0300, Alexander Kochetkov wrote:
> If SPI is used for periodic polling any sensor, significant delays
> sometimes appear. Switching on module clocks during resume lead to delays.
> Enabling autosuspend mode causes the controller to not suspend between
> SPI
On Thu, Oct 15, 2020 at 01:15:37PM +0300, Felipe Balbi wrote:
> Serge Semin writes:
>
> > On Wed, Oct 14, 2020 at 05:09:37PM +0300, Felipe Balbi wrote:
> >>
> >> Hi Serge,
> >>
> >> Serge Semin writes:
> >> > In accordance with the DWC USB3 bindings the corresponding node name is
> >> >
On Tue, Oct 13, 2020 at 11:27:33PM +0200, Jernej Škrabec wrote:
> Dne petek, 09. oktober 2020 ob 09:36:51 CEST je Maxime Ripard napisal(a):
> > On Thu, Oct 08, 2020 at 10:00:06PM +0200, Clément Péron wrote:
> > > Hi Maxime,
> > >
> > > Adding linux-sunxi a
On Sun, Oct 11, 2020 at 11:15:14PM +0200, Clément Péron wrote:
> make dtbs_check warm about unknown address/size-cells property in the
> pinetab device-tree.
>
> This is because these information are not necessary.
>
> Drop them.
>
> Signed-off-by: Clément Péron
Queued as a fix for 5.10
On Thu, Oct 08, 2020 at 07:40:44PM +0200, Michal Suchánek wrote:
> On Thu, Oct 08, 2020 at 07:14:54PM +0200, Maxime Ripard wrote:
> > On Thu, Oct 08, 2020 at 06:02:19PM +0200, Michal Suchánek wrote:
> > > On Thu, Oct 08, 2020 at 05:13:15PM +0200, Maxime Ripard
On Thu, Oct 08, 2020 at 08:40:06PM +0200, Michal Suchanek wrote:
> There are two models of Orange Pi zero which are confusingly marketed
> under the same name. Old model comes without a flash memory and current
> model does have a flash memory. Add bindings for each model.
>
> Signed-off-by:
On Sun, Oct 11, 2020 at 10:22:11PM +0200, Clément Péron wrote:
> As slots and slot_width can be set manually using set_tdm().
> These values are then kept in sun4i_i2s struct.
> So we need to check if these values are set or not.
>
> This is not done actually and will trigger a bug.
> For
On Tue, Oct 06, 2020 at 12:03:14AM -0500, Samuel Holland wrote:
> On 10/5/20 7:13 AM, Maxime Ripard wrote:
> > On Sat, Oct 03, 2020 at 04:19:38PM +0200, Clément Péron wrote:
> >> As slots and slot_width can be set manually using set_tdm().
> >> These values are th
Hi,
On Mon, Oct 05, 2020 at 03:23:12PM +0200, Clément Péron wrote:
> On Mon, 5 Oct 2020 at 14:13, Maxime Ripard wrote:
> >
> > On Sat, Oct 03, 2020 at 04:19:38PM +0200, Clément Péron wrote:
> > > As slots and slot_width can be set manually using set_tdm().
> >
Hi!
On Sun, Oct 11, 2020 at 11:22:37PM +0200, Clément Péron wrote:
> Beelink GS1 LED trigger a warning when running dtbs_check.
>
> Update the node with a valid pattern property.
>
> Also add the function and the color of the LED and drop the
> label which is deprecated.
>
> Signed-off-by:
On Mon, Oct 05, 2020 at 11:51:08PM -0500, Samuel Holland wrote:
> On 10/5/20 7:04 AM, Maxime Ripard wrote:
> > Hi,
> >
> > On Wed, Sep 30, 2020 at 09:11:46PM -0500, Samuel Holland wrote:
> >> The AIF clock control register has the same layout for all three AIFs.
&g
Hi!
On Sun, Oct 11, 2020 at 11:15:42PM +0200, Clément Péron wrote:
> make dtbs_check report a warning because the documentation
> for the A64 codec compatible is missing.
>
> The A64 codec compatible is actually a simple fallback to the A33.
>
> Reflect this in the dt-bindings Documentation.
>
On Thu, Oct 08, 2020 at 10:00:06PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> Adding linux-sunxi and Jernej Skrabec to this discussion.
>
> On Thu, 8 Oct 2020 at 17:10, Maxime Ripard wrote:
> >
> > Hi Clément,
> >
> > On Mon, Oct 05, 2020 at 08:47:19PM +
On Thu, Oct 08, 2020 at 06:02:19PM +0200, Michal Suchánek wrote:
> On Thu, Oct 08, 2020 at 05:13:15PM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Tue, Sep 29, 2020 at 10:30:25AM +0200, Michal Suchanek wrote:
> > > The flash is present on all new boards a
Hi,
On Tue, Sep 29, 2020 at 10:30:25AM +0200, Michal Suchanek wrote:
> The flash is present on all new boards and users went out of their way
> to add it on the old ones.
>
> Enabling it makes a more reasonable default.
>
> Signed-off-by: Michal Suchanek
> ---
>
Hi Clément,
On Mon, Oct 05, 2020 at 08:47:19PM +0200, Clément Péron wrote:
> On Mon, 5 Oct 2020 at 11:21, Maxime Ripard wrote:
> >
> > Hi Clément,
> >
> > On Sat, Oct 03, 2020 at 11:20:01AM +0200, Clément Péron wrote:
> > > Sunxi MMC driver can't distingui
Hi Stephen,
On Tue, Oct 06, 2020 at 02:56:37PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the sunxi tree got a conflict in:
>
> arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>
> between commit:
>
> 0dea1794f3b4 ("arm64: allwinner: A100: add the basical
On Mon, Oct 05, 2020 at 11:43:51PM -0500, Samuel Holland wrote:
> On 10/5/20 7:01 AM, Maxime Ripard wrote:
> > On Wed, Sep 30, 2020 at 09:11:43PM -0500, Samuel Holland wrote:
> >> The codec's clock input is shared among all AIFs, and shared with other
> >> audio-
On Mon, Oct 05, 2020 at 11:29:51PM -0500, Samuel Holland wrote:
>
> On 10/5/20 6:30 AM, Maxime Ripard wrote:
> > On Wed, Sep 30, 2020 at 09:11:34PM -0500, Samuel Holland wrote:
> > > When using the I2S, LEFT_J, or RIGHT_J format, the hardware supports
> > > indep
On Wed, Sep 16, 2020 at 06:57:05PM +0200, Maxime Ripard wrote:
> On Mon, Sep 14, 2020 at 07:14:11PM +0900, Hoegeun Kwon wrote:
> > Hi Maxime,
> >
> > On 9/8/20 9:00 PM, Maxime Ripard wrote:
> > > Hi Hoegeun,
> > >
> > > On Mon, Sep 07, 2020 at 08:
Hi Dave,
On Fri, Oct 02, 2020 at 04:57:05PM +0100, Dave Stevenson wrote:
> Hi Maxime
>
> On Fri, 2 Oct 2020 at 16:19, Maxime Ripard wrote:
> >
> > Hi Tim,
> >
> > On Thu, Oct 01, 2020 at 11:15:46AM +0100, Tim Gover wrote:
> > > hdmi_enable_4k
)
> and set_fmt() callback definition.
>
> Signed-off-by: Clément Péron
Acked-by: Maxime Ripard
Maxime
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On Sat, Oct 03, 2020 at 04:19:39PM +0200, Clément Péron wrote:
> We are actually using a complex formula to just return a bunch of
> simple values. Also this formula is wrong for sun4i when calling
> get_wss() the function return 4 instead of 3.
>
> Replace this with a simpler switch case.
>
>
On Sat, Oct 03, 2020 at 04:19:38PM +0200, Clément Péron wrote:
> As slots and slot_width can be set manually using set_tdm().
> These values are then kept in sun4i_i2s struct.
> So we need to check if these values are setted or not
> in the struct.
>
> Avoid to check for this logic in
On Wed, Sep 30, 2020 at 09:11:47PM -0500, Samuel Holland wrote:
> This adds support for AIF2, which is stereo and has full clocking
> capability, making it very similar to AIF1.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
> +
> + regmap_update_bits(scodec->regmap, reg,
> +BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD),
> +value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
I guess it would be more readable without the intermediate variable to
store the register.
With that fixed,
Acked-by: Maxime Ripard
Maxime
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> formats.
>
> Since this codec is connected to the CPU via a DAI, not directly, we do
> not care if the CPU DAI is using 3-byte or 4-byte formats, so we can
> support them both.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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ck the exact divider, not just the closest divider.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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On Wed, Sep 30, 2020 at 09:11:43PM -0500, Samuel Holland wrote:
> The codec's clock input is shared among all AIFs, and shared with other
> audio-related hardware in the SoC, including I2S and SPDIF controllers.
> To ensure sample rates selected by userspace or by codec2codec DAI links
> are
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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on.
>
> Since the sample rate is tied to active AIF paths, disabling pmdown_time
> allows switching to the optimal sample rate immediately, instead of
> after a 5 second delay.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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frequencies divided by any available divisor.
>
> This commit enables support for those sample rates. It also stops
> advertising support for a 64 kHz sample rate, which is not supported.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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; to enforce symmetry for these parameters, so starting a new substream
> will not break an existing substream.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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Holland
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>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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e_2 (instead of ilog2, which rounds down).
>
> Since the rounded divisor is also needed for setting the SYSCLK/BCLK
> divisor, return the order base 2 instead of fully calculating the
> hardware register encoding.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxi
; in another driver (which, incedentally, has patches pending to remove
> that limitation).
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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On Wed, Sep 30, 2020 at 09:11:34PM -0500, Samuel Holland wrote:
> When using the I2S, LEFT_J, or RIGHT_J format, the hardware supports
> independent BCLK and LRCK inversion control. When using DSP_A or DSP_B,
> LRCK inversion is not supported. The register bit is repurposed to
> select between
; the format field before the inversion fields.
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Maxime
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ENMASK(5, 4)
> #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASKGENMASK(3, 2)
>
> +enum {
> + AIF1,
> + NAIFS
> +};
> +
It's a bit of a nitpick, but we should have less generic names for the
enums here, maybe prefix it with sun8i_codec like the rest of the driver?
Once fixed,
Acked-by: Maxime Ripard
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