[PATCH] dmaengine: qcom: bam_dma: Fix completed descriptors count
One space is left unused in circular FIFO to differentiate
'full' and 'empty' cases. So take that in to account while
counting for the descriptors completed.
Fixes the issue reported here,
https://lkml.org/lkml/2019/6/18/669
Cc: sta...@vger.kernel.org
Reported-by: Srinivas Kandagatla
Signed-off-by: Sricharan R
---
drivers/dma/qcom/bam_dma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 4b43844..8e90a40 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -799,6 +799,9 @@ static u32 process_channel_irqs(struct bam_device *bdev)
/* Number of bytes available to read */
avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
+ if (offset < bchan->head)
+ avail--;
+
list_for_each_entry_safe(async_desc, tmp,
>desc_list, desc_node) {
/* Not enough data to read */
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/20/2019 9:02 PM, Christian Lamparter wrote:
> Hello Sricharan,
>
> On Wednesday, June 19, 2019 4:42:11 PM CEST Sricharan R wrote:
>> On 6/15/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
>>>> Hi Christian,
>>>>
>>>> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
>>>>> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>>>>>> Hi Christian,
>>>>>>
>>>>>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>>>>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R
>>>>>>> wrote:
>>>>>>>>
>>>>>>>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>>>>>>>> CP01 evaluation board.
>>>>>>>>
>>>>>>>> Signed-off-by: Sricharan R
>>>>>>>> Signed-off-by: Abhishek Sahu
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>>>>>>>
>>>>>>>> + clocks {
>>>>>>>> + sleep_clk: sleep_clk {
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + clock-frequency = <32000>;
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>> Recently-ish, we ran into an issue with the clock-frequency of the
>>>>>>> sleep_clk
>>>>>>> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
>>>>>>> From what I know, the external "32KHz" crystals have 32768 Hz, but the
>>>>>>> QSDK
>>>>>>> declares them at 32000 Hz. Since you probably have access to the BOM and
>>>>>>> datasheets. Can you please confirm what's the real clock frequency for
>>>>>>> the IPQ6018.
>>>>>>> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>>>>>>>
>>>>>>
>>>>>> What exactly is the issue that you faced ?
>>>>>> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as
>>>>>> well.
>>>>>
>>>>> We need just a confirmation.
>>>>>
>>>>> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
>>>>>
>>>>> | sleep_clk: sleep_clk {
>>>>> | compatible = "fixed-clock";
>>>>> | clock-frequency = <32768>;
>>>>> | #clock-cells = <0>;
>>>>> | };
>>>>>
>>>>> <https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/qcom-ipq4019.dtsi#L144>
>>>>>
>>>>> Which makes sense, because all previous Qualcomm Atheros MIPS and the
>>>>> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
>>>>>
>>>>> For example: The AR9344 derives the clock from the 25MHz/40MHz external
>>>>> oscillator. This is explained in "8.16.9 Derived RTC Clock
>>>>> (DERIVED_RTC_CLK)".
>>>>> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
>>>>> depending whenever the external reference crystal has 40MHz or 25MHz.
>>>>> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
>>>>> in "10.19.11 Derived RTC Clock".
>>>>>
>>>>> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
>>>>> <http://lists.infradead.org/pipermail/openwrt-devel/2019-May/017131.html>
>>>>> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
>>>>> sleep clock."
>>>>>
>>>>> So this is pretty much "why there is an issue", it's confusing.
>>>>> Is possible can you please look if there are (fixed) divisors values
>>>>> listed in the documentation or the registers and bits that the values
>>>>> are stored in? Because then we could just calculate it.
>>>>>
>>>>
>>>> Really sorry for the confusion. So looking little more, SLEEP_CLK is
>>>> derived
>>
Re: [PATCH] dmaengine: qcom-bam: fix circular buffer handling
Hi Srini, On 6/18/2019 10:20 PM, Srinivas Kandagatla wrote: > > > On 18/06/2019 17:27, Sricharan R wrote: >> The Macro's expect that buffer size is power of 2. So we are infact >> passing the actual correct >> size ( MAX_DESCRIPTORS + 1 = 4096) > This will make the circular buffer macros happy but question is that do we > actually have that many descriptor buffers? > > This is what is in the driver: > > #define BAM_DESC_FIFO_SIZE SZ_32K > #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1) > #define BAM_FIFO_SIZE (SZ_32K - 8) > > Wouldn't having MAX_DESCRIPTORS + 1 = 4096 lead to overflow the actual > descriptor memory size of (SZ_32K - 8) ? > Right, but the CIRC_SPACE macro assumes there is 1 space less than the actual size. That said, agree there is an issue on the boundary. I will also do some testing tomorrow on this and get back. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/15/2019 2:11 AM, Christian Lamparter wrote:
> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
>>> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>>>> Hi Christian,
>>>>
>>>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R
>>>>> wrote:
>>>>>>
>>>>>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>>>>>> CP01 evaluation board.
>>>>>>
>>>>>> Signed-off-by: Sricharan R
>>>>>> Signed-off-by: Abhishek Sahu
>>>>>> --- /dev/null
>>>>>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>>>>>
>>>>>> + clocks {
>>>>>> + sleep_clk: sleep_clk {
>>>>>> + compatible = "fixed-clock";
>>>>>> + clock-frequency = <32000>;
>>>>>> + #clock-cells = <0>;
>>>>>> + };
>>>>>> +
>>>>> Recently-ish, we ran into an issue with the clock-frequency of the
>>>>> sleep_clk
>>>>> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
>>>>> From what I know, the external "32KHz" crystals have 32768 Hz, but the
>>>>> QSDK
>>>>> declares them at 32000 Hz. Since you probably have access to the BOM and
>>>>> datasheets. Can you please confirm what's the real clock frequency for
>>>>> the IPQ6018.
>>>>> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>>>>>
>>>>
>>>> What exactly is the issue that you faced ?
>>>> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
>>>
>>> We need just a confirmation.
>>>
>>> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
>>>
>>> | sleep_clk: sleep_clk {
>>> | compatible = "fixed-clock";
>>> | clock-frequency = <32768>;
>>> | #clock-cells = <0>;
>>> | };
>>>
>>> <https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/qcom-ipq4019.dtsi#L144>
>>>
>>> Which makes sense, because all previous Qualcomm Atheros MIPS and the
>>> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
>>>
>>> For example: The AR9344 derives the clock from the 25MHz/40MHz external
>>> oscillator. This is explained in "8.16.9 Derived RTC Clock
>>> (DERIVED_RTC_CLK)".
>>> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
>>> depending whenever the external reference crystal has 40MHz or 25MHz.
>>> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
>>> in "10.19.11 Derived RTC Clock".
>>>
>>> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
>>> <http://lists.infradead.org/pipermail/openwrt-devel/2019-May/017131.html>
>>> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
>>> sleep clock."
>>>
>>> So this is pretty much "why there is an issue", it's confusing.
>>> Is possible can you please look if there are (fixed) divisors values
>>> listed in the documentation or the registers and bits that the values
>>> are stored in? Because then we could just calculate it.
>>>
>>
>> Really sorry for the confusion. So looking little more, SLEEP_CLK is derived
>> from an external 38.4MHZ crystal, it is 32.768 KHZ.
> That's really valuable information to have. Thank you!
>
>> Somehow the clk freq plan etc seems to mention them only as .032 MHZ and
>> misses
>> out. That means i will correct the patch for 32768 and probably the
>> ipq8074.dtsi as well
>
> Ok, there's one more issue that Paul found (at least with the IPQ4019),
> https://patchwork.ozlabs.org/patch/1099482
>
> it seems that the "sleep_clk" node in the qcom-ipq4019.dtsi is not used by
> the gcc-ipq4019.c clk driver. this causes both wifi rtc_clks and the usb sleep
> clks to dangle in the /sys/kernel/debug/clk/clk_summary (from a RT-AC58U)
>
>clock enable_cnt p
Re: [PATCH] dmaengine: qcom-bam: fix circular buffer handling
On 6/18/2019 8:42 PM, Srinivas Kandagatla wrote: > > > On 18/06/2019 15:56, Sricharan R wrote: >> So MAX_DESCRIPTORS is used in driver for masking head/tail pointers. >> That's why we have to pass MAX_DESCRIPTORS + 1 so that it works >> when the Macros does a size - 1 > Isn't that incorrect to do that, pretending to have more descriptors than we > actually have? > The Macro's expect that buffer size is power of 2. So we are infact passing the actual correct size ( MAX_DESCRIPTORS + 1 = 4096) Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] dmaengine: qcom-bam: fix circular buffer handling
Hi Srini,
On 6/18/2019 8:20 PM, Srinivas Kandagatla wrote:
> Hi Sricharan,
>
> On 18/06/2019 08:13, Sricharan R wrote:
>> Hi Srini,
>>
>> On 6/14/2019 7:50 PM, Srinivas Kandagatla wrote:
>>> For some reason arguments to most of the circular buffers
>>> macros are used in reverse, tail is used for head and vice versa.
>>>
>>> This leads to bam thinking that there is an extra descriptor at the
>>> end and leading to retransmitting descriptor which was not scheduled
>>> by any driver. This happens after MAX_DESCRIPTORS (4096) are scheduled
>>> and done, so most of the drivers would not notice this, unless they are
>>> heavily using bam dma. Originally found this issue while testing
>>> SoundWire over SlimBus on DB845c which uses DMA very heavily for
>>> read/writes.
>>>
>>> Signed-off-by: Srinivas Kandagatla
>>> ---
>>> drivers/dma/qcom/bam_dma.c | 9 -
>>> 1 file changed, 4 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
>>> index cb860cb53c27..43d7b0a9713a 100644
>>> --- a/drivers/dma/qcom/bam_dma.c
>>> +++ b/drivers/dma/qcom/bam_dma.c
>>> @@ -350,8 +350,8 @@ static const struct reg_offset_data bam_v1_7_reg_info[]
>>> = {
>>> #define BAM_DESC_FIFO_SIZE SZ_32K
>>> #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw)
>>> - 1)
>>> #define BAM_FIFO_SIZE (SZ_32K - 8)
>>> -#define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\
>>> - MAX_DESCRIPTORS + 1) == 0)
>>> +#define IS_BUSY(chan) (CIRC_SPACE(bchan->head, bchan->tail,\
>>> + MAX_DESCRIPTORS) == 0)
>>> struct bam_chan {
>>> struct virt_dma_chan vc;
>>> @@ -806,7 +806,7 @@ static u32 process_channel_irqs(struct bam_device *bdev)
>>> offset /= sizeof(struct bam_desc_hw);
>>> /* Number of bytes available to read */
>>> - avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
>>> + avail = CIRC_CNT(bchan->head, offset, MAX_DESCRIPTORS);
>>>
>> one question, so MAX_DESCRIPTORS is already a mask,
>> #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct
>> bam_desc_hw) - 1)
>>
>> CIRC_CNT/SPACE macros also does a size - 1, so would it not be a problem
>> if we
>> just pass MAX_DESCRIPTORS ?
>
> Thanks for looking at this,
> TBH, usage of CIRC_* macros is only valid for power-of-2 buffers,
> In bam case MAX_DESCRIPTORS is 4095.
> Am really not sure why 8 bytes have been removed from fifo data buffer size.
> So basically usage of these macros is incorrect in bam case, this need to be
> fixed properly.
>
> Do you agree?
>
So MAX_DESCRIPTORS is used in driver for masking head/tail pointers.
That's why we have to pass MAX_DESCRIPTORS + 1 so that it works
when the Macros does a size - 1
Regards,
Sricharan
> Vinod, can you hold off with this patch, I will try to find some time this
> week to cook up a better patch removing the usage of these macros.
>
>
>
> thanks,
> srini
>
>>
>> Regards,
>> Sricharan
>>
>>> list_for_each_entry_safe(async_desc, tmp,
>>> >desc_list, desc_node) {
>>> @@ -997,8 +997,7 @@ static void bam_start_dma(struct bam_chan *bchan)
>>> bam_apply_new_config(bchan, async_desc->dir);
>>> desc = async_desc->curr_desc;
>>> - avail = CIRC_SPACE(bchan->tail, bchan->head,
>>> - MAX_DESCRIPTORS + 1);
>>> + avail = CIRC_SPACE(bchan->head, bchan->tail, MAX_DESCRIPTORS);
>>> if (async_desc->num_desc > avail)
>>> async_desc->xfer_len = avail;
>>>
>>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] dmaengine: qcom-bam: fix circular buffer handling
Hi Srini,
On 6/14/2019 7:50 PM, Srinivas Kandagatla wrote:
> For some reason arguments to most of the circular buffers
> macros are used in reverse, tail is used for head and vice versa.
>
> This leads to bam thinking that there is an extra descriptor at the
> end and leading to retransmitting descriptor which was not scheduled
> by any driver. This happens after MAX_DESCRIPTORS (4096) are scheduled
> and done, so most of the drivers would not notice this, unless they are
> heavily using bam dma. Originally found this issue while testing
> SoundWire over SlimBus on DB845c which uses DMA very heavily for
> read/writes.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/dma/qcom/bam_dma.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> index cb860cb53c27..43d7b0a9713a 100644
> --- a/drivers/dma/qcom/bam_dma.c
> +++ b/drivers/dma/qcom/bam_dma.c
> @@ -350,8 +350,8 @@ static const struct reg_offset_data bam_v1_7_reg_info[] =
> {
> #define BAM_DESC_FIFO_SIZE SZ_32K
> #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
> #define BAM_FIFO_SIZE(SZ_32K - 8)
> -#define IS_BUSY(chan)(CIRC_SPACE(bchan->tail, bchan->head,\
> - MAX_DESCRIPTORS + 1) == 0)
> +#define IS_BUSY(chan)(CIRC_SPACE(bchan->head, bchan->tail,\
> + MAX_DESCRIPTORS) == 0)
>
> struct bam_chan {
> struct virt_dma_chan vc;
> @@ -806,7 +806,7 @@ static u32 process_channel_irqs(struct bam_device *bdev)
> offset /= sizeof(struct bam_desc_hw);
>
> /* Number of bytes available to read */
> - avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
> + avail = CIRC_CNT(bchan->head, offset, MAX_DESCRIPTORS);
>
one question, so MAX_DESCRIPTORS is already a mask,
#define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) -
1)
CIRC_CNT/SPACE macros also does a size - 1, so would it not be a problem if we
just pass MAX_DESCRIPTORS ?
Regards,
Sricharan
> list_for_each_entry_safe(async_desc, tmp,
>>desc_list, desc_node) {
> @@ -997,8 +997,7 @@ static void bam_start_dma(struct bam_chan *bchan)
> bam_apply_new_config(bchan, async_desc->dir);
>
> desc = async_desc->curr_desc;
> - avail = CIRC_SPACE(bchan->tail, bchan->head,
> -MAX_DESCRIPTORS + 1);
> + avail = CIRC_SPACE(bchan->head, bchan->tail, MAX_DESCRIPTORS);
>
> if (async_desc->num_desc > avail)
> async_desc->xfer_len = avail;
>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>>>
>>>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>>>> CP01 evaluation board.
>>>>
>>>> Signed-off-by: Sricharan R
>>>> Signed-off-by: Abhishek Sahu
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>>>
>>>> + clocks {
>>>> + sleep_clk: sleep_clk {
>>>> + compatible = "fixed-clock";
>>>> + clock-frequency = <32000>;
>>>> + #clock-cells = <0>;
>>>> + };
>>>> +
>>> Recently-ish, we ran into an issue with the clock-frequency of the sleep_clk
>>> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
>>> From what I know, the external "32KHz" crystals have 32768 Hz, but the QSDK
>>> declares them at 32000 Hz. Since you probably have access to the BOM and
>>> datasheets. Can you please confirm what's the real clock frequency for
>>> the IPQ6018.
>>> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>>>
>>
>> What exactly is the issue that you faced ?
>> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
>
> We need just a confirmation.
>
> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
>
> | sleep_clk: sleep_clk {
> | compatible = "fixed-clock";
> | clock-frequency = <32768>;
> | #clock-cells = <0>;
> | };
>
> <https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/qcom-ipq4019.dtsi#L144>
>
> Which makes sense, because all previous Qualcomm Atheros MIPS and the
> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
>
> For example: The AR9344 derives the clock from the 25MHz/40MHz external
> oscillator. This is explained in "8.16.9 Derived RTC Clock (DERIVED_RTC_CLK)".
> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
> depending whenever the external reference crystal has 40MHz or 25MHz.
> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
> in "10.19.11 Derived RTC Clock".
>
> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
> <http://lists.infradead.org/pipermail/openwrt-devel/2019-May/017131.html>
> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
> sleep clock."
>
> So this is pretty much "why there is an issue", it's confusing.
> Is possible can you please look if there are (fixed) divisors values
> listed in the documentation or the registers and bits that the values
> are stored in? Because then we could just calculate it.
>
Really sorry for the confusion. So looking little more, SLEEP_CLK is derived
from an external 38.4MHZ crystal, it is 32.768 KHZ. Somehow the
clk freq plan etc seems to mention them only as .032 MHZ and misses
out. That means i will correct the patch for 32768 and probably the
ipq8074.dtsi as well
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Bjorn,
On 6/8/2019 9:18 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:16 PDT 2019, Sricharan R wrote:
>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>
> Please fix the order of these (or add a Co-developed-by).
>
ok
>> ---
>> arch/arm64/boot/dts/qcom/Makefile| 1 +
>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
>> +++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 21d548f..ac22dbb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -2,6 +2,7 @@
>> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
>
> Sort order.
>
ok
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> new file mode 100644
>> index 000..ac7cb22
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> @@ -0,0 +1,35 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 CP01 board device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq6018.dtsi"
>> +
>> +/ {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x2>;
>
> This is a count, write it in base 10..
>
ok
>> +model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
>> +compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
>> +interrupt-parent = <>;
>
> Changing #address-cells, #size-cells and interrupt-parent will break the
> dtsi, so I think you should specify them there.
>
ok, will move it to the dtsi.
>> +};
>> +
>> + {
>
> Please sort your nodes based on address, then node name, then label.
>
ok
>> +uart_pins: uart_pins {
>> +mux {
>> +pins = "gpio44", "gpio45";
>> +function = "blsp2_uart";
>> +drive-strength = <8>;
>> +bias-pull-down;
>> +};
>> +};
>> +};
>> +
>> +_uart3 {
>> +pinctrl-0 = <_pins>;
>> +pinctrl-names = "default";
>> +status = "ok";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> new file mode 100644
>> index 000..79cccdd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -0,0 +1,231 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ6018";
>> +compatible = "qcom,ipq6018";
>
> No need for model and compatible in the dtsi, these should always be
> specified by the including file.
>
ok, will move it to the dts.
>> +
>> +chosen {
>> +bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
>
> Do you really need console? Can't you use stdout-path?
>
ok, will change.
> And there's no need to specify init=/init.
>
ok.
>> +bootargs-append = " swiotlb=1 clk_ignore_unused";
>
> I'm hoping that you will work on removing the need for
> clk_ignore_unused.
>
hmm, should not be required even now. will remove that.
>> +};
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +tz:tz@4850 {
>
> Space after :
>
ok
Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
Hi Bjorn,
On 6/8/2019 9:02 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> This patch adds support for the global clock controller found on
>> the ipq6018 based devices.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: anusha
>> Signed-off-by: Abhishek Sahu
>
> Please fix your s-o-b chain, as described in my reply to 1/8..
>
ok.
>> ---
>> drivers/clk/qcom/Kconfig |9 +
>> drivers/clk/qcom/Makefile |1 +
>> drivers/clk/qcom/gcc-ipq6018.c | 5267
>>
>> 3 files changed, 5277 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index e1ff83c..e5fb091 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -120,6 +120,15 @@ config IPQ_GCC_8074
>>i2c, USB, SD/eMMC, etc. Select this for the root clock
>>of ipq8074.
>>
>> +config IPQ_GCC_6018
>
> Please maintain sort order.
>
ok.
>> +tristate "IPQ6018 Global Clock Controller"
>> +depends on COMMON_CLK_QCOM
>> +help
>> + Support for global clock controller on ipq6018 devices.
>> + Say Y if you want to use peripheral devices such as UART, SPI,
>> + i2c, USB, SD/eMMC, etc. Select this for the root clock
>> + of ipq6018.
>> +
>> config MSM_GCC_8660
>> tristate "MSM8660 Global Clock Controller"
>> help
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index f0768fb..025137d 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
>> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> +obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>
> Ditto.
>
ok.
>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> [..]
>> +static int gcc_ipq6018_probe(struct platform_device *pdev)
>> +{
>> +return qcom_cc_probe(pdev, _ipq6018_desc);
>> +}
>> +
>> +static int gcc_ipq6018_remove(struct platform_device *pdev)
>> +{
>> +return 0;
>
> Just omit .remove from the gcc_ipq6018_driver instead of providing a
> dummy function.
>
ok.
>> +}
>> +
>> +static struct platform_driver gcc_ipq6018_driver = {
>> +.probe = gcc_ipq6018_probe,
>> +.remove = gcc_ipq6018_remove,
>> +.driver = {
>> +.name = "qcom,gcc-ipq6018",
>> +.owner = THIS_MODULE,
>
> Don't specify .owner in platform drivers.
>
ok.
> [..]
>> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:gcc-ipq6018");
>
> This modalias won't be used.
>
ok. But it looks to be there in other clk drivers as well.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings
On 6/8/2019 8:57 AM, Bjorn Andersson wrote: > On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote: > >> Signed-off-by: Sricharan R >> Signed-off-by: speriaka >> --- >> Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml >> b/Documentation/devicetree/bindings/arm/qcom.yaml >> index f6316ab..7b19028 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml >> @@ -36,6 +36,7 @@ description: | >> mdm9615 >> ipq8074 >> sdm845 >> +ipq6018 > > It would be nice if these lists where sorted, but as that's not the > case, please sort it wrt the other ipq at least. > ok. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver
Hi Bjorn,
On 6/8/2019 8:56 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> Add initial pinctrl driver to support pin configuration with
>> pinctrl framework for ipq6018.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Rajkumar Ayyasamy
>> Signed-off-by: speriaka
>
Thanks for the review !!
> These should start with the author, then followed by each person that
> handled the patch on its way to the list - so your name should probably
> be last. If you have more than one author add Co-developed-by, in
> addition to the Signed-off-by.
>
> And please spell our speriaka's first and last name.
>
ok, will fix it.
> [..]
>> diff --git
>> a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt
>> b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt
> [..]
>> +- #gpio-cells:
>> +Usage: required
>> +Value type:
>> +Definition: must be 2. Specifying the pin number and flags, as defined
>> +in
>
> You're missing the required "gpio-ranges" property.
>
ok, will add.
>> +
> [..]
>> +- function:
>> +Usage: required
>> +Value type:
>> +Definition: Specify the alternative function to be configured for the
>> +specified pins. Functions are only valid for gpio pins.
>> +Valid values are:
>> +adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
>
> Please indent these.
>
ok.
> [..]
>
> The rest should be in a separate patch from the binding.
>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> [..]
>> +enum ipq6018_functions {
> [..]
>> +msm_mux_NA,
>
> I like when these are sorted, and if you make the last entry msm_mux__
> the msm_pingroup array becomes easier to read.
>
ok.
>> +};
> [..]
>> +static const struct msm_function ipq6018_functions[] = {
> [..]
>> +FUNCTION(gcc_tlmm),
>
> As above, please sort these.
>
ok.
>> +};
>> +
>> +static const struct msm_pingroup ipq6018_groups[] = {
>> +PINGROUP(0, qpic_pad, wci20, qdss_traceclk_b, NA, burn0, NA, NA, NA,
>> + NA),
>
> Please ignore the 80-char and skip the line breaks.
>
ok.
>> +PINGROUP(1, qpic_pad, mac12, qdss_tracectl_b, NA, burn1, NA, NA, NA,
>> + NA),
>> +PINGROUP(2, qpic_pad, wci20, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
>> +PINGROUP(3, qpic_pad, mac01, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
>> +PINGROUP(4, qpic_pad, mac01, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
>> +PINGROUP(5, qpic_pad4, mac21, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
>
> Is there a reason to keep qpic_padN as separate functions from qpic_pad?
>
Hmm, the auto-gen scripts needs to be fixed. Will correct it.
> [..]
>> +static struct platform_driver ipq6018_pinctrl_driver = {
>> +.driver = {
>> +.name = "ipq6018-pinctrl",
>> +.owner = THIS_MODULE,
>
> .owner is populated automagically by platform_driver_register, so please
> omit this.
>
ok, missed it. will fix.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> + clocks {
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> +
> Recently-ish, we ran into an issue with the clock-frequency of the sleep_clk
> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
> From what I know, the external "32KHz" crystals have 32768 Hz, but the QSDK
> declares them at 32000 Hz. Since you probably have access to the BOM and
> datasheets. Can you please confirm what's the real clock frequency for
> the IPQ6018.
> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>
What exactly is the issue that you faced ?
Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Sudeep,
On 6/5/2019 11:04 PM, Sudeep Holla wrote:
> On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> ---
>> arch/arm64/boot/dts/qcom/Makefile| 1 +
>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
>> +++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>
> [...]
>
>> +
>> +CPU3: cpu@3 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53";
>> +enable-method = "psci";
>> +reg = <0x3>;
>> +next-level-cache = <_0>;
>> +};
>> +
>> +L2_0: l2-cache {
>> +compatible = "cache";
>> +cache-level = <0x2>;
>> +};
>> +};
>> +
>> +pmuv8: pmu {
>> +compatible = "arm,armv8-pmuv3";
>
> We know these are Cortex-A53s, why not update these accordingly ?
>
Ok, will change this.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Marc,
On 6/5/2019 10:56 PM, Marc Zyngier wrote:
> On 05/06/2019 18:16, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> ---
>> arch/arm64/boot/dts/qcom/Makefile| 1 +
>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
>> +++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 21d548f..ac22dbb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -2,6 +2,7 @@
>> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> new file mode 100644
>> index 000..ac7cb22
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> @@ -0,0 +1,35 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 CP01 board device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq6018.dtsi"
>> +
>> +/ {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x2>;
>> +model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
>> +compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
>> +interrupt-parent = <>;
>> +};
>> +
>> + {
>> +uart_pins: uart_pins {
>> +mux {
>> +pins = "gpio44", "gpio45";
>> +function = "blsp2_uart";
>> +drive-strength = <8>;
>> +bias-pull-down;
>> +};
>> +};
>> +};
>> +
>> +_uart3 {
>> +pinctrl-0 = <_pins>;
>> +pinctrl-names = "default";
>> +status = "ok";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> new file mode 100644
>> index 000..79cccdd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -0,0 +1,231 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ6018";
>> +compatible = "qcom,ipq6018";
>> +
>> +chosen {
>> +bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
>> +bootargs-append = " swiotlb=1 clk_ignore_unused";
>> +};
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +tz:tz@4850 {
>> +no-map;
>> +reg = <0x0 0x4850 0x0 0x0020>;
>> +};
>> +};
>> +
>> +soc: soc {
>> +#address-cells = <0x1>;
>> +#size-cells = <0x1>;
>> +ranges = <0 0 0 0x>;
>> +dma-ranges;
>> +compatible = "simple-bus";
>> +
>> +intc: interrupt-controller@b00 {
>> +compatible = "qcom,msm-qgic2";
>> +interrupt-controller;
>> +#interrupt-cells = <0x3>;
>> +reg = <0xb00 0x1000>, <0xb002000 0x1000>;
>
> Where are the rest of the GICv2 MMIO regions, such as GICV and GICH? And
> the maintenance interrupt?
>
GICH - 0xB001000 -- 0xB002000
GICV - 0xB004000 -- 0xB005000
Will add this and the PPI as well.
Regards,
Sricharan
>> +};
>> +
>> +timer {
>> +compatible = "arm,armv8-timer";
>> +interrupts = > IRQ_TYPE_LEVEL_LOW)>,
>> + > IRQ_TYPE_LEVEL_LOW)>,
>> + > IRQ_TYPE_LEVEL_LOW)>,
>> + > IRQ_TYPE_LEVEL_LOW)>;
>
> The fact that you expose the EL2 timer interrupt would tend to confirm
> the idea that this system supports virtualization... Hence my questions
> above.
>
> Thanks,
>
> M.
>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
3 files changed, 5277 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83c..e5fb091 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -120,6 +120,15 @@ config IPQ_GCC_8074
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq8074.
+config IPQ_GCC_6018
+ tristate "IPQ6018 Global Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for global clock controller on ipq6018 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc. Select this for the root clock
+ of ipq6018.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb..025137d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
+obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
new file mode 100644
index 000..9f4552b
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -0,0 +1,5267 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_BIAS_PLL,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_BIAS_PLL_NSS_NOC,
+ P_UNIPHY1_TX,
+ P_PCIE20_PHY0_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_GPLL6,
+ P_SLEEP_CLK,
+ P_UBI32_PLL,
+ P_NSS_CRYPTO_PLL,
+ P_PI_SLEEP,
+};
+
+static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ "xo",
+ "bias_pll_cc_clk",
+ "gpll0",
+ "gpll4",
+ "nss_crypto_pll",
+ "ubi32_pll",
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ "xo",
+ "bias_pll_nss_noc_clk",
+ "gpll0",
+ "gpll2",
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] =
{
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_t
[PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings
Signed-off-by: Sricharan R Signed-off-by: speriaka --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f6316ab..7b19028 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + ipq6018 The 'board' element must be one of the following strings: @@ -45,6 +46,7 @@ description: | mtp sbc hk01 + cp01-c1 The 'soc_version' and 'board_version' elements take the form of v. where the minor number may be omitted when it's zero, i.e. v1.0 is the same -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 6/6] arm64: defconfig: Enable qcom ipq6018 clock and pinctrl
These configs are required for booting kernel in qcom ipq6018 boards. Signed-off-by: Sricharan R --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4d58351..abf64ee 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -373,6 +373,7 @@ CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y @@ -646,6 +647,7 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_GCC_8074=y +CONFIG_IPQ_GCC_6018=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver
Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq6018. Signed-off-by: Sricharan R Signed-off-by: Rajkumar Ayyasamy Signed-off-by: speriaka --- .../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile |1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 4 files changed, 1380 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt new file mode 100644 index 000..5a3edb1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt @@ -0,0 +1,186 @@ +Qualcomm Technologies, Inc. IPQ6018 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +IPQ6018 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,ipq6018-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio121, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data, + qdsd_cmd, + qdsd_data0, + qdsd_data1, + qdsd_data2, + qdsd_data3 + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0, + atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en, + bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, + blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, + blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, + blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, + cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, + display_5v, dmic0_clk, dmic0_data, dsi_rst,
[PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231 +++
3 files changed, 267 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index 21d548f..ac22dbb 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_ARCH_QCOM)+= apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM)+= apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM)+= ipq8074-hk01.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8994-angler-rev-101.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
new file mode 100644
index 000..ac7cb22
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPQ6018 CP01 board device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq6018.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
+ compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
+ interrupt-parent = <>;
+};
+
+ {
+ uart_pins: uart_pins {
+ mux {
+ pins = "gpio44", "gpio45";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+};
+
+_uart3 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
new file mode 100644
index 000..79cccdd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPQ6018 SoC device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ6018";
+ compatible = "qcom,ipq6018";
+
+ chosen {
+ bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
+ bootargs-append = " swiotlb=1 clk_ignore_unused";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz:tz@4850 {
+ no-map;
+ reg = <0x0 0x4850 0x0 0x0020>;
+ };
+ };
+
+ soc: soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0 0 0 0x>;
+ dma-ranges;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@b00 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ reg = <0xb00 0x1000>, <0xb002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ timer@b12 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb12 0x1000>;
+ clock-frequency = <1920>;
+
+ frame@b12 {
+ frame-number = <0>;
+ interrupts = ,
+;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = ;
+
[PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller
Add the compatible strings and the include file for ipq6018 gcc clock controller. Signed-off-by: Sricharan R Signed-off-by: anusha Signed-off-by: Abhishek Sahu --- .../devicetree/bindings/clock/qcom,gcc.txt | 1 + include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 + 2 files changed, 406 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 8661c3c..40bb3de 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,gcc-ipq8064" "qcom,gcc-ipq4019" "qcom,gcc-ipq8074" + "qcom,gcc-ipq6018" "qcom,gcc-msm8660" "qcom,gcc-msm8916" "qcom,gcc-msm8960" diff --git a/include/dt-bindings/clock/qcom,gcc-ipq6018.h b/include/dt-bindings/clock/qcom,gcc-ipq6018.h new file mode 100644 index 000..b8aec10 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq6018.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H + +#define GPLL0 0 +#define UBI32_PLL 1 +#define GPLL6 2 +#define GPLL4 3 +#define PCNOC_BFDCD_CLK_SRC4 +#define GPLL2 5 +#define NSS_CRYPTO_PLL 6 +#define NSS_PPE_CLK_SRC7 +#define GCC_XO_CLK_SRC 8 +#define NSS_CE_CLK_SRC 9 +#define GCC_SLEEP_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define NSS_PORT5_RX_CLK_SRC 12 +#define NSS_PORT5_TX_CLK_SRC 13 +#define PCIE0_AXI_CLK_SRC 14 +#define USB0_MASTER_CLK_SRC15 +#define APSS_AHB_POSTDIV_CLK_SRC 16 +#define NSS_PORT1_RX_CLK_SRC 17 +#define NSS_PORT1_TX_CLK_SRC 18 +#define NSS_PORT2_RX_CLK_SRC 19 +#define NSS_PORT2_TX_CLK_SRC 20 +#define NSS_PORT3_RX_CLK_SRC 21 +#define NSS_PORT3_TX_CLK_SRC 22 +#define NSS_PORT4_RX_CLK_SRC 23 +#define NSS_PORT4_TX_CLK_SRC 24 +#define NSS_PORT5_RX_DIV_CLK_SRC 25 +#define NSS_PORT5_TX_DIV_CLK_SRC 26 +#define APSS_AXI_CLK_SRC 27 +#define NSS_CRYPTO_CLK_SRC 28 +#define NSS_PORT1_RX_DIV_CLK_SRC 29 +#define NSS_PORT1_TX_DIV_CLK_SRC 30 +#define NSS_PORT2_RX_DIV_CLK_SRC 31 +#define NSS_PORT2_TX_DIV_CLK_SRC 32 +#define NSS_PORT3_RX_DIV_CLK_SRC 33 +#define NSS_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_PORT4_RX_DIV_CLK_SRC 35 +#define NSS_PORT4_TX_DIV_CLK_SRC 36 +#define NSS_UBI0_CLK_SRC 37 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC38 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC39 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC40 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC41 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC42 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC43 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC44 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC45 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC46 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC47 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC48 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC49 +#define BLSP1_UART1_APPS_CLK_SRC 50 +#define BLSP1_UART2_APPS_CLK_SRC 51 +#define BLSP1_UART3_APPS_CLK_SRC 52 +#define BLSP1_UART4_APPS_CLK_SRC 53 +#define BLSP1_UART5_APPS_CLK_SRC 54 +#define BLSP1_UART6_APPS_CLK_SRC 55 +#define CRYPTO_CLK_SRC 56 +#define NSS_UBI0_DIV_CLK_SRC 57 +#define PCIE0_AUX_CLK_SRC 58 +#define PCIE0_PIPE_CLK_SRC 59 +#define SDCC1_APPS_CLK_SRC 60 +#define USB0_AUX_CLK_SRC 61 +#define USB0_MOCK_UTMI_CLK_SRC 62 +#define USB0_PIPE_CLK_SRC 63 +#define USB1_MOCK_UTMI_CLK_SRC 64 +#define GCC_APSS_AHB_CLK 65 +#define GCC_APSS_AXI_CLK 66 +#define GCC_BLSP1_AHB_CLK
[PATCH 0/6] Add minimal boot support for IPQ6018
The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq6018-cp01 board. Sricharan R (6): pinctrl: qcom: Add ipq6018 pinctrl driver dt-bindings: qcom: Add ipq6018 bindings clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: Add ipq6018 Global Clock Controller support arm64: dts: Add ipq6018 SoC and CP01 board support arm64: defconfig: Enable qcom ipq6018 clock and pinctrl Documentation/devicetree/bindings/arm/qcom.yaml|2 + .../devicetree/bindings/clock/qcom,gcc.txt |1 + arch/arm64/boot/dts/qcom/Makefile |1 + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 + arch/arm64/configs/defconfig |2 + drivers/clk/qcom/Kconfig |9 + drivers/clk/qcom/Makefile |1 + drivers/clk/qcom/gcc-ipq6018.c | 5267 drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile |1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 + include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 ++ 13 files changed, 7148 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq6018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 0/6] Add minimal boot support for IPQ6018
Sorry, Got sb...@codeaurora.org wrong. Will fix and repost Regards, Sricharan On 6/5/2019 10:45 PM, Sricharan R wrote: > The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, > Gateways and Access Points. > > This series adds minimal board boot support for ipq6018-cp01 > board. > > Sricharan R (6): > pinctrl: qcom: Add ipq6018 pinctrl driver > dt-bindings: qcom: Add ipq6018 bindings > clk: qcom: Add DT bindings for ipq6018 gcc clock controller > clk: qcom: Add ipq6018 Global Clock Controller support > arm64: dts: Add ipq6018 SoC and CP01 board support > arm64: defconfig: Enable qcom ipq6018 clock and pinctrl > > Documentation/devicetree/bindings/arm/qcom.yaml|2 + > .../devicetree/bindings/clock/qcom,gcc.txt |1 + > arch/arm64/boot/dts/qcom/Makefile |1 + > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 + > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 + > arch/arm64/configs/defconfig |2 + > drivers/clk/qcom/Kconfig |9 + > drivers/clk/qcom/Makefile |1 + > drivers/clk/qcom/gcc-ipq6018.c | 5267 > > drivers/pinctrl/qcom/Kconfig | 10 + > drivers/pinctrl/qcom/Makefile |1 + > drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 + > include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 ++ > 13 files changed, 7148 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi > create mode 100644 drivers/clk/qcom/gcc-ipq6018.c > create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c > create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h > -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
3 files changed, 5277 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83c..e5fb091 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -120,6 +120,15 @@ config IPQ_GCC_8074
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq8074.
+config IPQ_GCC_6018
+ tristate "IPQ6018 Global Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for global clock controller on ipq6018 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc. Select this for the root clock
+ of ipq6018.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb..025137d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
+obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
new file mode 100644
index 000..9f4552b
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -0,0 +1,5267 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_BIAS_PLL,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_BIAS_PLL_NSS_NOC,
+ P_UNIPHY1_TX,
+ P_PCIE20_PHY0_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_GPLL6,
+ P_SLEEP_CLK,
+ P_UBI32_PLL,
+ P_NSS_CRYPTO_PLL,
+ P_PI_SLEEP,
+};
+
+static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ "xo",
+ "bias_pll_cc_clk",
+ "gpll0",
+ "gpll4",
+ "nss_crypto_pll",
+ "ubi32_pll",
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ "xo",
+ "bias_pll_nss_noc_clk",
+ "gpll0",
+ "gpll2",
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] =
{
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_t
[PATCH 6/6] arm64: defconfig: Enable qcom ipq6018 clock and pinctrl
These configs are required for booting kernel in qcom ipq6018 boards. Signed-off-by: Sricharan R --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4d58351..abf64ee 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -373,6 +373,7 @@ CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y @@ -646,6 +647,7 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_GCC_8074=y +CONFIG_IPQ_GCC_6018=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231 +++
3 files changed, 267 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index 21d548f..ac22dbb 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_ARCH_QCOM)+= apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM)+= apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM)+= ipq8074-hk01.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8994-angler-rev-101.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
new file mode 100644
index 000..ac7cb22
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPQ6018 CP01 board device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq6018.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
+ compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
+ interrupt-parent = <>;
+};
+
+ {
+ uart_pins: uart_pins {
+ mux {
+ pins = "gpio44", "gpio45";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+};
+
+_uart3 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
new file mode 100644
index 000..79cccdd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPQ6018 SoC device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ6018";
+ compatible = "qcom,ipq6018";
+
+ chosen {
+ bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
+ bootargs-append = " swiotlb=1 clk_ignore_unused";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz:tz@4850 {
+ no-map;
+ reg = <0x0 0x4850 0x0 0x0020>;
+ };
+ };
+
+ soc: soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0 0 0 0x>;
+ dma-ranges;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@b00 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ reg = <0xb00 0x1000>, <0xb002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ timer@b12 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb12 0x1000>;
+ clock-frequency = <1920>;
+
+ frame@b12 {
+ frame-number = <0>;
+ interrupts = ,
+;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = ;
+
[PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller
Add the compatible strings and the include file for ipq6018 gcc clock controller. Signed-off-by: Sricharan R Signed-off-by: anusha Signed-off-by: Abhishek Sahu --- .../devicetree/bindings/clock/qcom,gcc.txt | 1 + include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 + 2 files changed, 406 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 8661c3c..40bb3de 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,gcc-ipq8064" "qcom,gcc-ipq4019" "qcom,gcc-ipq8074" + "qcom,gcc-ipq6018" "qcom,gcc-msm8660" "qcom,gcc-msm8916" "qcom,gcc-msm8960" diff --git a/include/dt-bindings/clock/qcom,gcc-ipq6018.h b/include/dt-bindings/clock/qcom,gcc-ipq6018.h new file mode 100644 index 000..b8aec10 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq6018.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H + +#define GPLL0 0 +#define UBI32_PLL 1 +#define GPLL6 2 +#define GPLL4 3 +#define PCNOC_BFDCD_CLK_SRC4 +#define GPLL2 5 +#define NSS_CRYPTO_PLL 6 +#define NSS_PPE_CLK_SRC7 +#define GCC_XO_CLK_SRC 8 +#define NSS_CE_CLK_SRC 9 +#define GCC_SLEEP_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define NSS_PORT5_RX_CLK_SRC 12 +#define NSS_PORT5_TX_CLK_SRC 13 +#define PCIE0_AXI_CLK_SRC 14 +#define USB0_MASTER_CLK_SRC15 +#define APSS_AHB_POSTDIV_CLK_SRC 16 +#define NSS_PORT1_RX_CLK_SRC 17 +#define NSS_PORT1_TX_CLK_SRC 18 +#define NSS_PORT2_RX_CLK_SRC 19 +#define NSS_PORT2_TX_CLK_SRC 20 +#define NSS_PORT3_RX_CLK_SRC 21 +#define NSS_PORT3_TX_CLK_SRC 22 +#define NSS_PORT4_RX_CLK_SRC 23 +#define NSS_PORT4_TX_CLK_SRC 24 +#define NSS_PORT5_RX_DIV_CLK_SRC 25 +#define NSS_PORT5_TX_DIV_CLK_SRC 26 +#define APSS_AXI_CLK_SRC 27 +#define NSS_CRYPTO_CLK_SRC 28 +#define NSS_PORT1_RX_DIV_CLK_SRC 29 +#define NSS_PORT1_TX_DIV_CLK_SRC 30 +#define NSS_PORT2_RX_DIV_CLK_SRC 31 +#define NSS_PORT2_TX_DIV_CLK_SRC 32 +#define NSS_PORT3_RX_DIV_CLK_SRC 33 +#define NSS_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_PORT4_RX_DIV_CLK_SRC 35 +#define NSS_PORT4_TX_DIV_CLK_SRC 36 +#define NSS_UBI0_CLK_SRC 37 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC38 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC39 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC40 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC41 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC42 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC43 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC44 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC45 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC46 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC47 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC48 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC49 +#define BLSP1_UART1_APPS_CLK_SRC 50 +#define BLSP1_UART2_APPS_CLK_SRC 51 +#define BLSP1_UART3_APPS_CLK_SRC 52 +#define BLSP1_UART4_APPS_CLK_SRC 53 +#define BLSP1_UART5_APPS_CLK_SRC 54 +#define BLSP1_UART6_APPS_CLK_SRC 55 +#define CRYPTO_CLK_SRC 56 +#define NSS_UBI0_DIV_CLK_SRC 57 +#define PCIE0_AUX_CLK_SRC 58 +#define PCIE0_PIPE_CLK_SRC 59 +#define SDCC1_APPS_CLK_SRC 60 +#define USB0_AUX_CLK_SRC 61 +#define USB0_MOCK_UTMI_CLK_SRC 62 +#define USB0_PIPE_CLK_SRC 63 +#define USB1_MOCK_UTMI_CLK_SRC 64 +#define GCC_APSS_AHB_CLK 65 +#define GCC_APSS_AXI_CLK 66 +#define GCC_BLSP1_AHB_CLK
[PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings
Signed-off-by: Sricharan R Signed-off-by: speriaka --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f6316ab..7b19028 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + ipq6018 The 'board' element must be one of the following strings: @@ -45,6 +46,7 @@ description: | mtp sbc hk01 + cp01-c1 The 'soc_version' and 'board_version' elements take the form of v. where the minor number may be omitted when it's zero, i.e. v1.0 is the same -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver
Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq6018. Signed-off-by: Sricharan R Signed-off-by: Rajkumar Ayyasamy Signed-off-by: speriaka --- .../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile |1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 4 files changed, 1380 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt new file mode 100644 index 000..5a3edb1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt @@ -0,0 +1,186 @@ +Qualcomm Technologies, Inc. IPQ6018 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +IPQ6018 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,ipq6018-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio121, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data, + qdsd_cmd, + qdsd_data0, + qdsd_data1, + qdsd_data2, + qdsd_data3 + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0, + atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en, + bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, + blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, + blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, + blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, + cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, + display_5v, dmic0_clk, dmic0_data, dsi_rst,
[PATCH 0/6] Add minimal boot support for IPQ6018
The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq6018-cp01 board. Sricharan R (6): pinctrl: qcom: Add ipq6018 pinctrl driver dt-bindings: qcom: Add ipq6018 bindings clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: Add ipq6018 Global Clock Controller support arm64: dts: Add ipq6018 SoC and CP01 board support arm64: defconfig: Enable qcom ipq6018 clock and pinctrl Documentation/devicetree/bindings/arm/qcom.yaml|2 + .../devicetree/bindings/clock/qcom,gcc.txt |1 + arch/arm64/boot/dts/qcom/Makefile |1 + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 + arch/arm64/configs/defconfig |2 + drivers/clk/qcom/Kconfig |9 + drivers/clk/qcom/Makefile |1 + drivers/clk/qcom/gcc-ipq6018.c | 5267 drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile |1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 + include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 ++ 13 files changed, 7148 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq6018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [RFC PATCH 2/9] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
Hi Niklas,
On 4/4/2019 10:39 AM, Niklas Cassel wrote:
> From: Sricharan R
>
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the read data,
> rest of the driver is same for both the cases. So pull the common things
> out for reuse.
>
> Signed-off-by: Sricharan R
> Signed-off-by: Niklas Cassel
> ---
Thanks for reposting this patch again. Sorry, got completely lost track
on this. Please let me know if you are planning to rework etc or anything
you need from me on this.
Regards,
Sricharan
> ...ryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 16 +--
> drivers/cpufreq/Kconfig.arm | 4 +-
> drivers/cpufreq/Makefile | 2 +-
> ...om-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 +++---
> 4 files changed, 85 insertions(+), 61 deletions(-)
> rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
> qcom-nvmem-cpufreq.txt} (97%)
> rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (69%)
>
> diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> similarity index 97%
> rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> index c2127b96805a..f4a7123730c3 100644
> --- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> @@ -1,13 +1,13 @@
> -Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
> +Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
> ===
>
> -In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> -that have KRYO processors, the CPU ferequencies subset and voltage value
> -of each OPP varies based on the silicon variant in use.
> +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
> +the CPU frequencies subset and voltage value of each OPP varies based on
> +the silicon variant in use.
> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> -The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> +The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information (existing HW bitmap).
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
> @@ -19,7 +19,7 @@ In 'cpus' nodes:
>
> In 'operating-points-v2' table:
> - compatible: Should be
> - - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
> + - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
> - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> efuse registers that has information about the
> speedbin that is used to select the right frequency/voltage
> @@ -127,7 +127,7 @@ Example 1:
> };
>
> cluster0_opp: opp_table0 {
> - compatible = "operating-points-v2-kryo-cpu";
> + compatible = "operating-points-v2-qcom-cpu";
> nvmem-cells = <_efuse>;
> opp-shared;
>
> @@ -338,7 +338,7 @@ Example 1:
> };
>
> cluster1_opp: opp_table1 {
> - compatible = "operating-points-v2-kryo-cpu";
> + compatible = "operating-points-v2-qcom-cpu";
> nvmem-cells = <_efuse>;
> opp-shared;
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 179a1d302f48..2e4aefa0f34d 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -110,8 +110,8 @@ config ARM_OMAP2PLUS_CPUFREQ
> depends on ARCH_OMAP2PLUS
> default ARCH_OMAP2PLUS
>
> -config ARM_QCOM_CPUFREQ_KRYO
> - tristate "Qualcomm Kryo based CPUFreq"
> +config ARM_QCOM_CPUFREQ_NVMEM
> + tristate "Qualcomm nvmem based CPUFreq"
> depends on ARM64
> depends on QCOM_QFPROM
> depends on QCOM_SMEM
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 689b26c6f949..8e83fd73bd2d 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -63,7 +63,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
> obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
> o
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
Hi Niklas, On 10/22/2018 9:00 PM, Niklas Cassel wrote: > On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote: >> Hi Stephen, >> >> On 10/18/2018 1:46 AM, Stephen Boyd wrote: >>> Quoting Stephen Boyd (2018-10-17 08:44:12) >>>> Quoting Sricharan R (2018-09-20 06:03:31) >>>>> >>>>> >>>>> On 9/20/2018 1:54 AM, Craig wrote: >>>>>> Yup, this patch seems to have fixed the higher frequencies from the >>>>>> quick test I did. >>>>>> >>>>> Thanks !!. Can i take that as >>>>> Tested-by: Craig Tatlor ? >>>>> >>>> >>>> Is this patch series going to be resent? >>>> >>> >>> Nevermind. Looking at it I think I can apply all the clk ones and we're >>> good to go. If you can send a followup patch series to change the >>> registration and provider APIs to be clk_hw instead of clk based I would >>> appreciate it. >>> >> >> Sorry for the late response. Was away. >> Only pending thing was separating out the binding documentation for the >> cpu-freq >> driver and fixing the text in documentation. That means, yes its fine to >> merge >> the clk ones as you said. I will resend that. Also, will send a follow up >> series for clk_hw to >> clk change as you mentioned separately. > > Hello Sricharan, > > Great to see that the clk parts has been marged to clk-next! > > Are you also planning on sending out a new version of the cpufreq driver > consolidation parts? > yeah right, will send a new version, sometime next week. > I'm planning on extending your consilidated cpufreq driver with support > for msm8916 (Cortex-A53), where I plan to read PVS/speedbin, in order to > set opp_supported_hw(), and also register with cpufreq (since Viresh/Ulf > suggested that we shouldn't register with cpufreq in the CPR power-domain > driver). ok sure. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
Hi Niklas, On 10/22/2018 9:00 PM, Niklas Cassel wrote: > On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote: >> Hi Stephen, >> >> On 10/18/2018 1:46 AM, Stephen Boyd wrote: >>> Quoting Stephen Boyd (2018-10-17 08:44:12) >>>> Quoting Sricharan R (2018-09-20 06:03:31) >>>>> >>>>> >>>>> On 9/20/2018 1:54 AM, Craig wrote: >>>>>> Yup, this patch seems to have fixed the higher frequencies from the >>>>>> quick test I did. >>>>>> >>>>> Thanks !!. Can i take that as >>>>> Tested-by: Craig Tatlor ? >>>>> >>>> >>>> Is this patch series going to be resent? >>>> >>> >>> Nevermind. Looking at it I think I can apply all the clk ones and we're >>> good to go. If you can send a followup patch series to change the >>> registration and provider APIs to be clk_hw instead of clk based I would >>> appreciate it. >>> >> >> Sorry for the late response. Was away. >> Only pending thing was separating out the binding documentation for the >> cpu-freq >> driver and fixing the text in documentation. That means, yes its fine to >> merge >> the clk ones as you said. I will resend that. Also, will send a follow up >> series for clk_hw to >> clk change as you mentioned separately. > > Hello Sricharan, > > Great to see that the clk parts has been marged to clk-next! > > Are you also planning on sending out a new version of the cpufreq driver > consolidation parts? > yeah right, will send a new version, sometime next week. > I'm planning on extending your consilidated cpufreq driver with support > for msm8916 (Cortex-A53), where I plan to read PVS/speedbin, in order to > set opp_supported_hw(), and also register with cpufreq (since Viresh/Ulf > suggested that we shouldn't register with cpufreq in the CPR power-domain > driver). ok sure. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
Hi Stephen, On 10/18/2018 1:46 AM, Stephen Boyd wrote: > Quoting Stephen Boyd (2018-10-17 08:44:12) >> Quoting Sricharan R (2018-09-20 06:03:31) >>> >>> >>> On 9/20/2018 1:54 AM, Craig wrote: >>>> Yup, this patch seems to have fixed the higher frequencies from the quick >>>> test I did. >>>> >>> Thanks !!. Can i take that as >>> Tested-by: Craig Tatlor ? >>> >> >> Is this patch series going to be resent? >> > > Nevermind. Looking at it I think I can apply all the clk ones and we're > good to go. If you can send a followup patch series to change the > registration and provider APIs to be clk_hw instead of clk based I would > appreciate it. > Sorry for the late response. Was away. Only pending thing was separating out the binding documentation for the cpu-freq driver and fixing the text in documentation. That means, yes its fine to merge the clk ones as you said. I will resend that. Also, will send a follow up series for clk_hw to clk change as you mentioned separately. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
Hi Stephen, On 10/18/2018 1:46 AM, Stephen Boyd wrote: > Quoting Stephen Boyd (2018-10-17 08:44:12) >> Quoting Sricharan R (2018-09-20 06:03:31) >>> >>> >>> On 9/20/2018 1:54 AM, Craig wrote: >>>> Yup, this patch seems to have fixed the higher frequencies from the quick >>>> test I did. >>>> >>> Thanks !!. Can i take that as >>> Tested-by: Craig Tatlor ? >>> >> >> Is this patch series going to be resent? >> > > Nevermind. Looking at it I think I can apply all the clk ones and we're > good to go. If you can send a followup patch series to change the > registration and provider APIs to be clk_hw instead of clk based I would > appreciate it. > Sorry for the late response. Was away. Only pending thing was separating out the binding documentation for the cpu-freq driver and fixing the text in documentation. That means, yes its fine to merge the clk ones as you said. I will resend that. Also, will send a follow up series for clk_hw to clk change as you mentioned separately. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
On 9/20/2018 1:54 AM, Craig wrote: > Yup, this patch seems to have fixed the higher frequencies from the quick > test I did. > Thanks !!. Can i take that as Tested-by: Craig Tatlor ? Regards, Sricharan > On 7 September 2018 15:28:53 BST, Craig Tatlor wrote: >> >> >> On 7 September 2018 10:57:34 BST, Sricharan R >> wrote: >>> Hi Craig, >>> >>> >>>>> [v12] >>>>> * Added my signed-off that was missing in some patches. >>>>> * Added Bjorn's acked that i missed earlier. >>>>> >>>> >>>> Can you give this a try on your 8974 device and check if the >>>> pvs version reporting, scaling for higher frequencies are fine ? >>>> Sorry, i could not get hold of a 8974 device. So in-case if you >>> still >>>> have the issues with higher frequencies, can you give a quick >> debug >>>> and report. That would be of great help. >>>> >>> Ping on this .. >> >> Hi, didn't see your last message, >> >> Will have a try on mine in the weekend and report back. >>> >>> Regards, >>> Sricharan >>> >>>> Regards, >>>> Sricharan >>>> >>>> >>>>> [v11] >>>>> * Dropped patch 13 and 14 from v10 and >>>>> merged the qcom-cpufreq-krait driver to the existing >>> qcom-cpufreq-kryo.c >>>>> * Rebased on top of clk-next >>>>> * Fixed a bug while populating the pvs version for krait. >>>>> >>>>> [v10] >>>>> * Addressed Stephen's comments to add clocks bindings properties >>>>> to the newly introduced nodes. >>>>> * Added a change to include opp-supported-hw to qcom-cpufreq.c >>>>> * Rebased on top of clk-next >>>>> * Although there were minor changes to bindings and the driver >>>>> retained the acked-by tags from Rob and Viresh respectively. >> >>>>> >>>>> [v9] >>>>> * Fixed a rebase issue in Makefile and added Tag from Robh. >>>>> >>>>> [v8] >>>>> * Fixed a bug in path#14 pointed out by Viresh and also added >>> tags. >>>>> No change in any other patch. >>>>> >>>>> [v7] >>>>> * Fixed comments from Viresh for cleaning up the error handling >>>>> in qcom-cpufreq.c. Also changed the init function to lateinit >>>>> call. This is required because nvmem which gets initialised >> with >>>>> module_init needs to go first. >>>>> * Fixed Rob's comments for bindings documentation >>>>> * Fixed kbuild build issue in clk-lpc32xx.c >>>>> * Rebased on top of clk-next >>>>> >>>>> [v6] >>>>> * Adrressed comments from Viresh for patch #14 in v5 [5] >>>>> * Introduced a new binding operating-points-v2-krait-cpu >>>>> as per discussion with Rob >>>>> * Added Review tags >>>>> >>>>> [v5] >>>>> * Addressed comments from Rob for bindings >>>>> * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, >>> accordingly >>>>> dropped patch #12 and corrected patch #11 from previous patch >>> set in [4] >>>>> * Converted to use #spdx tags for newly introduced files >>>>> >>>>> Mostly a resend of the v3 posted by Stephen quite some time back >> [1] >>>>> except for few changes. >>>>> Based on reading some feedback from list, >>>>> * Dropped the patch "clk: Add safe switch hook" from v3 [2]. >>>>> Now this is taken care by patch#10 in this series only for >>> Krait. >>>>> * Dropped the path "clk: Avoid sending high rates to downstream >>>>> clocks during set_rate" from v3 [3]. >>>>> * Rebased on top of clk-next. >>>>> * Dropped the DT update from the series. Will send separately >>>>> * Now with cpufreq-dt+opp supporting voltage scaling, registering >>> the >>>>> krait cpu supplies in DT should be sufficient. But one issue >> is, >>>>> the qcom-cpufreq drivers reads the efuse and based on that >>> registers >>>>> the opp data and then registers the cpufreq-dt
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
On 9/20/2018 1:54 AM, Craig wrote: > Yup, this patch seems to have fixed the higher frequencies from the quick > test I did. > Thanks !!. Can i take that as Tested-by: Craig Tatlor ? Regards, Sricharan > On 7 September 2018 15:28:53 BST, Craig Tatlor wrote: >> >> >> On 7 September 2018 10:57:34 BST, Sricharan R >> wrote: >>> Hi Craig, >>> >>> >>>>> [v12] >>>>> * Added my signed-off that was missing in some patches. >>>>> * Added Bjorn's acked that i missed earlier. >>>>> >>>> >>>> Can you give this a try on your 8974 device and check if the >>>> pvs version reporting, scaling for higher frequencies are fine ? >>>> Sorry, i could not get hold of a 8974 device. So in-case if you >>> still >>>> have the issues with higher frequencies, can you give a quick >> debug >>>> and report. That would be of great help. >>>> >>> Ping on this .. >> >> Hi, didn't see your last message, >> >> Will have a try on mine in the weekend and report back. >>> >>> Regards, >>> Sricharan >>> >>>> Regards, >>>> Sricharan >>>> >>>> >>>>> [v11] >>>>> * Dropped patch 13 and 14 from v10 and >>>>> merged the qcom-cpufreq-krait driver to the existing >>> qcom-cpufreq-kryo.c >>>>> * Rebased on top of clk-next >>>>> * Fixed a bug while populating the pvs version for krait. >>>>> >>>>> [v10] >>>>> * Addressed Stephen's comments to add clocks bindings properties >>>>> to the newly introduced nodes. >>>>> * Added a change to include opp-supported-hw to qcom-cpufreq.c >>>>> * Rebased on top of clk-next >>>>> * Although there were minor changes to bindings and the driver >>>>> retained the acked-by tags from Rob and Viresh respectively. >> >>>>> >>>>> [v9] >>>>> * Fixed a rebase issue in Makefile and added Tag from Robh. >>>>> >>>>> [v8] >>>>> * Fixed a bug in path#14 pointed out by Viresh and also added >>> tags. >>>>> No change in any other patch. >>>>> >>>>> [v7] >>>>> * Fixed comments from Viresh for cleaning up the error handling >>>>> in qcom-cpufreq.c. Also changed the init function to lateinit >>>>> call. This is required because nvmem which gets initialised >> with >>>>> module_init needs to go first. >>>>> * Fixed Rob's comments for bindings documentation >>>>> * Fixed kbuild build issue in clk-lpc32xx.c >>>>> * Rebased on top of clk-next >>>>> >>>>> [v6] >>>>> * Adrressed comments from Viresh for patch #14 in v5 [5] >>>>> * Introduced a new binding operating-points-v2-krait-cpu >>>>> as per discussion with Rob >>>>> * Added Review tags >>>>> >>>>> [v5] >>>>> * Addressed comments from Rob for bindings >>>>> * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, >>> accordingly >>>>> dropped patch #12 and corrected patch #11 from previous patch >>> set in [4] >>>>> * Converted to use #spdx tags for newly introduced files >>>>> >>>>> Mostly a resend of the v3 posted by Stephen quite some time back >> [1] >>>>> except for few changes. >>>>> Based on reading some feedback from list, >>>>> * Dropped the patch "clk: Add safe switch hook" from v3 [2]. >>>>> Now this is taken care by patch#10 in this series only for >>> Krait. >>>>> * Dropped the path "clk: Avoid sending high rates to downstream >>>>> clocks during set_rate" from v3 [3]. >>>>> * Rebased on top of clk-next. >>>>> * Dropped the DT update from the series. Will send separately >>>>> * Now with cpufreq-dt+opp supporting voltage scaling, registering >>> the >>>>> krait cpu supplies in DT should be sufficient. But one issue >> is, >>>>> the qcom-cpufreq drivers reads the efuse and based on that >>> registers >>>>> the opp data and then registers the cpufreq-dt
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
On 9/20/2018 1:54 AM, Craig wrote: > Yup, this patch seems to have fixed the higher frequencies from the quick > test I did. > Thanks !!. Can i take that as Craig Tatlor ? Regards, Sricharan tested-by: > On 7 September 2018 15:28:53 BST, Craig Tatlor wrote: >> >> >> On 7 September 2018 10:57:34 BST, Sricharan R >> wrote: >>> Hi Craig, >>> >>> >>>>> [v12] >>>>> * Added my signed-off that was missing in some patches. >>>>> * Added Bjorn's acked that i missed earlier. >>>>> >>>> >>>> Can you give this a try on your 8974 device and check if the >>>> pvs version reporting, scaling for higher frequencies are fine ? >>>> Sorry, i could not get hold of a 8974 device. So in-case if you >>> still >>>> have the issues with higher frequencies, can you give a quick >> debug >>>> and report. That would be of great help. >>>> >>> Ping on this .. >> >> Hi, didn't see your last message, >> >> Will have a try on mine in the weekend and report back. >>> >>> Regards, >>> Sricharan >>> >>>> Regards, >>>> Sricharan >>>> >>>> >>>>> [v11] >>>>> * Dropped patch 13 and 14 from v10 and >>>>> merged the qcom-cpufreq-krait driver to the existing >>> qcom-cpufreq-kryo.c >>>>> * Rebased on top of clk-next >>>>> * Fixed a bug while populating the pvs version for krait. >>>>> >>>>> [v10] >>>>> * Addressed Stephen's comments to add clocks bindings properties >>>>> to the newly introduced nodes. >>>>> * Added a change to include opp-supported-hw to qcom-cpufreq.c >>>>> * Rebased on top of clk-next >>>>> * Although there were minor changes to bindings and the driver >>>>> retained the acked-by tags from Rob and Viresh respectively. >> >>>>> >>>>> [v9] >>>>> * Fixed a rebase issue in Makefile and added Tag from Robh. >>>>> >>>>> [v8] >>>>> * Fixed a bug in path#14 pointed out by Viresh and also added >>> tags. >>>>> No change in any other patch. >>>>> >>>>> [v7] >>>>> * Fixed comments from Viresh for cleaning up the error handling >>>>> in qcom-cpufreq.c. Also changed the init function to lateinit >>>>> call. This is required because nvmem which gets initialised >> with >>>>> module_init needs to go first. >>>>> * Fixed Rob's comments for bindings documentation >>>>> * Fixed kbuild build issue in clk-lpc32xx.c >>>>> * Rebased on top of clk-next >>>>> >>>>> [v6] >>>>> * Adrressed comments from Viresh for patch #14 in v5 [5] >>>>> * Introduced a new binding operating-points-v2-krait-cpu >>>>> as per discussion with Rob >>>>> * Added Review tags >>>>> >>>>> [v5] >>>>> * Addressed comments from Rob for bindings >>>>> * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, >>> accordingly >>>>> dropped patch #12 and corrected patch #11 from previous patch >>> set in [4] >>>>> * Converted to use #spdx tags for newly introduced files >>>>> >>>>> Mostly a resend of the v3 posted by Stephen quite some time back >> [1] >>>>> except for few changes. >>>>> Based on reading some feedback from list, >>>>> * Dropped the patch "clk: Add safe switch hook" from v3 [2]. >>>>> Now this is taken care by patch#10 in this series only for >>> Krait. >>>>> * Dropped the path "clk: Avoid sending high rates to downstream >>>>> clocks during set_rate" from v3 [3]. >>>>> * Rebased on top of clk-next. >>>>> * Dropped the DT update from the series. Will send separately >>>>> * Now with cpufreq-dt+opp supporting voltage scaling, registering >>> the >>>>> krait cpu supplies in DT should be sufficient. But one issue >> is, >>>>> the qcom-cpufreq drivers reads the efuse and based on that >>> registers >>>>> the opp data and then registers the cpufreq-dt
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
On 9/20/2018 1:54 AM, Craig wrote: > Yup, this patch seems to have fixed the higher frequencies from the quick > test I did. > Thanks !!. Can i take that as Craig Tatlor ? Regards, Sricharan tested-by: > On 7 September 2018 15:28:53 BST, Craig Tatlor wrote: >> >> >> On 7 September 2018 10:57:34 BST, Sricharan R >> wrote: >>> Hi Craig, >>> >>> >>>>> [v12] >>>>> * Added my signed-off that was missing in some patches. >>>>> * Added Bjorn's acked that i missed earlier. >>>>> >>>> >>>> Can you give this a try on your 8974 device and check if the >>>> pvs version reporting, scaling for higher frequencies are fine ? >>>> Sorry, i could not get hold of a 8974 device. So in-case if you >>> still >>>> have the issues with higher frequencies, can you give a quick >> debug >>>> and report. That would be of great help. >>>> >>> Ping on this .. >> >> Hi, didn't see your last message, >> >> Will have a try on mine in the weekend and report back. >>> >>> Regards, >>> Sricharan >>> >>>> Regards, >>>> Sricharan >>>> >>>> >>>>> [v11] >>>>> * Dropped patch 13 and 14 from v10 and >>>>> merged the qcom-cpufreq-krait driver to the existing >>> qcom-cpufreq-kryo.c >>>>> * Rebased on top of clk-next >>>>> * Fixed a bug while populating the pvs version for krait. >>>>> >>>>> [v10] >>>>> * Addressed Stephen's comments to add clocks bindings properties >>>>> to the newly introduced nodes. >>>>> * Added a change to include opp-supported-hw to qcom-cpufreq.c >>>>> * Rebased on top of clk-next >>>>> * Although there were minor changes to bindings and the driver >>>>> retained the acked-by tags from Rob and Viresh respectively. >> >>>>> >>>>> [v9] >>>>> * Fixed a rebase issue in Makefile and added Tag from Robh. >>>>> >>>>> [v8] >>>>> * Fixed a bug in path#14 pointed out by Viresh and also added >>> tags. >>>>> No change in any other patch. >>>>> >>>>> [v7] >>>>> * Fixed comments from Viresh for cleaning up the error handling >>>>> in qcom-cpufreq.c. Also changed the init function to lateinit >>>>> call. This is required because nvmem which gets initialised >> with >>>>> module_init needs to go first. >>>>> * Fixed Rob's comments for bindings documentation >>>>> * Fixed kbuild build issue in clk-lpc32xx.c >>>>> * Rebased on top of clk-next >>>>> >>>>> [v6] >>>>> * Adrressed comments from Viresh for patch #14 in v5 [5] >>>>> * Introduced a new binding operating-points-v2-krait-cpu >>>>> as per discussion with Rob >>>>> * Added Review tags >>>>> >>>>> [v5] >>>>> * Addressed comments from Rob for bindings >>>>> * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, >>> accordingly >>>>> dropped patch #12 and corrected patch #11 from previous patch >>> set in [4] >>>>> * Converted to use #spdx tags for newly introduced files >>>>> >>>>> Mostly a resend of the v3 posted by Stephen quite some time back >> [1] >>>>> except for few changes. >>>>> Based on reading some feedback from list, >>>>> * Dropped the patch "clk: Add safe switch hook" from v3 [2]. >>>>> Now this is taken care by patch#10 in this series only for >>> Krait. >>>>> * Dropped the path "clk: Avoid sending high rates to downstream >>>>> clocks during set_rate" from v3 [3]. >>>>> * Rebased on top of clk-next. >>>>> * Dropped the DT update from the series. Will send separately >>>>> * Now with cpufreq-dt+opp supporting voltage scaling, registering >>> the >>>>> krait cpu supplies in DT should be sufficient. But one issue >> is, >>>>> the qcom-cpufreq drivers reads the efuse and based on that >>> registers >>>>> the opp data and then registers the cpufreq-dt
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
+|\
>> | | |-+
>> +---|/ | primary
>> + | +
>> +-|\ +--+
>> +---+| \ | |
>> | HFPLL || |-| CPU1 |
>> +---+ | | | | |
>> | +-+ | / +--+
>> +-| / 2 |-|/
>>+-+ +
>>
>> To support this in the common clock framework we model the muxes,
>> dividers, and PLLs as different clocks. CPUfreq only interacts
>> with the primary mux (farthest right in the diagram). When CPUfreq
>> sets a rate, the mux code finds the best parent that can provide the rate.
>> Due to the design, QSB and the top PLL are always a fixed rate and thus
>> only support one frequency each. These sources provide the lowest
>> frequencies for the CPUs. The HFPLLs are where we can make the CPU go
>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>> fast and divide it by two to get a particular frequency.
>>
>> When switching rates we can't leave the CPU clocked by the HFPLL because
>> we need to turn off the output of the PLL when changing its frequency.
>> This means we have to switch over to the secondary mux and use one of the
>> fixed sources. This is why we need something like the safe parent patch.
>>
>> [1]
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>> [2]
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>> [3]
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>> [4] https://lwn.net/Articles/740994/
>> [5] https://lkml.org/lkml/2017/12/19/537
>>
>>
>> Sricharan R (3):
>> clk: qcom: Add safe switch hook for krait mux clocks
>> cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>> based qcom socs
>> cpufreq: qcom: Add support for krait based socs
>>
>> Stephen Boyd (11):
>> ARM: Add Krait L2 register accessor functions
>> clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>> clk: qcom: Add HFPLL driver
>> dt-bindings: clock: Document qcom,hfpll
>> clk: qcom: Add MSM8960/APQ8064's HFPLLs
>> clk: qcom: Add IPQ806X's HFPLLs
>> clk: qcom: Add support for Krait clocks
>> clk: qcom: Add KPSS ACC/GCC driver
>> dt-bindings: arm: Document qcom,kpss-gcc
>> clk: qcom: Add Krait clock controller driver
>> dt-bindings: clock: Document qcom,krait-cc
>>
>> .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 +
>> .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++
>> .../devicetree/bindings/clock/qcom,hfpll.txt | 60
>> .../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
>> .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 7 +-
>> arch/arm/common/Kconfig| 3 +
>> arch/arm/common/Makefile | 1 +
>> arch/arm/common/krait-l2-accessors.c | 48 +++
>> arch/arm/include/asm/krait-l2-accessors.h | 9 +
>> drivers/clk/qcom/Kconfig | 28 ++
>> drivers/clk/qcom/Makefile | 5 +
>> drivers/clk/qcom/clk-hfpll.c | 244 +
>> drivers/clk/qcom/clk-hfpll.h | 44 +++
>> drivers/clk/qcom/clk-krait.c | 126 +++
>> drivers/clk/qcom/clk-krait.h | 40 +++
>> drivers/clk/qcom/gcc-ipq806x.c | 82 +
>> drivers/clk/qcom/gcc-msm8960.c | 172 +
>> drivers/clk/qcom/hfpll.c | 96 +
>> drivers/clk/qcom/kpss-xcc.c| 87 +
>> drivers/clk/qcom/krait-cc.c| 397
>> +
>> drivers/cpufreq/Kconfig.arm| 6 +-
>> drivers/cpufreq/Makefile | 2 +-
>> drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
>> drivers/cpufreq/qcom-cpufreq-kryo.c| 232
>> drivers/cpufreq/qcom-cpufreq-nvmem.c | 387
>>
>> include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
>> 26 files changed, 1941 insertions(+), 239 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>> rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
>> qcom-nvmem-cpufreq.txt} (98%)
>> create mode 100644 arch/arm/common/krait-l2-accessors.c
>> create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>> create mode 100644 drivers/clk/qcom/clk-hfpll.c
>> create mode 100644 drivers/clk/qcom/clk-hfpll.h
>> create mode 100644 drivers/clk/qcom/clk-krait.c
>> create mode 100644 drivers/clk/qcom/clk-krait.h
>> create mode 100644 drivers/clk/qcom/hfpll.c
>> create mode 100644 drivers/clk/qcom/kpss-xcc.c
>> create mode 100644 drivers/clk/qcom/krait-cc.c
>> delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>> create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>
>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
+|\
>> | | |-+
>> +---|/ | primary
>> + | +
>> +-|\ +--+
>> +---+| \ | |
>> | HFPLL || |-| CPU1 |
>> +---+ | | | | |
>> | +-+ | / +--+
>> +-| / 2 |-|/
>>+-+ +
>>
>> To support this in the common clock framework we model the muxes,
>> dividers, and PLLs as different clocks. CPUfreq only interacts
>> with the primary mux (farthest right in the diagram). When CPUfreq
>> sets a rate, the mux code finds the best parent that can provide the rate.
>> Due to the design, QSB and the top PLL are always a fixed rate and thus
>> only support one frequency each. These sources provide the lowest
>> frequencies for the CPUs. The HFPLLs are where we can make the CPU go
>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>> fast and divide it by two to get a particular frequency.
>>
>> When switching rates we can't leave the CPU clocked by the HFPLL because
>> we need to turn off the output of the PLL when changing its frequency.
>> This means we have to switch over to the secondary mux and use one of the
>> fixed sources. This is why we need something like the safe parent patch.
>>
>> [1]
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>> [2]
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>> [3]
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>> [4] https://lwn.net/Articles/740994/
>> [5] https://lkml.org/lkml/2017/12/19/537
>>
>>
>> Sricharan R (3):
>> clk: qcom: Add safe switch hook for krait mux clocks
>> cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>> based qcom socs
>> cpufreq: qcom: Add support for krait based socs
>>
>> Stephen Boyd (11):
>> ARM: Add Krait L2 register accessor functions
>> clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>> clk: qcom: Add HFPLL driver
>> dt-bindings: clock: Document qcom,hfpll
>> clk: qcom: Add MSM8960/APQ8064's HFPLLs
>> clk: qcom: Add IPQ806X's HFPLLs
>> clk: qcom: Add support for Krait clocks
>> clk: qcom: Add KPSS ACC/GCC driver
>> dt-bindings: arm: Document qcom,kpss-gcc
>> clk: qcom: Add Krait clock controller driver
>> dt-bindings: clock: Document qcom,krait-cc
>>
>> .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 +
>> .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++
>> .../devicetree/bindings/clock/qcom,hfpll.txt | 60
>> .../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
>> .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 7 +-
>> arch/arm/common/Kconfig| 3 +
>> arch/arm/common/Makefile | 1 +
>> arch/arm/common/krait-l2-accessors.c | 48 +++
>> arch/arm/include/asm/krait-l2-accessors.h | 9 +
>> drivers/clk/qcom/Kconfig | 28 ++
>> drivers/clk/qcom/Makefile | 5 +
>> drivers/clk/qcom/clk-hfpll.c | 244 +
>> drivers/clk/qcom/clk-hfpll.h | 44 +++
>> drivers/clk/qcom/clk-krait.c | 126 +++
>> drivers/clk/qcom/clk-krait.h | 40 +++
>> drivers/clk/qcom/gcc-ipq806x.c | 82 +
>> drivers/clk/qcom/gcc-msm8960.c | 172 +
>> drivers/clk/qcom/hfpll.c | 96 +
>> drivers/clk/qcom/kpss-xcc.c| 87 +
>> drivers/clk/qcom/krait-cc.c| 397
>> +
>> drivers/cpufreq/Kconfig.arm| 6 +-
>> drivers/cpufreq/Makefile | 2 +-
>> drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
>> drivers/cpufreq/qcom-cpufreq-kryo.c| 232
>> drivers/cpufreq/qcom-cpufreq-nvmem.c | 387
>>
>> include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
>> 26 files changed, 1941 insertions(+), 239 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>> rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
>> qcom-nvmem-cpufreq.txt} (98%)
>> create mode 100644 arch/arm/common/krait-l2-accessors.c
>> create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>> create mode 100644 drivers/clk/qcom/clk-hfpll.c
>> create mode 100644 drivers/clk/qcom/clk-hfpll.h
>> create mode 100644 drivers/clk/qcom/clk-krait.c
>> create mode 100644 drivers/clk/qcom/clk-krait.h
>> create mode 100644 drivers/clk/qcom/hfpll.c
>> create mode 100644 drivers/clk/qcom/kpss-xcc.c
>> create mode 100644 drivers/clk/qcom/krait-cc.c
>> delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>> create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>
>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
Hi Rob, On 8/17/2018 8:39 PM, Rob Herring wrote: > Hi, this email is from Rob's (experimental) review bot. I found a couple > of common problems with your patch. Please see below. > > On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote: >> The kryo cpufreq driver reads the nvmem cell and uses that data to >> populate the opps. There are other qcom cpufreq socs like krait which >> does similar thing. Except for the interpretation of the read data, >> rest of the driver is same for both the cases. So pull the common things >> out for reuse. >> >> Signed-off-by: Sricharan R > > The preferred subject prefix is "dt-bindings: : ...". > ok, will change and keep the bindings update part out for this and the next patch. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
Hi Rob, On 8/17/2018 8:39 PM, Rob Herring wrote: > Hi, this email is from Rob's (experimental) review bot. I found a couple > of common problems with your patch. Please see below. > > On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote: >> The kryo cpufreq driver reads the nvmem cell and uses that data to >> populate the opps. There are other qcom cpufreq socs like krait which >> does similar thing. Except for the interpretation of the read data, >> rest of the driver is same for both the cases. So pull the common things >> out for reuse. >> >> Signed-off-by: Sricharan R > > The preferred subject prefix is "dt-bindings: : ...". > ok, will change and keep the bindings update part out for this and the next patch. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
Hi Craig, On 8/14/2018 5:42 PM, Sricharan R wrote: > [v12] > * Added my signed-off that was missing in some patches. > * Added Bjorn's acked that i missed earlier. > Can you give this a try on your 8974 device and check if the pvs version reporting, scaling for higher frequencies are fine ? Sorry, i could not get hold of a 8974 device. So in-case if you still have the issues with higher frequencies, can you give a quick debug and report. That would be of great help. Regards, Sricharan > [v11] > * Dropped patch 13 and 14 from v10 and > merged the qcom-cpufreq-krait driver to the existing qcom-cpufreq-kryo.c > * Rebased on top of clk-next > * Fixed a bug while populating the pvs version for krait. > > [v10] > * Addressed Stephen's comments to add clocks bindings properties > to the newly introduced nodes. > * Added a change to include opp-supported-hw to qcom-cpufreq.c > * Rebased on top of clk-next > * Although there were minor changes to bindings and the driver > retained the acked-by tags from Rob and Viresh respectively. > > [v9] > * Fixed a rebase issue in Makefile and added Tag from Robh. > > [v8] > * Fixed a bug in path#14 pointed out by Viresh and also added tags. > No change in any other patch. > > [v7] > * Fixed comments from Viresh for cleaning up the error handling > in qcom-cpufreq.c. Also changed the init function to lateinit > call. This is required because nvmem which gets initialised with > module_init needs to go first. > * Fixed Rob's comments for bindings documentation > * Fixed kbuild build issue in clk-lpc32xx.c > * Rebased on top of clk-next > > [v6] > * Adrressed comments from Viresh for patch #14 in v5 [5] > * Introduced a new binding operating-points-v2-krait-cpu > as per discussion with Rob > * Added Review tags > > [v5] > * Addressed comments from Rob for bindings > * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, > accordingly > dropped patch #12 and corrected patch #11 from previous patch set in [4] > * Converted to use #spdx tags for newly introduced files > > Mostly a resend of the v3 posted by Stephen quite some time back [1] > except for few changes. > Based on reading some feedback from list, > * Dropped the patch "clk: Add safe switch hook" from v3 [2]. > Now this is taken care by patch#10 in this series only for Krait. > * Dropped the path "clk: Avoid sending high rates to downstream > clocks during set_rate" from v3 [3]. > * Rebased on top of clk-next. > * Dropped the DT update from the series. Will send separately > * Now with cpufreq-dt+opp supporting voltage scaling, registering the > krait cpu supplies in DT should be sufficient. But one issue is, > the qcom-cpufreq drivers reads the efuse and based on that registers > the opp data and then registers the cpufreq-dt device. So when > cpufreq-dt driver probes and registers the regulator to the OPP framework, > it expects that the opp data for the device should not be registered > before > the regulator. Will send a RFC patch removing that check, to find out the > right way of doing it. > > These patches provide cpufreq scaling on devices with Krait CPUs. > In Krait CPU designs there's one PLL and two muxes per CPU, allowing > us to switch CPU frequencies independently. > >secondary >+-++ >| QSB |---+|\ >+-+ || |-+ > |+---|/ | > || + | >+-+ || | >| PLL |+---+ | primary >+-+| || + > | |+-|\ +--+ >+---+ | | | \ | | >| HFPLL |--+-| |-| CPU0 | >+---+ | || | | | | > | || +-+ | / +--+ > | |+-| / 2 |-|/ > | | +-+ + > | | secondary > | |+ > | +|\ > | | |-+ > +---|/ | primary > + | + > +-|\ +--+ >+---+| \ | | >| HFPLL || |-| CPU1 | >+---+
Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
Hi Craig, On 8/14/2018 5:42 PM, Sricharan R wrote: > [v12] > * Added my signed-off that was missing in some patches. > * Added Bjorn's acked that i missed earlier. > Can you give this a try on your 8974 device and check if the pvs version reporting, scaling for higher frequencies are fine ? Sorry, i could not get hold of a 8974 device. So in-case if you still have the issues with higher frequencies, can you give a quick debug and report. That would be of great help. Regards, Sricharan > [v11] > * Dropped patch 13 and 14 from v10 and > merged the qcom-cpufreq-krait driver to the existing qcom-cpufreq-kryo.c > * Rebased on top of clk-next > * Fixed a bug while populating the pvs version for krait. > > [v10] > * Addressed Stephen's comments to add clocks bindings properties > to the newly introduced nodes. > * Added a change to include opp-supported-hw to qcom-cpufreq.c > * Rebased on top of clk-next > * Although there were minor changes to bindings and the driver > retained the acked-by tags from Rob and Viresh respectively. > > [v9] > * Fixed a rebase issue in Makefile and added Tag from Robh. > > [v8] > * Fixed a bug in path#14 pointed out by Viresh and also added tags. > No change in any other patch. > > [v7] > * Fixed comments from Viresh for cleaning up the error handling > in qcom-cpufreq.c. Also changed the init function to lateinit > call. This is required because nvmem which gets initialised with > module_init needs to go first. > * Fixed Rob's comments for bindings documentation > * Fixed kbuild build issue in clk-lpc32xx.c > * Rebased on top of clk-next > > [v6] > * Adrressed comments from Viresh for patch #14 in v5 [5] > * Introduced a new binding operating-points-v2-krait-cpu > as per discussion with Rob > * Added Review tags > > [v5] > * Addressed comments from Rob for bindings > * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, > accordingly > dropped patch #12 and corrected patch #11 from previous patch set in [4] > * Converted to use #spdx tags for newly introduced files > > Mostly a resend of the v3 posted by Stephen quite some time back [1] > except for few changes. > Based on reading some feedback from list, > * Dropped the patch "clk: Add safe switch hook" from v3 [2]. > Now this is taken care by patch#10 in this series only for Krait. > * Dropped the path "clk: Avoid sending high rates to downstream > clocks during set_rate" from v3 [3]. > * Rebased on top of clk-next. > * Dropped the DT update from the series. Will send separately > * Now with cpufreq-dt+opp supporting voltage scaling, registering the > krait cpu supplies in DT should be sufficient. But one issue is, > the qcom-cpufreq drivers reads the efuse and based on that registers > the opp data and then registers the cpufreq-dt device. So when > cpufreq-dt driver probes and registers the regulator to the OPP framework, > it expects that the opp data for the device should not be registered > before > the regulator. Will send a RFC patch removing that check, to find out the > right way of doing it. > > These patches provide cpufreq scaling on devices with Krait CPUs. > In Krait CPU designs there's one PLL and two muxes per CPU, allowing > us to switch CPU frequencies independently. > >secondary >+-++ >| QSB |---+|\ >+-+ || |-+ > |+---|/ | > || + | >+-+ || | >| PLL |+---+ | primary >+-+| || + > | |+-|\ +--+ >+---+ | | | \ | | >| HFPLL |--+-| |-| CPU0 | >+---+ | || | | | | > | || +-+ | / +--+ > | |+-| / 2 |-|/ > | | +-+ + > | | secondary > | |+ > | +|\ > | | |-+ > +---|/ | primary > + | + > +-|\ +--+ >+---+| \ | | >| HFPLL || |-| CPU1 | >+---+
[PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 5f61225..33d1bc5 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = _l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll_l2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2797,6 +2876,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = _core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = _tcm_src.clkr,
[NSSTCM_CLK] = _tcm_clk.clkr,
+ [PLL9] = ,
+ [PLL10] = ,
+ [PLL12] = _l2.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 5f61225..33d1bc5 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = _l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll_l2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2797,6 +2876,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = _core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = _tcm_src.clkr,
[NSSTCM_CLK] = _tcm_clk.clkr,
+ [PLL9] = ,
+ [PLL10] = ,
+ [PLL12] = _l2.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 07/14] clk: qcom: Add support for Krait clocks
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/clk/qcom/clk-krait.c
create mode 100644 drivers/clk/qcom/clk-krait.h
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 21aec10..ada4160 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -280,3 +280,7 @@ config QCOM_HFPLL
Support for the high-frequency PLLs present on Qualcomm devices.
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+ bool
+ select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f82eeac..506c4cf 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
clk-qcom-y += clk-hfpll.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT 8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+ unsigned long flags;
+ u32 regval;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ regval = krait_get_l2_indirect_reg(mux->offset);
+ regval &= ~(mux->mask << mux->shift);
+ regval |= (sel & mux->mask) << mux->shift;
+ if (mux->lpl) {
+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+ }
+ krait_set_l2_indirect_reg(mux->offset, regval);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ /* Wait for switch to complete. */
+ mb();
+ udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = clk_mux_reindex(index, mux->parent_map, 0);
+ mux->en_mask = sel;
+ /* Don't touch mux if CPU is off as it won't work */
+ if (__clk_is_enabled(hw->clk))
+ __krait_mux_set_sel(mux, sel);
+
+ return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = krait_get_l2_indirect_reg(mux->offset);
+ sel >>= mux->shift;
+ sel &= mux->mask;
+ mux->en_mask = sel;
+
+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+ .set_parent = krait_mux_set_parent,
+ .get_parent = krait_mux_get_parent,
+ .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+ return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
+ unsigned long flags;
+ u32 val;
+ u32 mask = BIT(d->width) - 1;
+
+ if (d->lpl)
+ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ val = krait_get_l2_indirect_reg(d->offset);
+ val &= ~mask;
+ krait_set_l2_indirect_reg(d->offset, val);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ return 0;
+}
+
+static unsigned long
+krait_div2
[PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4 files changed, 80 insertions(+), 56 deletions(-)
rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
qcom-nvmem-cpufreq.txt} (99%)
rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (65%)
diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
similarity index 99%
rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c2127b9..6dcdfcd 100644
--- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,7 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
@@ -127,7 +127,7 @@ Example 1:
};
cluster0_opp: opp_table0 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
@@ -338,7 +338,7 @@ Example 1:
};
cluster1_opp: opp_table1 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 52f5f1a..13fbd97 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -124,8 +124,8 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
-config ARM_QCOM_CPUFREQ_KRYO
- tristate "Qualcomm Kryo based CPUFreq"
+config ARM_QCOM_CPUFREQ_NVMEM
+ tristate "Qualcomm nvmem based CPUFreq"
depends on ARM64
depends on QCOM_QFPROM
depends on QCOM_SMEM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index fb4a2ec..551 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
-obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO)+= qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
similarity index 65%
rename from drivers/cpufreq/qcom-cpufreq-kryo.c
rename to drivers/cpufreq/qcom-cpufreq-nvmem.c
index efc9a7a..0ad8e5b 100644
--- a/drivers/cpufreq/qcom-cpufreq-kryo.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -9,7 +9,7 @@
* based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
* defines the voltage and frequency value based on the msm-id in SMEM
* and speedbin blown in the efuse combination.
- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+ * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC
* to provide the OPP framework with required information.
* This is used to determine the voltage and frequency value for each OPP of
* operating-points-v2 table when it is parsed by the OPP framework.
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -42,9 +43,9 @@ enum _msm8996_version {
NUM_OF_MSM8996_VERSIONS,
};
-struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev;
+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
-static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
+static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
{
size_t len;
u32 *msm_id;
@@ -73,34 +74,70 @@ static enu
[PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 7ede744..59f1af4 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
+ mux->reparent = true;
+
return 0;
}
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 441ba1e..9120bd2 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -12,6 +12,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
boollpl;
+ u8 safe_sel;
+ u8 old_index;
+ boolreparent;
struct clk_hw hw;
struct notifier_block clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
};
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+unsigned long event,
+void *data)
+{
+ int ret = 0;
+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+clk_nb);
+ /* Switch to safe parent */
+ if (event == PRE_RATE_CHANGE) {
+ mux->old_index = krait_mux_clk_ops.get_parent(>hw);
+ ret = krait_mux_clk_ops.set_parent(>hw, mux->safe_sel);
+ mux->reparent = false;
+ /*
+* By the time POST_RATE_CHANGE notifier is called,
+* clk framework itself would have changed the parent for the new rate.
+* Only otherwise, put back to the old parent.
+*/
+ } else if (event == POST_RATE_CHANGE) {
+ if (!mux->reparent)
+ ret = krait_mux_clk_ops.set_parent(>hw,
+ mux->old_index);
+ }
+
+ return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+ struct krait_mux_clk *mux)
+{
+ int ret = 0;
+
+ mux->clk_nb.notifier_call = krait_notifier_cb;
+ ret = clk_notifier_register(clk, >clk_nb);
+ if (ret)
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+ return ret;
+}
+
static int
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
@@ -70,6 +113,7 @@
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
+ int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init =
+ mux->safe_sel = 0;
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
err_aux:
@@ -119,6 +169,7 @@
krait_add_pri_mux(struct device *dev, int id, const char *s,
unsigned int offset)
{
+ int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init =
+ mux->safe_sel = 2;
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto err_p3;
+err_p3:
kfree(p_names[2]);
err_p2:
kfree(p_names[1]);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 07/14] clk: qcom: Add support for Krait clocks
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/clk/qcom/clk-krait.c
create mode 100644 drivers/clk/qcom/clk-krait.h
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 21aec10..ada4160 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -280,3 +280,7 @@ config QCOM_HFPLL
Support for the high-frequency PLLs present on Qualcomm devices.
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+ bool
+ select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f82eeac..506c4cf 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
clk-qcom-y += clk-hfpll.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT 8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+ unsigned long flags;
+ u32 regval;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ regval = krait_get_l2_indirect_reg(mux->offset);
+ regval &= ~(mux->mask << mux->shift);
+ regval |= (sel & mux->mask) << mux->shift;
+ if (mux->lpl) {
+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+ }
+ krait_set_l2_indirect_reg(mux->offset, regval);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ /* Wait for switch to complete. */
+ mb();
+ udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = clk_mux_reindex(index, mux->parent_map, 0);
+ mux->en_mask = sel;
+ /* Don't touch mux if CPU is off as it won't work */
+ if (__clk_is_enabled(hw->clk))
+ __krait_mux_set_sel(mux, sel);
+
+ return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = krait_get_l2_indirect_reg(mux->offset);
+ sel >>= mux->shift;
+ sel &= mux->mask;
+ mux->en_mask = sel;
+
+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+ .set_parent = krait_mux_set_parent,
+ .get_parent = krait_mux_get_parent,
+ .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+ return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
+ unsigned long flags;
+ u32 val;
+ u32 mask = BIT(d->width) - 1;
+
+ if (d->lpl)
+ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ val = krait_get_l2_indirect_reg(d->offset);
+ val &= ~mask;
+ krait_set_l2_indirect_reg(d->offset, val);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ return 0;
+}
+
+static unsigned long
+krait_div2
[PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4 files changed, 80 insertions(+), 56 deletions(-)
rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
qcom-nvmem-cpufreq.txt} (99%)
rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (65%)
diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
similarity index 99%
rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c2127b9..6dcdfcd 100644
--- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,7 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
@@ -127,7 +127,7 @@ Example 1:
};
cluster0_opp: opp_table0 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
@@ -338,7 +338,7 @@ Example 1:
};
cluster1_opp: opp_table1 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 52f5f1a..13fbd97 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -124,8 +124,8 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
-config ARM_QCOM_CPUFREQ_KRYO
- tristate "Qualcomm Kryo based CPUFreq"
+config ARM_QCOM_CPUFREQ_NVMEM
+ tristate "Qualcomm nvmem based CPUFreq"
depends on ARM64
depends on QCOM_QFPROM
depends on QCOM_SMEM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index fb4a2ec..551 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
-obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO)+= qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
similarity index 65%
rename from drivers/cpufreq/qcom-cpufreq-kryo.c
rename to drivers/cpufreq/qcom-cpufreq-nvmem.c
index efc9a7a..0ad8e5b 100644
--- a/drivers/cpufreq/qcom-cpufreq-kryo.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -9,7 +9,7 @@
* based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
* defines the voltage and frequency value based on the msm-id in SMEM
* and speedbin blown in the efuse combination.
- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+ * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC
* to provide the OPP framework with required information.
* This is used to determine the voltage and frequency value for each OPP of
* operating-points-v2 table when it is parsed by the OPP framework.
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -42,9 +43,9 @@ enum _msm8996_version {
NUM_OF_MSM8996_VERSIONS,
};
-struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev;
+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
-static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
+static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
{
size_t len;
u32 *msm_id;
@@ -73,34 +74,70 @@ static enu
[PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 7ede744..59f1af4 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
+ mux->reparent = true;
+
return 0;
}
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 441ba1e..9120bd2 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -12,6 +12,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
boollpl;
+ u8 safe_sel;
+ u8 old_index;
+ boolreparent;
struct clk_hw hw;
struct notifier_block clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
};
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+unsigned long event,
+void *data)
+{
+ int ret = 0;
+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+clk_nb);
+ /* Switch to safe parent */
+ if (event == PRE_RATE_CHANGE) {
+ mux->old_index = krait_mux_clk_ops.get_parent(>hw);
+ ret = krait_mux_clk_ops.set_parent(>hw, mux->safe_sel);
+ mux->reparent = false;
+ /*
+* By the time POST_RATE_CHANGE notifier is called,
+* clk framework itself would have changed the parent for the new rate.
+* Only otherwise, put back to the old parent.
+*/
+ } else if (event == POST_RATE_CHANGE) {
+ if (!mux->reparent)
+ ret = krait_mux_clk_ops.set_parent(>hw,
+ mux->old_index);
+ }
+
+ return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+ struct krait_mux_clk *mux)
+{
+ int ret = 0;
+
+ mux->clk_nb.notifier_call = krait_notifier_cb;
+ ret = clk_notifier_register(clk, >clk_nb);
+ if (ret)
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+ return ret;
+}
+
static int
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
@@ -70,6 +113,7 @@
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
+ int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init =
+ mux->safe_sel = 0;
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
err_aux:
@@ -119,6 +169,7 @@
krait_add_pri_mux(struct device *dev, int id, const char *s,
unsigned int offset)
{
+ int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init =
+ mux->safe_sel = 2;
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto err_p3;
+err_p3:
kfree(p_names[2]);
err_p2:
kfree(p_names[1]);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 ++
2 files changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
+- clocks:
+Usage: required
+Value type:
+Definition: reference to the pll parents.
+
+- clock-names:
+Usage: required
+Value type:
+Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: optional
+ Value type:
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
+ CPU number starting at 0.
+
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: should be one of the following. The generic compatible
+ "qcom,kpss-gcc" should also be included.
+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: base address and size of the register region
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the pll parents.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
+ an L2 cache auxiliary clock.
+
+Example:
+
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+ reg = <0x2011000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 ++
2 files changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
+- clocks:
+Usage: required
+Value type:
+Definition: reference to the pll parents.
+
+- clock-names:
+Usage: required
+Value type:
+Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: optional
+ Value type:
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
+ CPU number starting at 0.
+
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: should be one of the following. The generic compatible
+ "qcom,kpss-gcc" should also be included.
+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: base address and size of the register region
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the pll parents.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
+ an L2 cache auxiliary clock.
+
+Example:
+
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+ reg = <0x2011000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
The required OPP related data is determined based on
the efuse value. This is similar to the existing code for
kryo cores. So adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++--
4 files changed, 149 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 6dcdfcd..7bc0f1a 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,8 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
+apq8064, msm8960 and ipq8074.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 13fbd97..497ae89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
config ARM_QCOM_CPUFREQ_NVMEM
tristate "Qualcomm nvmem based CPUFreq"
- depends on ARM64
+ depends on ARCH_QCOM
depends on QCOM_QFPROM
depends on QCOM_SMEM
select PM_OPP
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57..917cdc2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -128,6 +128,11 @@
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+ { .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,apq8064", },
+ { .compatible = "qcom,msm8974", },
+ { .compatible = "qcom,msm8960", },
+
{ }
};
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 0ad8e5b..5f2add0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -45,6 +45,82 @@ enum _msm8996_version {
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse;
+
+ pte_efuse = *((u32 *)buf);
+
+ *speed = pte_efuse & 0xf;
+ if (*speed == 0xf)
+ *speed = (pte_efuse >> 4) & 0xf;
+
+ if (*speed == 0xf) {
+ *speed = 0;
+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
+ } else {
+ pr_info("Speed bin: %d\n", *speed);
+ }
+
+ *pvs = (pte_efuse >> 10) & 0x7;
+ if (*pvs == 0x7)
+ *pvs = (pte_efuse >> 13) & 0x7;
+
+ if (*pvs == 0x7) {
+ *pvs = 0;
+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+ } else {
+ pr_info("PVS bin: %d\n", *pvs);
+ }
+
+ kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse, redundant_sel;
+
+ pte_efuse = *((u32 *)buf);
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+ *speed = pte_efuse & 0x7;
+
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+ switch (redundant_sel) {
+ case 1:
+ *speed = (pte_efuse >> 27) & 0xf;
+ break;
+ case 2:
+ *pvs = (pte_efuse >> 27) & 0xf;
+ break;
+ }
+
+ /* Check SPEED_BIN_BLOW_STATUS */
+ if (pte_efuse & BIT(3)) {
+ pr_info("Speed bin: %d\n", *speed);
+ } else {
+ pr_warn("Speed bin not set. Defaulting to 0!\n");
+ *speed = 0;
+ }
+
+ /* Check PVS_BLOW_STATUS */
+ pte_efuse = *(((u32 *)buf) + 4);
+ pte_efuse &= BIT(21);
+ if (pte_efuse) {
+
[PATCH v12 10/14] clk: qcom: Add Krait clock controller driver
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/krait-cc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7a99627..7c7ca65 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -289,6 +289,14 @@ config KPSS_XCC
if you want to support CPU frequency scaling on devices such
as MSM8960, APQ8064, etc.
+config KRAITCC
+ tristate "Krait Clock Controller"
+ depends on COMMON_CLK_QCOM && ARM
+ select KRAIT_CLOCKS
+ help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 92310ee..949829b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..7ede744 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
- sel = clk_mux_reindex(index, mux->parent_map, 0);
+ sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
sel &= mux->mask;
mux->en_mask = sel;
- return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+ return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
const struct clk_ops krait_mux_clk_ops = {
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+ 2,
+ 0,
+};
+
+static unsigned int pri_mux_map[] = {
+ 1,
+ 2,
+ 0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+ struct krait_div2_clk *div;
+ struct clk_init_data init = {
+ .num_parents = 1,
+ .ops = _div2_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ const char *p_names[1];
+ struct clk *clk;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return -ENOMEM;
+
+ div->width = 2;
+ div->shift = 6;
+ div->lpl = id >= 0;
+ div->offset = offset;
+ div->hw.init =
+
+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+ if (!init.name)
+ return -ENOMEM;
+
+ init.parent_names = p_names;
+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+ if (!p_names[0]) {
+ kfree(init.name);
+ return -ENOMEM;
+ }
+
+ clk = devm_clk_register(dev, >hw);
+ kfree(p_names[0]);
+ kfree(init.name);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+ struct krait_mux_clk *mux;
+ static const char *sec_mux_list[] = {
+ "acpu_aux",
+ "qsb",
+ };
+ struct clk_init_data init = {
+ .parent_names = sec_mux_list,
+ .num_parents = ARRAY_SIZE(sec_mux_list),
+ .ops = _mux_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ struct clk *clk;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ mux->offset = of
[PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
The required OPP related data is determined based on
the efuse value. This is similar to the existing code for
kryo cores. So adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++--
4 files changed, 149 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 6dcdfcd..7bc0f1a 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,8 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
+apq8064, msm8960 and ipq8074.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 13fbd97..497ae89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
config ARM_QCOM_CPUFREQ_NVMEM
tristate "Qualcomm nvmem based CPUFreq"
- depends on ARM64
+ depends on ARCH_QCOM
depends on QCOM_QFPROM
depends on QCOM_SMEM
select PM_OPP
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57..917cdc2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -128,6 +128,11 @@
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+ { .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,apq8064", },
+ { .compatible = "qcom,msm8974", },
+ { .compatible = "qcom,msm8960", },
+
{ }
};
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 0ad8e5b..5f2add0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -45,6 +45,82 @@ enum _msm8996_version {
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse;
+
+ pte_efuse = *((u32 *)buf);
+
+ *speed = pte_efuse & 0xf;
+ if (*speed == 0xf)
+ *speed = (pte_efuse >> 4) & 0xf;
+
+ if (*speed == 0xf) {
+ *speed = 0;
+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
+ } else {
+ pr_info("Speed bin: %d\n", *speed);
+ }
+
+ *pvs = (pte_efuse >> 10) & 0x7;
+ if (*pvs == 0x7)
+ *pvs = (pte_efuse >> 13) & 0x7;
+
+ if (*pvs == 0x7) {
+ *pvs = 0;
+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+ } else {
+ pr_info("PVS bin: %d\n", *pvs);
+ }
+
+ kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse, redundant_sel;
+
+ pte_efuse = *((u32 *)buf);
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+ *speed = pte_efuse & 0x7;
+
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+ switch (redundant_sel) {
+ case 1:
+ *speed = (pte_efuse >> 27) & 0xf;
+ break;
+ case 2:
+ *pvs = (pte_efuse >> 27) & 0xf;
+ break;
+ }
+
+ /* Check SPEED_BIN_BLOW_STATUS */
+ if (pte_efuse & BIT(3)) {
+ pr_info("Speed bin: %d\n", *speed);
+ } else {
+ pr_warn("Speed bin not set. Defaulting to 0!\n");
+ *speed = 0;
+ }
+
+ /* Check PVS_BLOW_STATUS */
+ pte_efuse = *(((u32 *)buf) + 4);
+ pte_efuse &= BIT(21);
+ if (pte_efuse) {
+
[PATCH v12 10/14] clk: qcom: Add Krait clock controller driver
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/krait-cc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7a99627..7c7ca65 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -289,6 +289,14 @@ config KPSS_XCC
if you want to support CPU frequency scaling on devices such
as MSM8960, APQ8064, etc.
+config KRAITCC
+ tristate "Krait Clock Controller"
+ depends on COMMON_CLK_QCOM && ARM
+ select KRAIT_CLOCKS
+ help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 92310ee..949829b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..7ede744 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
- sel = clk_mux_reindex(index, mux->parent_map, 0);
+ sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
sel &= mux->mask;
mux->en_mask = sel;
- return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+ return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
const struct clk_ops krait_mux_clk_ops = {
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+ 2,
+ 0,
+};
+
+static unsigned int pri_mux_map[] = {
+ 1,
+ 2,
+ 0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+ struct krait_div2_clk *div;
+ struct clk_init_data init = {
+ .num_parents = 1,
+ .ops = _div2_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ const char *p_names[1];
+ struct clk *clk;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return -ENOMEM;
+
+ div->width = 2;
+ div->shift = 6;
+ div->lpl = id >= 0;
+ div->offset = offset;
+ div->hw.init =
+
+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+ if (!init.name)
+ return -ENOMEM;
+
+ init.parent_names = p_names;
+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+ if (!p_names[0]) {
+ kfree(init.name);
+ return -ENOMEM;
+ }
+
+ clk = devm_clk_register(dev, >hw);
+ kfree(p_names[0]);
+ kfree(init.name);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+ struct krait_mux_clk *mux;
+ static const char *sec_mux_list[] = {
+ "acpu_aux",
+ "qsb",
+ };
+ struct clk_init_data init = {
+ .parent_names = sec_mux_list,
+ .num_parents = ARRAY_SIZE(sec_mux_list),
+ .ops = _mux_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ struct clk *clk;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ mux->offset = of
[PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/kpss-xcc.c | 87 +
3 files changed, 96 insertions(+)
create mode 100644 drivers/clk/qcom/kpss-xcc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ada4160..7a99627 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -281,6 +281,14 @@ config QCOM_HFPLL
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+config KPSS_XCC
+ tristate "KPSS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 506c4cf..92310ee 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const char *aux_parents[] = {
+ "pll8_vote",
+ "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+ 3,
+ 0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+ { .compatible = "qcom,kpss-gcc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, >dev);
+ if (!id)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (id->data) {
+ if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, ))
+ return -ENODEV;
+ base += 0x14;
+ } else {
+ name = "acpu_l2_aux";
+ base += 0x28;
+ }
+
+ clk = clk_register_mux_table(>dev, name, aux_parents,
+ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+0, aux_parent_map, NULL);
+
+ platform_set_drvdata(pdev, clk);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+ clk_unregister_mux(platform_get_drvdata(pdev));
+ return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+ .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
+ },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/kpss-xcc.c | 87 +
3 files changed, 96 insertions(+)
create mode 100644 drivers/clk/qcom/kpss-xcc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ada4160..7a99627 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -281,6 +281,14 @@ config QCOM_HFPLL
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+config KPSS_XCC
+ tristate "KPSS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 506c4cf..92310ee 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const char *aux_parents[] = {
+ "pll8_vote",
+ "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+ 3,
+ 0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+ { .compatible = "qcom,kpss-gcc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, >dev);
+ if (!id)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (id->data) {
+ if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, ))
+ return -ENODEV;
+ base += 0x14;
+ } else {
+ name = "acpu_l2_aux";
+ base += 0x28;
+ }
+
+ clk = clk_register_mux_table(>dev, name, aux_parents,
+ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+0, aux_parent_map, NULL);
+
+ platform_set_drvdata(pdev, clk);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+ clk_unregister_mux(platform_get_drvdata(pdev));
+ return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+ .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
+ },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 000..030ba60
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,34 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: must be one of:
+ "qcom,krait-cc-v1"
+ "qcom,krait-cc-v2"
+
+- #clock-cells:
+ Usage: required
+ Value type:
+ Definition: must be 1
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the clock parents of hfpll, secondary muxes.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
+
+Example:
+
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <>, <>, <_aux>, <_aux>,
;
+ clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux",
"qsb";
+ #clock-cells = <1>;
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 000..030ba60
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,34 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: must be one of:
+ "qcom,krait-cc-v1"
+ "qcom,krait-cc-v2"
+
+- #clock-cells:
+ Usage: required
+ Value type:
+ Definition: must be 1
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the clock parents of hfpll, secondary muxes.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
+
+Example:
+
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <>, <>, <_aux>, <_aux>,
;
+ clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux",
"qsb";
+ #clock-cells = <1>;
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 000..ec02a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,60 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: :
+ shall contain only one of the following. The generic
+ compatible "qcom,hfpll" should be also included.
+
+"qcom,hfpll-ipq8064", "qcom,hfpll"
+"qcom,hfpll-apq8064", "qcom,hfpll"
+"qcom,hfpll-msm8974", "qcom,hfpll"
+"qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: address and size of HPLL registers. An optional second
+ element specifies the address and size of the alias
+ register region.
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the xo clock.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "xo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+ starting at 0. Otherwise hfpll_Y where Y is more specific
+ such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+ clock-controller@f9016000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf9016000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll_l2";
+ };
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+ clock-controller@f908a000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll0";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 01/14] ARM: Add Krait L2 register accessor functions
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland
Cc: Russell King
Acked-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
arch/arm/common/Kconfig | 3 ++
arch/arm/common/Makefile | 1 +
arch/arm/common/krait-l2-accessors.c | 48 +++
arch/arm/include/asm/krait-l2-accessors.h | 9 ++
4 files changed, 61 insertions(+)
create mode 100644 arch/arm/common/krait-l2-accessors.c
create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index e5ad070..c8e1986 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,6 +7,9 @@ config DMABOUNCE
bool
select ZONE_DMA
+config KRAIT_L2_ACCESSORS
+ bool
+
config SHARP_LOCOMO
bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3157be4..219a260 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -7,6 +7,7 @@ obj-y += firmware.o
obj-$(CONFIG_SA) += sa.o
obj-$(CONFIG_DMABOUNCE)+= dmabounce.o
+obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
diff --git a/arch/arm/common/krait-l2-accessors.c
b/arch/arm/common/krait-l2-accessors.c
new file mode 100644
index 000..9a97dda
--- /dev/null
+++ b/arch/arm/common/krait-l2-accessors.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+
+#include
+#include
+
+static DEFINE_RAW_SPINLOCK(krait_l2_lock);
+
+void krait_set_l2_indirect_reg(u32 addr, u32 val)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_l2_lock, flags);
+ /*
+* Select the L2 window by poking l2cpselr, then write to the window
+* via l2cpdr.
+*/
+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+ isb();
+ asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
+ isb();
+
+ raw_spin_unlock_irqrestore(_l2_lock, flags);
+}
+EXPORT_SYMBOL(krait_set_l2_indirect_reg);
+
+u32 krait_get_l2_indirect_reg(u32 addr)
+{
+ u32 val;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_l2_lock, flags);
+ /*
+* Select the L2 window by poking l2cpselr, then read from the window
+* via l2cpdr.
+*/
+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+ isb();
+ asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
+
+ raw_spin_unlock_irqrestore(_l2_lock, flags);
+
+ return val;
+}
+EXPORT_SYMBOL(krait_get_l2_indirect_reg);
diff --git a/arch/arm/include/asm/krait-l2-accessors.h
b/arch/arm/include/asm/krait-l2-accessors.h
new file mode 100644
index 000..a5f2cdd
--- /dev/null
+++ b/arch/arm/include/asm/krait-l2-accessors.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
+#define __ASMARM_KRAIT_L2_ACCESSORS_H
+
+extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
+extern u32 krait_get_l2_indirect_reg(u32 addr);
+
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed, 174 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index fd495e0..3994747 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3254,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+ .mode_reg = 0x3280,
+ .l_reg = 0x3288,
+ .m_reg = 0x328c,
+ .n_reg = 0x3290,
+ .config_reg = 0x3284,
+ .status_reg = 0x329c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3294,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+ .mode_reg = 0x32c0,
+ .l_reg = 0x32c8,
+ .m_reg = 0x32cc,
+ .n_reg = 0x32d0,
+ .config_reg = 0x32c4,
+ .status_reg = 0x32dc,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x32d4,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll3",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3400,
+ .l_reg = 0x3408,
+ .m_reg = 0x340c,
+ .n_reg = 0x3410,
+ .config_reg = 0x3404,
+ .status_reg = 0x341c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3414,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+
[PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 000..ec02a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,60 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: :
+ shall contain only one of the following. The generic
+ compatible "qcom,hfpll" should be also included.
+
+"qcom,hfpll-ipq8064", "qcom,hfpll"
+"qcom,hfpll-apq8064", "qcom,hfpll"
+"qcom,hfpll-msm8974", "qcom,hfpll"
+"qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: address and size of HPLL registers. An optional second
+ element specifies the address and size of the alias
+ register region.
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the xo clock.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "xo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+ starting at 0. Otherwise hfpll_Y where Y is more specific
+ such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+ clock-controller@f9016000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf9016000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll_l2";
+ };
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+ clock-controller@f908a000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll0";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 01/14] ARM: Add Krait L2 register accessor functions
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland
Cc: Russell King
Acked-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
arch/arm/common/Kconfig | 3 ++
arch/arm/common/Makefile | 1 +
arch/arm/common/krait-l2-accessors.c | 48 +++
arch/arm/include/asm/krait-l2-accessors.h | 9 ++
4 files changed, 61 insertions(+)
create mode 100644 arch/arm/common/krait-l2-accessors.c
create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index e5ad070..c8e1986 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,6 +7,9 @@ config DMABOUNCE
bool
select ZONE_DMA
+config KRAIT_L2_ACCESSORS
+ bool
+
config SHARP_LOCOMO
bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3157be4..219a260 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -7,6 +7,7 @@ obj-y += firmware.o
obj-$(CONFIG_SA) += sa.o
obj-$(CONFIG_DMABOUNCE)+= dmabounce.o
+obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
diff --git a/arch/arm/common/krait-l2-accessors.c
b/arch/arm/common/krait-l2-accessors.c
new file mode 100644
index 000..9a97dda
--- /dev/null
+++ b/arch/arm/common/krait-l2-accessors.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+
+#include
+#include
+
+static DEFINE_RAW_SPINLOCK(krait_l2_lock);
+
+void krait_set_l2_indirect_reg(u32 addr, u32 val)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_l2_lock, flags);
+ /*
+* Select the L2 window by poking l2cpselr, then write to the window
+* via l2cpdr.
+*/
+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+ isb();
+ asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
+ isb();
+
+ raw_spin_unlock_irqrestore(_l2_lock, flags);
+}
+EXPORT_SYMBOL(krait_set_l2_indirect_reg);
+
+u32 krait_get_l2_indirect_reg(u32 addr)
+{
+ u32 val;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_l2_lock, flags);
+ /*
+* Select the L2 window by poking l2cpselr, then read from the window
+* via l2cpdr.
+*/
+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+ isb();
+ asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
+
+ raw_spin_unlock_irqrestore(_l2_lock, flags);
+
+ return val;
+}
+EXPORT_SYMBOL(krait_get_l2_indirect_reg);
diff --git a/arch/arm/include/asm/krait-l2-accessors.h
b/arch/arm/include/asm/krait-l2-accessors.h
new file mode 100644
index 000..a5f2cdd
--- /dev/null
+++ b/arch/arm/include/asm/krait-l2-accessors.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
+#define __ASMARM_KRAIT_L2_ACCESSORS_H
+
+extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
+extern u32 krait_get_l2_indirect_reg(u32 addr);
+
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed, 174 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index fd495e0..3994747 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3254,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+ .mode_reg = 0x3280,
+ .l_reg = 0x3288,
+ .m_reg = 0x328c,
+ .n_reg = 0x3290,
+ .config_reg = 0x3284,
+ .status_reg = 0x329c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3294,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+ .mode_reg = 0x32c0,
+ .l_reg = 0x32c8,
+ .m_reg = 0x32cc,
+ .n_reg = 0x32d0,
+ .config_reg = 0x32c4,
+ .status_reg = 0x32dc,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x32d4,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll3",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3400,
+ .l_reg = 0x3408,
+ .m_reg = 0x340c,
+ .n_reg = 0x3410,
+ .config_reg = 0x3404,
+ .status_reg = 0x341c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3414,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+
[PATCH v12 03/14] clk: qcom: Add HFPLL driver
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0647686..21aec10 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV
Technologies, Inc. SPMI PMIC. It configures the frequency of
clkdiv outputs of the PMIC. These clocks are typically wired
through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the high-frequency PLLs present on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as MSM8974, APQ8084, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7818e6c..f82eeac 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
new file mode 100644
index 000..a6de7101
--- /dev/null
+++ b/drivers/clk/qcom/hfpll.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+static const struct hfpll_data hdata = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x430405d,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .user_val = 0x8,
+ .user_vco_mask = 0x10,
+ .low_vco_max_rate = 124800,
+ .min_rate = 53760UL,
+ .max_rate = 29UL,
+};
+
+static const struct of_device_id qcom_hfpll_match_table[] = {
+ { .compatible = "qcom,hfpll" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+
+static const struct regmap_config hfpll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x30,
+ .fast_io= true,
+};
+
+static int qcom_hfpll_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = >dev;
+ void __iomem *base;
+ struct regmap *regmap;
+ struct clk_hfpll *h;
+ struct clk_init_data init = {
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = _ops_hfpll,
+ };
+
+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
+ if (!h)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(>dev, base, _regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
+ 0, ))
+ return -ENODEV;
+
+ h->d =
+ h->clkr.hw.init =
+ spin_lock_init(>lock);
+
+ return devm_clk_register_regmap(>dev, >clkr);
+}
+
+static struct platform_driver qcom_hfpll_driver = {
+ .probe = qcom_hfpll_probe,
+ .driver = {
+ .name = "qcom-hfpll",
+ .of_match_table = qcom_hfpll_match_table,
+ },
+};
+module_platform_driver(qcom_hfpll_driver);
+
+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-hfpll");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/clk-hfpll.h | 44
3 files changed, 289 insertions(+)
create mode 100644 drivers/clk/qcom/clk-hfpll.c
create mode 100644 drivers/clk/qcom/clk-hfpll.h
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 21a4503..7818e6c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-y += clk-hfpll.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
new file mode 100644
index 000..3c04805
--- /dev/null
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+#define PLL_OUTCTRLBIT(0)
+#define PLL_BYPASSNL BIT(1)
+#define PLL_RESET_NBIT(2)
+
+/* Initialize a HFPLL at a given rate and enable it. */
+static void __clk_hfpll_init_once(struct clk_hw *hw)
+{
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+
+ if (likely(h->init_done))
+ return;
+
+ /* Configure PLL parameters for integer mode. */
+ if (hd->config_val)
+ regmap_write(regmap, hd->config_reg, hd->config_val);
+ regmap_write(regmap, hd->m_reg, 0);
+ regmap_write(regmap, hd->n_reg, 1);
+
+ if (hd->user_reg) {
+ u32 regval = hd->user_val;
+ unsigned long rate;
+
+ rate = clk_hw_get_rate(hw);
+
+ /* Pick the right VCO. */
+ if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
+ regval |= hd->user_vco_mask;
+ regmap_write(regmap, hd->user_reg, regval);
+ }
+
+ if (hd->droop_reg)
+ regmap_write(regmap, hd->droop_reg, hd->droop_val);
+
+ h->init_done = true;
+}
+
+static void __clk_hfpll_enable(struct clk_hw *hw)
+{
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+ u32 val;
+
+ __clk_hfpll_init_once(hw);
+
+ /* Disable PLL bypass mode. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
+
+ /*
+* H/W requires a 5us delay between disabling the bypass and
+* de-asserting the reset. Delay 10us just to be safe.
+*/
+ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
+
+ /* Wait for PLL to lock. */
+ if (hd->status_reg) {
+ do {
+ regmap_read(regmap, hd->status_reg, );
+ } while (!(val & BIT(hd->lock_bit)));
+ } else {
+ udelay(60);
+ }
+
+ /* Enable PLL output. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
+}
+
+/* Enable an already-configured HFPLL. */
+static int clk_hfpll_enable(struct clk_hw *hw)
+{
+ unsigned long flags;
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+ u32 mode;
+
+ spin_lock_irqsave(>lock, flags);
+ regmap_read(regmap, hd->mode_reg, );
+ if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
+ __clk_hfpll_enable(hw);
+ spin_unlock_irqrestore(>lock, flags);
+
+ return 0;
+}
+
+static void __clk_hfpll_disable(struct clk_hfpll *h)
+{
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+
+ /*
+* Disable the PLL output, disable test mode, enable the bypass mode,
+* and assert the reset.
+*/
+ regmap_update_bits(regmap, hd->mode_reg,
+ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
+}
+
+static void clk_hfpll_disable(struct clk_hw *hw)
+{
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(>lock, flags);
+ __clk_hfpll_disable(h);
+ spin_unlock_irqrestore(>lock, flags);
+}
+
+static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
+
[PATCH V12 00/14] Krait clocks + Krait CPUfreq
rates we can't leave the CPU clocked by the HFPLL because
we need to turn off the output of the PLL when changing its frequency.
This means we have to switch over to the secondary mux and use one of the
fixed sources. This is why we need something like the safe parent patch.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
based qcom socs
cpufreq: qcom: Add support for krait based socs
Stephen Boyd (11):
ARM: Add Krait L2 register accessor functions
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
clk: qcom: Add HFPLL driver
dt-bindings: clock: Document qcom,hfpll
clk: qcom: Add MSM8960/APQ8064's HFPLLs
clk: qcom: Add IPQ806X's HFPLLs
clk: qcom: Add support for Krait clocks
clk: qcom: Add KPSS ACC/GCC driver
dt-bindings: arm: Document qcom,kpss-gcc
clk: qcom: Add Krait clock controller driver
dt-bindings: clock: Document qcom,krait-cc
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 +
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++
.../devicetree/bindings/clock/qcom,hfpll.txt | 60
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 7 +-
arch/arm/common/Kconfig| 3 +
arch/arm/common/Makefile | 1 +
arch/arm/common/krait-l2-accessors.c | 48 +++
arch/arm/include/asm/krait-l2-accessors.h | 9 +
drivers/clk/qcom/Kconfig | 28 ++
drivers/clk/qcom/Makefile | 5 +
drivers/clk/qcom/clk-hfpll.c | 244 +
drivers/clk/qcom/clk-hfpll.h | 44 +++
drivers/clk/qcom/clk-krait.c | 126 +++
drivers/clk/qcom/clk-krait.h | 40 +++
drivers/clk/qcom/gcc-ipq806x.c | 82 +
drivers/clk/qcom/gcc-msm8960.c | 172 +
drivers/clk/qcom/hfpll.c | 96 +
drivers/clk/qcom/kpss-xcc.c| 87 +
drivers/clk/qcom/krait-cc.c| 397 +
drivers/cpufreq/Kconfig.arm| 6 +-
drivers/cpufreq/Makefile | 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-kryo.c| 232
drivers/cpufreq/qcom-cpufreq-nvmem.c | 387
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
26 files changed, 1941 insertions(+), 239 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
qcom-nvmem-cpufreq.txt} (98%)
create mode 100644 arch/arm/common/krait-l2-accessors.c
create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
create mode 100644 drivers/clk/qcom/clk-hfpll.c
create mode 100644 drivers/clk/qcom/clk-hfpll.h
create mode 100644 drivers/clk/qcom/clk-krait.c
create mode 100644 drivers/clk/qcom/clk-krait.h
create mode 100644 drivers/clk/qcom/hfpll.c
create mode 100644 drivers/clk/qcom/kpss-xcc.c
create mode 100644 drivers/clk/qcom/krait-cc.c
delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 03/14] clk: qcom: Add HFPLL driver
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0647686..21aec10 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV
Technologies, Inc. SPMI PMIC. It configures the frequency of
clkdiv outputs of the PMIC. These clocks are typically wired
through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the high-frequency PLLs present on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as MSM8974, APQ8084, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7818e6c..f82eeac 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
new file mode 100644
index 000..a6de7101
--- /dev/null
+++ b/drivers/clk/qcom/hfpll.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+static const struct hfpll_data hdata = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x430405d,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .user_val = 0x8,
+ .user_vco_mask = 0x10,
+ .low_vco_max_rate = 124800,
+ .min_rate = 53760UL,
+ .max_rate = 29UL,
+};
+
+static const struct of_device_id qcom_hfpll_match_table[] = {
+ { .compatible = "qcom,hfpll" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+
+static const struct regmap_config hfpll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x30,
+ .fast_io= true,
+};
+
+static int qcom_hfpll_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = >dev;
+ void __iomem *base;
+ struct regmap *regmap;
+ struct clk_hfpll *h;
+ struct clk_init_data init = {
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = _ops_hfpll,
+ };
+
+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
+ if (!h)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(>dev, base, _regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
+ 0, ))
+ return -ENODEV;
+
+ h->d =
+ h->clkr.hw.init =
+ spin_lock_init(>lock);
+
+ return devm_clk_register_regmap(>dev, >clkr);
+}
+
+static struct platform_driver qcom_hfpll_driver = {
+ .probe = qcom_hfpll_probe,
+ .driver = {
+ .name = "qcom-hfpll",
+ .of_match_table = qcom_hfpll_match_table,
+ },
+};
+module_platform_driver(qcom_hfpll_driver);
+
+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-hfpll");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/clk-hfpll.h | 44
3 files changed, 289 insertions(+)
create mode 100644 drivers/clk/qcom/clk-hfpll.c
create mode 100644 drivers/clk/qcom/clk-hfpll.h
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 21a4503..7818e6c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-y += clk-hfpll.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
new file mode 100644
index 000..3c04805
--- /dev/null
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+#define PLL_OUTCTRLBIT(0)
+#define PLL_BYPASSNL BIT(1)
+#define PLL_RESET_NBIT(2)
+
+/* Initialize a HFPLL at a given rate and enable it. */
+static void __clk_hfpll_init_once(struct clk_hw *hw)
+{
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+
+ if (likely(h->init_done))
+ return;
+
+ /* Configure PLL parameters for integer mode. */
+ if (hd->config_val)
+ regmap_write(regmap, hd->config_reg, hd->config_val);
+ regmap_write(regmap, hd->m_reg, 0);
+ regmap_write(regmap, hd->n_reg, 1);
+
+ if (hd->user_reg) {
+ u32 regval = hd->user_val;
+ unsigned long rate;
+
+ rate = clk_hw_get_rate(hw);
+
+ /* Pick the right VCO. */
+ if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
+ regval |= hd->user_vco_mask;
+ regmap_write(regmap, hd->user_reg, regval);
+ }
+
+ if (hd->droop_reg)
+ regmap_write(regmap, hd->droop_reg, hd->droop_val);
+
+ h->init_done = true;
+}
+
+static void __clk_hfpll_enable(struct clk_hw *hw)
+{
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+ u32 val;
+
+ __clk_hfpll_init_once(hw);
+
+ /* Disable PLL bypass mode. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
+
+ /*
+* H/W requires a 5us delay between disabling the bypass and
+* de-asserting the reset. Delay 10us just to be safe.
+*/
+ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
+
+ /* Wait for PLL to lock. */
+ if (hd->status_reg) {
+ do {
+ regmap_read(regmap, hd->status_reg, );
+ } while (!(val & BIT(hd->lock_bit)));
+ } else {
+ udelay(60);
+ }
+
+ /* Enable PLL output. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
+}
+
+/* Enable an already-configured HFPLL. */
+static int clk_hfpll_enable(struct clk_hw *hw)
+{
+ unsigned long flags;
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+ u32 mode;
+
+ spin_lock_irqsave(>lock, flags);
+ regmap_read(regmap, hd->mode_reg, );
+ if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
+ __clk_hfpll_enable(hw);
+ spin_unlock_irqrestore(>lock, flags);
+
+ return 0;
+}
+
+static void __clk_hfpll_disable(struct clk_hfpll *h)
+{
+ struct hfpll_data const *hd = h->d;
+ struct regmap *regmap = h->clkr.regmap;
+
+ /*
+* Disable the PLL output, disable test mode, enable the bypass mode,
+* and assert the reset.
+*/
+ regmap_update_bits(regmap, hd->mode_reg,
+ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
+}
+
+static void clk_hfpll_disable(struct clk_hw *hw)
+{
+ struct clk_hfpll *h = to_clk_hfpll(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(>lock, flags);
+ __clk_hfpll_disable(h);
+ spin_unlock_irqrestore(>lock, flags);
+}
+
+static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
+
[PATCH V12 00/14] Krait clocks + Krait CPUfreq
rates we can't leave the CPU clocked by the HFPLL because
we need to turn off the output of the PLL when changing its frequency.
This means we have to switch over to the secondary mux and use one of the
fixed sources. This is why we need something like the safe parent patch.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
based qcom socs
cpufreq: qcom: Add support for krait based socs
Stephen Boyd (11):
ARM: Add Krait L2 register accessor functions
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
clk: qcom: Add HFPLL driver
dt-bindings: clock: Document qcom,hfpll
clk: qcom: Add MSM8960/APQ8064's HFPLLs
clk: qcom: Add IPQ806X's HFPLLs
clk: qcom: Add support for Krait clocks
clk: qcom: Add KPSS ACC/GCC driver
dt-bindings: arm: Document qcom,kpss-gcc
clk: qcom: Add Krait clock controller driver
dt-bindings: clock: Document qcom,krait-cc
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 +
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++
.../devicetree/bindings/clock/qcom,hfpll.txt | 60
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 7 +-
arch/arm/common/Kconfig| 3 +
arch/arm/common/Makefile | 1 +
arch/arm/common/krait-l2-accessors.c | 48 +++
arch/arm/include/asm/krait-l2-accessors.h | 9 +
drivers/clk/qcom/Kconfig | 28 ++
drivers/clk/qcom/Makefile | 5 +
drivers/clk/qcom/clk-hfpll.c | 244 +
drivers/clk/qcom/clk-hfpll.h | 44 +++
drivers/clk/qcom/clk-krait.c | 126 +++
drivers/clk/qcom/clk-krait.h | 40 +++
drivers/clk/qcom/gcc-ipq806x.c | 82 +
drivers/clk/qcom/gcc-msm8960.c | 172 +
drivers/clk/qcom/hfpll.c | 96 +
drivers/clk/qcom/kpss-xcc.c| 87 +
drivers/clk/qcom/krait-cc.c| 397 +
drivers/cpufreq/Kconfig.arm| 6 +-
drivers/cpufreq/Makefile | 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-kryo.c| 232
drivers/cpufreq/qcom-cpufreq-nvmem.c | 387
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
26 files changed, 1941 insertions(+), 239 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
qcom-nvmem-cpufreq.txt} (98%)
create mode 100644 arch/arm/common/krait-l2-accessors.c
create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
create mode 100644 drivers/clk/qcom/clk-hfpll.c
create mode 100644 drivers/clk/qcom/clk-hfpll.h
create mode 100644 drivers/clk/qcom/clk-krait.c
create mode 100644 drivers/clk/qcom/clk-krait.h
create mode 100644 drivers/clk/qcom/hfpll.c
create mode 100644 drivers/clk/qcom/kpss-xcc.c
create mode 100644 drivers/clk/qcom/krait-cc.c
delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4 files changed, 80 insertions(+), 56 deletions(-)
rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
qcom-nvmem-cpufreq.txt} (99%)
rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (65%)
diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
similarity index 99%
rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c2127b9..6dcdfcd 100644
--- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,7 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
@@ -127,7 +127,7 @@ Example 1:
};
cluster0_opp: opp_table0 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
@@ -338,7 +338,7 @@ Example 1:
};
cluster1_opp: opp_table1 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 52f5f1a..13fbd97 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -124,8 +124,8 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
-config ARM_QCOM_CPUFREQ_KRYO
- tristate "Qualcomm Kryo based CPUFreq"
+config ARM_QCOM_CPUFREQ_NVMEM
+ tristate "Qualcomm nvmem based CPUFreq"
depends on ARM64
depends on QCOM_QFPROM
depends on QCOM_SMEM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index fb4a2ec..551 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
-obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO)+= qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
similarity index 65%
rename from drivers/cpufreq/qcom-cpufreq-kryo.c
rename to drivers/cpufreq/qcom-cpufreq-nvmem.c
index efc9a7a..0ad8e5b 100644
--- a/drivers/cpufreq/qcom-cpufreq-kryo.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -9,7 +9,7 @@
* based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
* defines the voltage and frequency value based on the msm-id in SMEM
* and speedbin blown in the efuse combination.
- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+ * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC
* to provide the OPP framework with required information.
* This is used to determine the voltage and frequency value for each OPP of
* operating-points-v2 table when it is parsed by the OPP framework.
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -42,9 +43,9 @@ enum _msm8996_version {
NUM_OF_MSM8996_VERSIONS,
};
-struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev;
+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
-static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
+static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
{
size_t len;
u32 *msm_id;
@@ -73,34 +74,70 @@ static enu
[PATCH 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4 files changed, 80 insertions(+), 56 deletions(-)
rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
qcom-nvmem-cpufreq.txt} (99%)
rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (65%)
diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
similarity index 99%
rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c2127b9..6dcdfcd 100644
--- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,7 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
@@ -127,7 +127,7 @@ Example 1:
};
cluster0_opp: opp_table0 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
@@ -338,7 +338,7 @@ Example 1:
};
cluster1_opp: opp_table1 {
- compatible = "operating-points-v2-kryo-cpu";
+ compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <_efuse>;
opp-shared;
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 52f5f1a..13fbd97 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -124,8 +124,8 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
-config ARM_QCOM_CPUFREQ_KRYO
- tristate "Qualcomm Kryo based CPUFreq"
+config ARM_QCOM_CPUFREQ_NVMEM
+ tristate "Qualcomm nvmem based CPUFreq"
depends on ARM64
depends on QCOM_QFPROM
depends on QCOM_SMEM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index fb4a2ec..551 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
-obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO)+= qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
similarity index 65%
rename from drivers/cpufreq/qcom-cpufreq-kryo.c
rename to drivers/cpufreq/qcom-cpufreq-nvmem.c
index efc9a7a..0ad8e5b 100644
--- a/drivers/cpufreq/qcom-cpufreq-kryo.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -9,7 +9,7 @@
* based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
* defines the voltage and frequency value based on the msm-id in SMEM
* and speedbin blown in the efuse combination.
- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+ * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC
* to provide the OPP framework with required information.
* This is used to determine the voltage and frequency value for each OPP of
* operating-points-v2 table when it is parsed by the OPP framework.
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -42,9 +43,9 @@ enum _msm8996_version {
NUM_OF_MSM8996_VERSIONS,
};
-struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev;
+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
-static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
+static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
{
size_t len;
u32 *msm_id;
@@ -73,34 +74,70 @@ static enu
[PATCH 14/14] cpufreq: qcom: Add support for krait based socs
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
The required OPP related data is determined based on
the efuse value. This is similar to the existing code for
kryo cores. So adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++--
4 files changed, 149 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 6dcdfcd..7bc0f1a 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,8 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
+apq8064, msm8960 and ipq8074.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 13fbd97..497ae89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
config ARM_QCOM_CPUFREQ_NVMEM
tristate "Qualcomm nvmem based CPUFreq"
- depends on ARM64
+ depends on ARCH_QCOM
depends on QCOM_QFPROM
depends on QCOM_SMEM
select PM_OPP
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57..917cdc2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -128,6 +128,11 @@
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+ { .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,apq8064", },
+ { .compatible = "qcom,msm8974", },
+ { .compatible = "qcom,msm8960", },
+
{ }
};
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 0ad8e5b..5f2add0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -45,6 +45,82 @@ enum _msm8996_version {
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse;
+
+ pte_efuse = *((u32 *)buf);
+
+ *speed = pte_efuse & 0xf;
+ if (*speed == 0xf)
+ *speed = (pte_efuse >> 4) & 0xf;
+
+ if (*speed == 0xf) {
+ *speed = 0;
+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
+ } else {
+ pr_info("Speed bin: %d\n", *speed);
+ }
+
+ *pvs = (pte_efuse >> 10) & 0x7;
+ if (*pvs == 0x7)
+ *pvs = (pte_efuse >> 13) & 0x7;
+
+ if (*pvs == 0x7) {
+ *pvs = 0;
+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+ } else {
+ pr_info("PVS bin: %d\n", *pvs);
+ }
+
+ kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse, redundant_sel;
+
+ pte_efuse = *((u32 *)buf);
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+ *speed = pte_efuse & 0x7;
+
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+ switch (redundant_sel) {
+ case 1:
+ *speed = (pte_efuse >> 27) & 0xf;
+ break;
+ case 2:
+ *pvs = (pte_efuse >> 27) & 0xf;
+ break;
+ }
+
+ /* Check SPEED_BIN_BLOW_STATUS */
+ if (pte_efuse & BIT(3)) {
+ pr_info("Speed bin: %d\n", *speed);
+ } else {
+ pr_warn("Speed bin not set. Defaulting to 0!\n");
+ *speed = 0;
+ }
+
+ /* Check PVS_BLOW_STATUS */
+ pte_efuse = *(((u32 *)buf) + 4);
+ pte_efuse &= BIT(21);
+ if (pte_efuse) {
+
[PATCH 14/14] cpufreq: qcom: Add support for krait based socs
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
The required OPP related data is determined based on
the efuse value. This is similar to the existing code for
kryo cores. So adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++--
4 files changed, 149 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 6dcdfcd..7bc0f1a 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,8 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
+ - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
+apq8064, msm8960 and ipq8074.
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 13fbd97..497ae89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
config ARM_QCOM_CPUFREQ_NVMEM
tristate "Qualcomm nvmem based CPUFreq"
- depends on ARM64
+ depends on ARCH_QCOM
depends on QCOM_QFPROM
depends on QCOM_SMEM
select PM_OPP
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57..917cdc2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -128,6 +128,11 @@
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+ { .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,apq8064", },
+ { .compatible = "qcom,msm8974", },
+ { .compatible = "qcom,msm8960", },
+
{ }
};
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c
b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 0ad8e5b..5f2add0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -45,6 +45,82 @@ enum _msm8996_version {
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse;
+
+ pte_efuse = *((u32 *)buf);
+
+ *speed = pte_efuse & 0xf;
+ if (*speed == 0xf)
+ *speed = (pte_efuse >> 4) & 0xf;
+
+ if (*speed == 0xf) {
+ *speed = 0;
+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
+ } else {
+ pr_info("Speed bin: %d\n", *speed);
+ }
+
+ *pvs = (pte_efuse >> 10) & 0x7;
+ if (*pvs == 0x7)
+ *pvs = (pte_efuse >> 13) & 0x7;
+
+ if (*pvs == 0x7) {
+ *pvs = 0;
+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+ } else {
+ pr_info("PVS bin: %d\n", *pvs);
+ }
+
+ kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+ u32 pte_efuse, redundant_sel;
+
+ pte_efuse = *((u32 *)buf);
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+ *speed = pte_efuse & 0x7;
+
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+ switch (redundant_sel) {
+ case 1:
+ *speed = (pte_efuse >> 27) & 0xf;
+ break;
+ case 2:
+ *pvs = (pte_efuse >> 27) & 0xf;
+ break;
+ }
+
+ /* Check SPEED_BIN_BLOW_STATUS */
+ if (pte_efuse & BIT(3)) {
+ pr_info("Speed bin: %d\n", *speed);
+ } else {
+ pr_warn("Speed bin not set. Defaulting to 0!\n");
+ *speed = 0;
+ }
+
+ /* Check PVS_BLOW_STATUS */
+ pte_efuse = *(((u32 *)buf) + 4);
+ pte_efuse &= BIT(21);
+ if (pte_efuse) {
+
[PATCH 12/14] clk: qcom: Add safe switch hook for krait mux clocks
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 7ede744..59f1af4 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
+ mux->reparent = true;
+
return 0;
}
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 441ba1e..9120bd2 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -12,6 +12,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
boollpl;
+ u8 safe_sel;
+ u8 old_index;
+ boolreparent;
struct clk_hw hw;
struct notifier_block clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
};
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+unsigned long event,
+void *data)
+{
+ int ret = 0;
+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+clk_nb);
+ /* Switch to safe parent */
+ if (event == PRE_RATE_CHANGE) {
+ mux->old_index = krait_mux_clk_ops.get_parent(>hw);
+ ret = krait_mux_clk_ops.set_parent(>hw, mux->safe_sel);
+ mux->reparent = false;
+ /*
+* By the time POST_RATE_CHANGE notifier is called,
+* clk framework itself would have changed the parent for the new rate.
+* Only otherwise, put back to the old parent.
+*/
+ } else if (event == POST_RATE_CHANGE) {
+ if (!mux->reparent)
+ ret = krait_mux_clk_ops.set_parent(>hw,
+ mux->old_index);
+ }
+
+ return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+ struct krait_mux_clk *mux)
+{
+ int ret = 0;
+
+ mux->clk_nb.notifier_call = krait_notifier_cb;
+ ret = clk_notifier_register(clk, >clk_nb);
+ if (ret)
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+ return ret;
+}
+
static int
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
@@ -70,6 +113,7 @@
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
+ int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init =
+ mux->safe_sel = 0;
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
err_aux:
@@ -119,6 +169,7 @@
krait_add_pri_mux(struct device *dev, int id, const char *s,
unsigned int offset)
{
+ int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init =
+ mux->safe_sel = 2;
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto err_p3;
+err_p3:
kfree(p_names[2]);
err_p2:
kfree(p_names[1]);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 12/14] clk: qcom: Add safe switch hook for krait mux clocks
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 7ede744..59f1af4 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
+ mux->reparent = true;
+
return 0;
}
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 441ba1e..9120bd2 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -12,6 +12,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
boollpl;
+ u8 safe_sel;
+ u8 old_index;
+ boolreparent;
struct clk_hw hw;
struct notifier_block clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
};
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+unsigned long event,
+void *data)
+{
+ int ret = 0;
+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+clk_nb);
+ /* Switch to safe parent */
+ if (event == PRE_RATE_CHANGE) {
+ mux->old_index = krait_mux_clk_ops.get_parent(>hw);
+ ret = krait_mux_clk_ops.set_parent(>hw, mux->safe_sel);
+ mux->reparent = false;
+ /*
+* By the time POST_RATE_CHANGE notifier is called,
+* clk framework itself would have changed the parent for the new rate.
+* Only otherwise, put back to the old parent.
+*/
+ } else if (event == POST_RATE_CHANGE) {
+ if (!mux->reparent)
+ ret = krait_mux_clk_ops.set_parent(>hw,
+ mux->old_index);
+ }
+
+ return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+ struct krait_mux_clk *mux)
+{
+ int ret = 0;
+
+ mux->clk_nb.notifier_call = krait_notifier_cb;
+ ret = clk_notifier_register(clk, >clk_nb);
+ if (ret)
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+ return ret;
+}
+
static int
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
@@ -70,6 +113,7 @@
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
+ int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init =
+ mux->safe_sel = 0;
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
err_aux:
@@ -119,6 +169,7 @@
krait_add_pri_mux(struct device *dev, int id, const char *s,
unsigned int offset)
{
+ int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init =
+ mux->safe_sel = 2;
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
clk = devm_clk_register(dev, >hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto err_p3;
+err_p3:
kfree(p_names[2]);
err_p2:
kfree(p_names[1]);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 11/14] dt-bindings: clock: Document qcom,krait-cc
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 000..030ba60
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,34 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: must be one of:
+ "qcom,krait-cc-v1"
+ "qcom,krait-cc-v2"
+
+- #clock-cells:
+ Usage: required
+ Value type:
+ Definition: must be 1
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the clock parents of hfpll, secondary muxes.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
+
+Example:
+
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <>, <>, <_aux>, <_aux>,
;
+ clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux",
"qsb";
+ #clock-cells = <1>;
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 10/14] clk: qcom: Add Krait clock controller driver
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/krait-cc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index b17f638..4d0b88f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -270,6 +270,14 @@ config KPSS_XCC
if you want to support CPU frequency scaling on devices such
as MSM8960, APQ8064, etc.
+config KRAITCC
+ tristate "Krait Clock Controller"
+ depends on COMMON_CLK_QCOM && ARM
+ select KRAIT_CLOCKS
+ help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b9cf068..dd30198 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..7ede744 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
- sel = clk_mux_reindex(index, mux->parent_map, 0);
+ sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
sel &= mux->mask;
mux->en_mask = sel;
- return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+ return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
const struct clk_ops krait_mux_clk_ops = {
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+ 2,
+ 0,
+};
+
+static unsigned int pri_mux_map[] = {
+ 1,
+ 2,
+ 0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+ struct krait_div2_clk *div;
+ struct clk_init_data init = {
+ .num_parents = 1,
+ .ops = _div2_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ const char *p_names[1];
+ struct clk *clk;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return -ENOMEM;
+
+ div->width = 2;
+ div->shift = 6;
+ div->lpl = id >= 0;
+ div->offset = offset;
+ div->hw.init =
+
+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+ if (!init.name)
+ return -ENOMEM;
+
+ init.parent_names = p_names;
+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+ if (!p_names[0]) {
+ kfree(init.name);
+ return -ENOMEM;
+ }
+
+ clk = devm_clk_register(dev, >hw);
+ kfree(p_names[0]);
+ kfree(init.name);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+ struct krait_mux_clk *mux;
+ static const char *sec_mux_list[] = {
+ "acpu_aux",
+ "qsb",
+ };
+ struct clk_init_data init = {
+ .parent_names = sec_mux_list,
+ .num_parents = ARRAY_SIZE(sec_mux_list),
+ .ops = _mux_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ struct clk *clk;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ mux->offset = offset;
+ mux->lpl = id >= 0;
+ mux->mask = 0x3;
+ mux->shift = 2;
+ mux->parent_map = sec_mux_map;
+ mux->hw.init =
+
+
[PATCH 11/14] dt-bindings: clock: Document qcom,krait-cc
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 000..030ba60
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,34 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: must be one of:
+ "qcom,krait-cc-v1"
+ "qcom,krait-cc-v2"
+
+- #clock-cells:
+ Usage: required
+ Value type:
+ Definition: must be 1
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the clock parents of hfpll, secondary muxes.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
+
+Example:
+
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <>, <>, <_aux>, <_aux>,
;
+ clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux",
"qsb";
+ #clock-cells = <1>;
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 10/14] clk: qcom: Add Krait clock controller driver
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/krait-cc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index b17f638..4d0b88f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -270,6 +270,14 @@ config KPSS_XCC
if you want to support CPU frequency scaling on devices such
as MSM8960, APQ8064, etc.
+config KRAITCC
+ tristate "Krait Clock Controller"
+ depends on COMMON_CLK_QCOM && ARM
+ select KRAIT_CLOCKS
+ help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b9cf068..dd30198 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..7ede744 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
- sel = clk_mux_reindex(index, mux->parent_map, 0);
+ sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
sel &= mux->mask;
mux->en_mask = sel;
- return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+ return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
const struct clk_ops krait_mux_clk_ops = {
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+ 2,
+ 0,
+};
+
+static unsigned int pri_mux_map[] = {
+ 1,
+ 2,
+ 0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+ struct krait_div2_clk *div;
+ struct clk_init_data init = {
+ .num_parents = 1,
+ .ops = _div2_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ const char *p_names[1];
+ struct clk *clk;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return -ENOMEM;
+
+ div->width = 2;
+ div->shift = 6;
+ div->lpl = id >= 0;
+ div->offset = offset;
+ div->hw.init =
+
+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+ if (!init.name)
+ return -ENOMEM;
+
+ init.parent_names = p_names;
+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+ if (!p_names[0]) {
+ kfree(init.name);
+ return -ENOMEM;
+ }
+
+ clk = devm_clk_register(dev, >hw);
+ kfree(p_names[0]);
+ kfree(init.name);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+ struct krait_mux_clk *mux;
+ static const char *sec_mux_list[] = {
+ "acpu_aux",
+ "qsb",
+ };
+ struct clk_init_data init = {
+ .parent_names = sec_mux_list,
+ .num_parents = ARRAY_SIZE(sec_mux_list),
+ .ops = _mux_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ struct clk *clk;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ mux->offset = offset;
+ mux->lpl = id >= 0;
+ mux->mask = 0x3;
+ mux->shift = 2;
+ mux->parent_map = sec_mux_map;
+ mux->hw.init =
+
+
[PATCH 04/14] dt-bindings: clock: Document qcom,hfpll
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 000..ec02a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,60 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: :
+ shall contain only one of the following. The generic
+ compatible "qcom,hfpll" should be also included.
+
+"qcom,hfpll-ipq8064", "qcom,hfpll"
+"qcom,hfpll-apq8064", "qcom,hfpll"
+"qcom,hfpll-msm8974", "qcom,hfpll"
+"qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: address and size of HPLL registers. An optional second
+ element specifies the address and size of the alias
+ register region.
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the xo clock.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "xo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+ starting at 0. Otherwise hfpll_Y where Y is more specific
+ such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+ clock-controller@f9016000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf9016000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll_l2";
+ };
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+ clock-controller@f908a000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll0";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 04/14] dt-bindings: clock: Document qcom,hfpll
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 000..ec02a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,60 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: :
+ shall contain only one of the following. The generic
+ compatible "qcom,hfpll" should be also included.
+
+"qcom,hfpll-ipq8064", "qcom,hfpll"
+"qcom,hfpll-apq8064", "qcom,hfpll"
+"qcom,hfpll-msm8974", "qcom,hfpll"
+"qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: address and size of HPLL registers. An optional second
+ element specifies the address and size of the alias
+ register region.
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the xo clock.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "xo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+ starting at 0. Otherwise hfpll_Y where Y is more specific
+ such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+ clock-controller@f9016000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf9016000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll_l2";
+ };
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+ clock-controller@f908a000 {
+ compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+ clocks = <_board>;
+ clock-names = "xo";
+ clock-output-names = "hfpll0";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 08/14] clk: qcom: Add KPSS ACC/GCC driver
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/kpss-xcc.c | 87 +
3 files changed, 96 insertions(+)
create mode 100644 drivers/clk/qcom/kpss-xcc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 66894d2..b17f638 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -262,6 +262,14 @@ config QCOM_HFPLL
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+config KPSS_XCC
+ tristate "KPSS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 82615ed..b9cf068 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -43,4 +43,5 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const char *aux_parents[] = {
+ "pll8_vote",
+ "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+ 3,
+ 0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+ { .compatible = "qcom,kpss-gcc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, >dev);
+ if (!id)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (id->data) {
+ if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, ))
+ return -ENODEV;
+ base += 0x14;
+ } else {
+ name = "acpu_l2_aux";
+ base += 0x28;
+ }
+
+ clk = clk_register_mux_table(>dev, name, aux_parents,
+ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+0, aux_parent_map, NULL);
+
+ platform_set_drvdata(pdev, clk);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+ clk_unregister_mux(platform_get_drvdata(pdev));
+ return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+ .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
+ },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 07/14] clk: qcom: Add support for Krait clocks
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/clk/qcom/clk-krait.c
create mode 100644 drivers/clk/qcom/clk-krait.h
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 95f9980..66894d2 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -261,3 +261,7 @@ config QCOM_HFPLL
Support for the high-frequency PLLs present on Qualcomm devices.
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+ bool
+ select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index d486aa3..82615ed 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
clk-qcom-y += clk-hfpll.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT 8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+ unsigned long flags;
+ u32 regval;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ regval = krait_get_l2_indirect_reg(mux->offset);
+ regval &= ~(mux->mask << mux->shift);
+ regval |= (sel & mux->mask) << mux->shift;
+ if (mux->lpl) {
+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+ }
+ krait_set_l2_indirect_reg(mux->offset, regval);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ /* Wait for switch to complete. */
+ mb();
+ udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = clk_mux_reindex(index, mux->parent_map, 0);
+ mux->en_mask = sel;
+ /* Don't touch mux if CPU is off as it won't work */
+ if (__clk_is_enabled(hw->clk))
+ __krait_mux_set_sel(mux, sel);
+
+ return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = krait_get_l2_indirect_reg(mux->offset);
+ sel >>= mux->shift;
+ sel &= mux->mask;
+ mux->en_mask = sel;
+
+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+ .set_parent = krait_mux_set_parent,
+ .get_parent = krait_mux_get_parent,
+ .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+ return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
+ unsigned long flags;
+ u32 val;
+ u32 mask = BIT(d->width) - 1;
+
+ if (d->lpl)
+ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ val = krait_get_l2_indirect_reg(d->offset);
+ val &= ~mask;
+ krait_set_l2_indirect_reg(d->offset, val);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ return 0;
+}
+
+static unsigned long
+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
+ u32 mask = BIT(d->width) - 1;
+ u32 div;
+
+
[PATCH 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed, 174 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb551c7..809f16a 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3254,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+ .mode_reg = 0x3280,
+ .l_reg = 0x3288,
+ .m_reg = 0x328c,
+ .n_reg = 0x3290,
+ .config_reg = 0x3284,
+ .status_reg = 0x329c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3294,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+ .mode_reg = 0x32c0,
+ .l_reg = 0x32c8,
+ .m_reg = 0x32cc,
+ .n_reg = 0x32d0,
+ .config_reg = 0x32c4,
+ .status_reg = 0x32dc,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x32d4,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll3",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3400,
+ .l_reg = 0x3408,
+ .m_reg = 0x340c,
+ .n_reg = 0x3410,
+ .config_reg = 0x3404,
+ .status_reg = 0x341c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3414,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = _l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names =
[PATCH 06/14] clk: qcom: Add IPQ806X's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 28eb200..d571cf8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = _l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll_l2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2800,6 +2879,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = _core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = _tcm_src.clkr,
[NSSTCM_CLK] = _tcm_clk.clkr,
+ [PLL9] = ,
+ [PLL10] = ,
+ [PLL12] = _l2.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed, 174 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb551c7..809f16a 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3254,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+ .mode_reg = 0x3280,
+ .l_reg = 0x3288,
+ .m_reg = 0x328c,
+ .n_reg = 0x3290,
+ .config_reg = 0x3284,
+ .status_reg = 0x329c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3294,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+ .mode_reg = 0x32c0,
+ .l_reg = 0x32c8,
+ .m_reg = 0x32cc,
+ .n_reg = 0x32d0,
+ .config_reg = 0x32c4,
+ .status_reg = 0x32dc,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x32d4,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll3",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3400,
+ .l_reg = 0x3408,
+ .m_reg = 0x340c,
+ .n_reg = 0x3410,
+ .config_reg = 0x3404,
+ .status_reg = 0x341c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3414,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = _l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names =
[PATCH 08/14] clk: qcom: Add KPSS ACC/GCC driver
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/kpss-xcc.c | 87 +
3 files changed, 96 insertions(+)
create mode 100644 drivers/clk/qcom/kpss-xcc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 66894d2..b17f638 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -262,6 +262,14 @@ config QCOM_HFPLL
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+config KPSS_XCC
+ tristate "KPSS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 82615ed..b9cf068 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -43,4 +43,5 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const char *aux_parents[] = {
+ "pll8_vote",
+ "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+ 3,
+ 0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+ { .compatible = "qcom,kpss-gcc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, >dev);
+ if (!id)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (id->data) {
+ if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, ))
+ return -ENODEV;
+ base += 0x14;
+ } else {
+ name = "acpu_l2_aux";
+ base += 0x28;
+ }
+
+ clk = clk_register_mux_table(>dev, name, aux_parents,
+ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+0, aux_parent_map, NULL);
+
+ platform_set_drvdata(pdev, clk);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+ clk_unregister_mux(platform_get_drvdata(pdev));
+ return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+ .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
+ },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 07/14] clk: qcom: Add support for Krait clocks
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/clk/qcom/clk-krait.c
create mode 100644 drivers/clk/qcom/clk-krait.h
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 95f9980..66894d2 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -261,3 +261,7 @@ config QCOM_HFPLL
Support for the high-frequency PLLs present on Qualcomm devices.
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+ bool
+ select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index d486aa3..82615ed 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
clk-qcom-y += clk-hfpll.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT 8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+ unsigned long flags;
+ u32 regval;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ regval = krait_get_l2_indirect_reg(mux->offset);
+ regval &= ~(mux->mask << mux->shift);
+ regval |= (sel & mux->mask) << mux->shift;
+ if (mux->lpl) {
+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+ }
+ krait_set_l2_indirect_reg(mux->offset, regval);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ /* Wait for switch to complete. */
+ mb();
+ udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = clk_mux_reindex(index, mux->parent_map, 0);
+ mux->en_mask = sel;
+ /* Don't touch mux if CPU is off as it won't work */
+ if (__clk_is_enabled(hw->clk))
+ __krait_mux_set_sel(mux, sel);
+
+ return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+ u32 sel;
+
+ sel = krait_get_l2_indirect_reg(mux->offset);
+ sel >>= mux->shift;
+ sel &= mux->mask;
+ mux->en_mask = sel;
+
+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+ .set_parent = krait_mux_set_parent,
+ .get_parent = krait_mux_get_parent,
+ .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+ return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
+ unsigned long flags;
+ u32 val;
+ u32 mask = BIT(d->width) - 1;
+
+ if (d->lpl)
+ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+ spin_lock_irqsave(_clock_reg_lock, flags);
+ val = krait_get_l2_indirect_reg(d->offset);
+ val &= ~mask;
+ krait_set_l2_indirect_reg(d->offset, val);
+ spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+ return 0;
+}
+
+static unsigned long
+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
+ u32 mask = BIT(d->width) - 1;
+ u32 div;
+
+
[PATCH 06/14] clk: qcom: Add IPQ806X's HFPLLs
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 28eb200..d571cf8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = _data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 6UL,
+ .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = _l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll_l2",
+ .ops = _ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2800,6 +2879,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = _core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = _tcm_src.clkr,
[NSSTCM_CLK] = _tcm_clk.clkr,
+ [PLL9] = ,
+ [PLL10] = ,
+ [PLL12] = _l2.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 09/14] dt-bindings: arm: Document qcom,kpss-gcc
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 ++
2 files changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
+- clocks:
+Usage: required
+Value type:
+Definition: reference to the pll parents.
+
+- clock-names:
+Usage: required
+Value type:
+Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: optional
+ Value type:
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
+ CPU number starting at 0.
+
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: should be one of the following. The generic compatible
+ "qcom,kpss-gcc" should also be included.
+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: base address and size of the register region
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the pll parents.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
+ an L2 cache auxiliary clock.
+
+Example:
+
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+ reg = <0x2011000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 09/14] dt-bindings: arm: Document qcom,kpss-gcc
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 44 ++
2 files changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
+- clocks:
+Usage: required
+Value type:
+Definition: reference to the pll parents.
+
+- clock-names:
+Usage: required
+Value type:
+Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: optional
+ Value type:
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
+ CPU number starting at 0.
+
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type:
+ Definition: should be one of the following. The generic compatible
+ "qcom,kpss-gcc" should also be included.
+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+ Usage: required
+ Value type:
+ Definition: base address and size of the register region
+
+- clocks:
+ Usage: required
+ Value type:
+ Definition: reference to the pll parents.
+
+- clock-names:
+ Usage: required
+ Value type:
+ Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: required
+ Value type:
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
+ an L2 cache auxiliary clock.
+
+Example:
+
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+ reg = <0x2011000 0x1000>;
+ clocks = < PLL8_VOTE>, < PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 03/14] clk: qcom: Add HFPLL driver
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9c3480d..95f9980 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -253,3 +253,11 @@ config SPMI_PMIC_CLKDIV
Technologies, Inc. SPMI PMIC. It configures the frequency of
clkdiv outputs of the PMIC. These clocks are typically wired
through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the high-frequency PLLs present on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as MSM8974, APQ8084, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1331ed7..d486aa3 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
new file mode 100644
index 000..a6de7101
--- /dev/null
+++ b/drivers/clk/qcom/hfpll.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+static const struct hfpll_data hdata = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x430405d,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .user_val = 0x8,
+ .user_vco_mask = 0x10,
+ .low_vco_max_rate = 124800,
+ .min_rate = 53760UL,
+ .max_rate = 29UL,
+};
+
+static const struct of_device_id qcom_hfpll_match_table[] = {
+ { .compatible = "qcom,hfpll" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+
+static const struct regmap_config hfpll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x30,
+ .fast_io= true,
+};
+
+static int qcom_hfpll_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = >dev;
+ void __iomem *base;
+ struct regmap *regmap;
+ struct clk_hfpll *h;
+ struct clk_init_data init = {
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = _ops_hfpll,
+ };
+
+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
+ if (!h)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(>dev, base, _regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
+ 0, ))
+ return -ENODEV;
+
+ h->d =
+ h->clkr.hw.init =
+ spin_lock_init(>lock);
+
+ return devm_clk_register_regmap(>dev, >clkr);
+}
+
+static struct platform_driver qcom_hfpll_driver = {
+ .probe = qcom_hfpll_probe,
+ .driver = {
+ .name = "qcom-hfpll",
+ .of_match_table = qcom_hfpll_match_table,
+ },
+};
+module_platform_driver(qcom_hfpll_driver);
+
+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-hfpll");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 03/14] clk: qcom: Add HFPLL driver
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9c3480d..95f9980 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -253,3 +253,11 @@ config SPMI_PMIC_CLKDIV
Technologies, Inc. SPMI PMIC. It configures the frequency of
clkdiv outputs of the PMIC. These clocks are typically wired
through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the high-frequency PLLs present on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as MSM8974, APQ8084, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1331ed7..d486aa3 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
new file mode 100644
index 000..a6de7101
--- /dev/null
+++ b/drivers/clk/qcom/hfpll.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+static const struct hfpll_data hdata = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x430405d,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .user_val = 0x8,
+ .user_vco_mask = 0x10,
+ .low_vco_max_rate = 124800,
+ .min_rate = 53760UL,
+ .max_rate = 29UL,
+};
+
+static const struct of_device_id qcom_hfpll_match_table[] = {
+ { .compatible = "qcom,hfpll" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+
+static const struct regmap_config hfpll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x30,
+ .fast_io= true,
+};
+
+static int qcom_hfpll_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = >dev;
+ void __iomem *base;
+ struct regmap *regmap;
+ struct clk_hfpll *h;
+ struct clk_init_data init = {
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = _ops_hfpll,
+ };
+
+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
+ if (!h)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(>dev, base, _regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
+ 0, ))
+ return -ENODEV;
+
+ h->d =
+ h->clkr.hw.init =
+ spin_lock_init(>lock);
+
+ return devm_clk_register_regmap(>dev, >clkr);
+}
+
+static struct platform_driver qcom_hfpll_driver = {
+ .probe = qcom_hfpll_probe,
+ .driver = {
+ .name = "qcom-hfpll",
+ .of_match_table = qcom_hfpll_match_table,
+ },
+};
+module_platform_driver(qcom_hfpll_driver);
+
+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-hfpll");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
[PATCH 01/14] ARM: Add Krait L2 register accessor functions
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland
Cc: Russell King
Signed-off-by: Stephen Boyd
---
arch/arm/common/Kconfig | 3 ++
arch/arm/common/Makefile | 1 +
arch/arm/common/krait-l2-accessors.c | 48 +++
arch/arm/include/asm/krait-l2-accessors.h | 9 ++
4 files changed, 61 insertions(+)
create mode 100644 arch/arm/common/krait-l2-accessors.c
create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index e5ad070..c8e1986 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,6 +7,9 @@ config DMABOUNCE
bool
select ZONE_DMA
+config KRAIT_L2_ACCESSORS
+ bool
+
config SHARP_LOCOMO
bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3157be4..219a260 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -7,6 +7,7 @@ obj-y += firmware.o
obj-$(CONFIG_SA) += sa.o
obj-$(CONFIG_DMABOUNCE)+= dmabounce.o
+obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
diff --git a/arch/arm/common/krait-l2-accessors.c
b/arch/arm/common/krait-l2-accessors.c
new file mode 100644
index 000..9a97dda
--- /dev/null
+++ b/arch/arm/common/krait-l2-accessors.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include
+#include
+
+#include
+#include
+
+static DEFINE_RAW_SPINLOCK(krait_l2_lock);
+
+void krait_set_l2_indirect_reg(u32 addr, u32 val)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_l2_lock, flags);
+ /*
+* Select the L2 window by poking l2cpselr, then write to the window
+* via l2cpdr.
+*/
+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+ isb();
+ asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
+ isb();
+
+ raw_spin_unlock_irqrestore(_l2_lock, flags);
+}
+EXPORT_SYMBOL(krait_set_l2_indirect_reg);
+
+u32 krait_get_l2_indirect_reg(u32 addr)
+{
+ u32 val;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_l2_lock, flags);
+ /*
+* Select the L2 window by poking l2cpselr, then read from the window
+* via l2cpdr.
+*/
+ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+ isb();
+ asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
+
+ raw_spin_unlock_irqrestore(_l2_lock, flags);
+
+ return val;
+}
+EXPORT_SYMBOL(krait_get_l2_indirect_reg);
diff --git a/arch/arm/include/asm/krait-l2-accessors.h
b/arch/arm/include/asm/krait-l2-accessors.h
new file mode 100644
index 000..a5f2cdd
--- /dev/null
+++ b/arch/arm/include/asm/krait-l2-accessors.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
+#define __ASMARM_KRAIT_L2_ACCESSORS_H
+
+extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
+extern u32 krait_get_l2_indirect_reg(u32 addr);
+
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
