Re: [linux-sunxi] [ANNOUNCE] Allwinner releasing CedarX open source

Hi Kevin, Am 19.05.2015 um 02:44 schrieb ke...@allwinnertech.com: Hi All, We're proud to announce a new code release today for CedarX. Before delving into the details, I'd like to share some context: i'm glad to see, that AW tries to make a move in the right direction. Although steps are no

[linux-sunxi] Re: [RFC 2/7] ARM: dts: sun9i: Add CCI-400 device nodes for A80

On Sun, May 17, 2015 at 10:51 PM, Maxime Ripard wrote: > On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote: >> The A80 includes an ARM CCI-400 interconnect to support multi-cluster >> CPU caches. >> >> Also add the default clock frequency for the CPUs. >> >> Signed-off-by: Chen-Yu Tsai

[linux-sunxi] Re: New firmware for GSL1680

:( Unfortunately still no success. I have grabbed from .module ko from .rodata binaries for GSLX680_FW_TEST GSLX680_FW_gsl_customer GSLX680_FW_I81_GSL3676B_8001280_OGS_SG GSLX680_FW_I802_GSL3676B_8001280_OGS_SG GSLX680_FW_I802_GSL3676B_8001280_OGS_DZ GSLX680_FW_I100_GSL3692_1280800_GG_SG GSLX680_

[linux-sunxi] Re: New firmware for GSL1680

Sergio, Please help to make it clear - the logic of gsl1680 FW: Is it organized in chunks of 128 byte? and if so - does it mean that current firmware = you should switch to the correct block of 128 byte between loaded set of such 128 byte blocks? On Monday, May 18, 2015 at 12:02:00 PM UTC+3, S

[linux-sunxi] Re: [PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates

On Mon, May 18, 2015 at 11:11:34AM +0200, Jens Kuske wrote: > Hi, > > On 05/17/15 14:50, Maxime Ripard wrote: > > Hi Jens, > > > > On Fri, May 15, 2015 at 06:38:52PM +0200, Jens Kuske wrote: > >> Some newer sunxi SoCs (A83T, H3) don't have individual registers for > >> AHB1, APB1 and APB2 gates a

Re: [linux-sunxi] Re: Request for detaild for GSL1680 driver for porting to Linux x86_64 kernel on baytrail 3735f platform

fre 2015-05-15 klockan 18:40 -0400 skrev jonsm...@gmail.com: > Another way - hook up JTAG. Use boundary scan to toggle the pins. That > will tell you the pin number. Look up the pin number and figure out > the GPIO. Or look at the source of the Android kernel running on the device for any hints.

[linux-sunxi] Re: [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

On Mon, May 18, 2015 at 11:32:31AM +0200, Jens Kuske wrote: > Hi, > > On 05/17/15 16:19, Maxime Ripard wrote: > > On Fri, May 15, 2015 at 06:38:54PM +0200, Jens Kuske wrote: > >> Add a remove function and export the init and remove function > >> to allow us to build the SoC specific drivers as mod

[linux-sunxi] Re: [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

On Tue, May 19, 2015 at 3:55 PM, Maxime Ripard wrote: > On Mon, May 18, 2015 at 11:32:31AM +0200, Jens Kuske wrote: >> Hi, >> >> On 05/17/15 16:19, Maxime Ripard wrote: >> > On Fri, May 15, 2015 at 06:38:54PM +0200, Jens Kuske wrote: >> >> Add a remove function and export the init and remove funct

Re: [linux-sunxi] [ANNOUNCE] Allwinner releasing CedarX open source

On Tue, May 19, 2015 at 08:44:13AM +0800, ke...@allwinnertech.com wrote: > Hi All, > > We're proud to announce a new code release today for CedarX. Before delving > into the details, I'd like to share some context: > > 1. As a growing company, we are doing our best to understand the needs of the

Re: [linux-sunxi] Re: New firmware for GSL1680

Hello, On 19 May 2015 at 09:37, wrote: > Sergio, > Please help to make it clear - the logic of gsl1680 FW: > > Is it organized in chunks of 128 byte? and if so - does it mean that current > firmware = you should switch to the correct block of 128 byte between loaded > set of such 128 byte blocks

[linux-sunxi] Re: [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

On Tue, May 19, 2015 at 04:02:39PM +0800, Chen-Yu Tsai wrote: > On Tue, May 19, 2015 at 3:55 PM, Maxime Ripard > wrote: > > On Mon, May 18, 2015 at 11:32:31AM +0200, Jens Kuske wrote: > >> Hi, > >> > >> On 05/17/15 16:19, Maxime Ripard wrote: > >> > On Fri, May 15, 2015 at 06:38:54PM +0200, Jens K

[linux-sunxi] Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

On Mon, May 18, 2015 at 11:22:32AM +0200, Jens Kuske wrote: > On 05/17/15 15:06, Maxime Ripard wrote: > > On Fri, May 15, 2015 at 06:38:53PM +0200, Jens Kuske wrote: > >> Currently, the sunxi clock driver gets the name for the base factor clock > >> of divs clocks from the name field in factors_dat

[linux-sunxi] Re: [PATCH v2 06/10] clk: sunxi: Add H3 clocks support

On Mon, May 18, 2015 at 11:45:50AM +0200, Jens Kuske wrote: > Hi, > > On 05/17/15 16:27, Maxime Ripard wrote: > > On Fri, May 15, 2015 at 06:38:56PM +0200, Jens Kuske wrote: > >> The H3 clock control unit is similar to the those of other sun8i family > >> members like the A23. > >> > >> It makes u

Re: [linux-sunxi] Re: New firmware for GSL1680

Sorry but your post makes it more weird. According https://linux-sunxi.org/GSL1680 page GSL1680 controller stores Firmware in 0x00-0x7F: these registers are used to load portions of the firmware This is only 128 8bit = 1byte registers. So main question is - does this registers = 128 1 byte reg

Re: [linux-sunxi] Re: New firmware for GSL1680

On 19 May 2015 at 11:39, wrote: > Sorry but your post makes it more weird. > According https://linux-sunxi.org/GSL1680 page GSL1680 controller stores > Firmware in 0x00-0x7F: these registers are used to load portions of the > firmware > This is only 128 8bit = 1byte registers. > So main question

Re: [linux-sunxi] Re: New firmware for GSL1680

"On Tuesday, May 19, 2015 at 12:53:43 PM UTC+3, Michal Suchanek wrote: That's one page of the configuration which is 128 bytes or 32 integers. Writing the page register gives access (read or write) to different pages. So one blob might have multiple such pages or the firmware can be composed of

Re: [linux-sunxi] Re: New firmware for GSL1680

On 19 May 2015 at 12:36, wrote: > "On Tuesday, May 19, 2015 at 12:53:43 PM UTC+3, Michal Suchanek wrote: > That's one page of the configuration which is 128 bytes or 32 integers. > Writing the page register gives access (read or write) to different pages. > So one blob might have multiple such pa

[linux-sunxi] A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

I have a board that's got A20 with Samsung's SDRAM 'K4B1G1646G BCK0'. The problem I'm facing now is that I'm not able to get it to boot. I keep getting the following on debug UART: U-Boot SPL 2014.04-10706-g36080eb (Aug 19 2014 - 16:42:16) DRAM:Timeout initialising DRAM resetting ... (Re

Re: [linux-sunxi] A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

Hi, On 19-05-15 12:56, sufi al hussaini hassani kamili raheemi wrote: I have a board that's got A20 with Samsung's SDRAM 'K4B1G1646G BCK0'. The problem I'm facing now is that I'm not able to get it to boot. I keep getting the following on debug UART: U-Boot SPL 2014.04-10706-g36080eb (Aug 19 2

Re: [linux-sunxi] Re: Request for detaild for GSL1680 driver for porting to Linux x86_64 kernel on baytrail 3735f platform

The problem is that there is usually NOAndroid kernel for device, for example Chuwi vi8 super with its plarform (vendor) drivers and platform initial settings. Actually I have found of the way how to detect corresponding gpio pin but it is manual (scripted + manual) guessing (enumerating). Moreo

Re: [linux-sunxi] Re: New firmware for GSL1680

Thank you for make it clear. ;-) Lets transform this knowledge into practical result! I have successfully compiled i2c-tools for x86 Android. So, what is the exact command line to grab all loaded into GSL 1680 chip firmware? i2cbus or i2cget? and how to use it , How via this toolset I could

[linux-sunxi] Re: A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

Thanks for the guidance @Hans. I'm trying to build Mainline U-Boot now. Will post my progress here. On Tuesday, May 19, 2015 at 2:56:30 PM UTC+4, sufi al hussaini hassani kamili raheemi wrote: > > I have a board that's got A20 with Samsung's SDRAM 'K4B1

Re: [linux-sunxi] [ANNOUNCE] Allwinner releasing CedarX open source

On Tue, 19 May 2015 08:44:13 +0800 "ke...@allwinnertech.com" wrote: > 3. Partial CedarX video decoder source code release. MPEG2, MPEG4, > MJPEG, and H264 drivers source code available. And for the others codecs, what are allwinner plans? Should we expect for them to also be released, and which a

Re: [linux-sunxi] [ANNOUNCE] Allwinner releasing CedarX open source

> 1. New code architecture. Driver has been split into several plugins, one > plugin per video format. > 2. GPL-complaint. We have scanned and analyzed the code to ensure that > there > is no GPL code used or called. > 3. Partial CedarX video decoder source code release. MPEG2, MPEG4, MJPEG, > and

[linux-sunxi] Re: [PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support

On Fri, May 15, 2015 at 6:38 PM, Jens Kuske wrote: > The H3 uses the same pin controller as previous SoC's from Allwinner. > Add support for the pins controlled by the main PIO controller. > > Signed-off-by: Jens Kuske Waiting for Maxime's ACKs on these patches before merging. Yours, Linus Wal

Re: [linux-sunxi] [ANNOUNCE] Allwinner releasing CedarX open source

On Tue, 19 May 2015 08:44:13 +0800 "ke...@allwinnertech.com" wrote: > 2. Open source software development is a collaborative process. It > works because people genuinely want to help others improve and be > successful. Some people are new and others help them learn the ropes > over time. We hope t

[linux-sunxi] Re: A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

I tried building mainline u-boot as you suggested @Hans. Here's what I did (please bear with me): Compiled u-boot (natively on olimex A20-micro): (Installed dtc first) > git clone git://git.denx.de/u-boot.git > make A20-OLinuXino_MICRO_defconfig > make Wrote the bootloader files to an SD card

[linux-sunxi] Re: [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

On Tue, May 19, 2015 at 9:55 AM, Maxime Ripard wrote: >> Apart from that, currently the kernel panics some seconds after removing >> the pinctrl module because mmc wants to access a gpio. Can this be >> prevented somehow? I think pinctrl must not be removed once other >> devices use any pin-relat

[linux-sunxi] Re: [PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support

On Tue, May 19, 2015 at 04:04:58PM +0200, Linus Walleij wrote: > On Fri, May 15, 2015 at 6:38 PM, Jens Kuske wrote: > > > The H3 uses the same pin controller as previous SoC's from Allwinner. > > Add support for the pins controlled by the main PIO controller. > > > > Signed-off-by: Jens Kuske >

[linux-sunxi] Re: A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

Has anyone tried this specific DRAM (Samsung's SDRAM 'K4B1G1646G BCK0')? I was wondering if someone could provide me with '[dram_para]' for the FEX file for this specific RAM. Thanks. On Tuesday, May 19, 2015 at 2:56:30 PM UTC+4, sufi al hussaini hassani kamili raheemi wrote: > > I have a board

Re: [linux-sunxi] Re: A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

On Tue, 19 May 2015 08:20:24 -0700 (PDT) sufi al hussaini hassani kamili raheemi wrote: > Has anyone tried this specific DRAM (Samsung's SDRAM 'K4B1G1646G BCK0')? Regarding the "has anyone tried" part of the question, this particular DDR3 chip does not seem to be very popular, according to the i

Re: [linux-sunxi] Re: A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

On Tue, 19 May 2015 07:57:19 -0700 (PDT) sufi al hussaini hassani kamili raheemi wrote: > I tried building mainline u-boot as you suggested @Hans. Here's what I did > (please bear with me): > > Compiled u-boot (natively on olimex A20-micro): > (Installed dtc first) > > > git clone git://git.de

[linux-sunxi] Re: A20 with Samsung's SDRAM 'K4B1G1646G BCK0'

I'm very grateful to you @Siarhei, for having taken the time to write these very helpful replies. You're awesome! I'll read how to get myself a uboot defconfig for my board, and will continue that way. But first, I'm starting with 'sunxi-bootsetup-prototype' image, to make sure all's well hardw