s/allwinner/sun50i-a64.dtsi index
> d783d164b9c3..fda1783b1c86 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -321,6 +321,11 @@
<...>
Kind regards,
Stefan
--
Stefan Brüns / Bergstraße 21 / 52062 A
e a consistent experience across boards, and we
> > will not have to always chase all the defconfigs to provide it.
>
> I think there's a problem on A64 -- the Pine series are all designed to be
> host-only, and it's the most popular A64 board series.
No, it just means the
with a sparse port mapping.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v5:
- Rebase on slave-dma/next tree
Changes in v4:
- remove range checks for dma-channels/dma-requests DT properties
Changes
layout defined maximum
of 32 is used.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4: None
Changes in v3:
- Drop leading 0 from unit name in DT example
Changes in v2: None
.../devicetree/bindings/dma/s
these out of the
conversion to distinct operations.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v4:
- Fix config initialization
Changes in v3: None
Changes in v2:
- Store burst lengths in config inste
The spi controller nodes omit the dma controller/channel references, add
it.
This does not yet enable DMA for SPI transfers, as the spi-sun6i driver
lacks support for DMA, but always uses PIO to the FIFO.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Changes in v4: None
C
The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with
a width of 1, 2, 4 or 8 bytes.
The register value for the the width is log2-encoded, change the
conversion function to provide the correct value for width == 8.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Unit-names must not start with a leading 0.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Changes in v4:
- Split minor fix in devicetree example from patch 6/10
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 2 +-
1 file c
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
e controller specific callback for burst length setting
- Store burst lengths in config instead of device structure
- Store burst widths in config
- Set default number of dma-request if not provided in config or devicetree
Stefan Brüns (11):
dmaengine: sun6i: Correct setting of clock autog
The A64 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals. The last used DRQ port is 27.
Add a device node for it.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Changes in v4: None
Changes in v3:
- Drop leading 0 from dma controlle
-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v4:
- Pass reference to config instead of config itself
- Fix config initialization
Changes in v3: None
Changes in v2:
- Use controller specific callback for burst le
it in the controller config structure.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v4:
- Correct callback function signature, pass pointer to controller
- sun6i_dma_dev refers to sun6i_dma_con
Preparatory patch: If the same compatible is used for different SoCs which
have a common register layout, but different number of channels, the
channel count can no longer be stored in the config. Store it in the
device structure instead.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
The spi controller nodes omit the dma controller/channel references, add
it.
This does not yet enable DMA for SPI transfers, as the spi-sun6i driver
lacks support for DMA, but always uses PIO to the FIFO.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Changes in v3: None
C
ing
- Store burst lengths in config instead of device structure
- Store burst widths in config
- Set default number of dma-request if not provided in config or devicetree
Stefan Brüns (10):
dmaengine: sun6i: Correct setting of clock autogating register for
A83T/H3
dmaengine: sun6i: Correct b
Preparatory patch: If the same compatible is used for different SoCs which
have a common register layout, but different number of channels, the
channel count can no longer be stored in the config. Store it in the
device structure instead.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
these out of the
conversion to distinct operations.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v3: None
Changes in v2:
- Store burst lengths in config instead of device structure
drivers/dma/sun6
with a sparse port mapping.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Changes in v3: None
Changes in v2:
- Set default number of dma-request if not provided in config or devicetree
drivers/dma/sun6i-dma.c | 37 -
1 file changed, 36 inse
The A64 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals. The last used DRQ port is 27.
Add a device node for it.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Changes in v3:
- Drop leading 0 from dma controller unit name
Changes
layout defined maximum
of 32 is used.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3:
- Drop leading 0 from unit name in DT example
Changes in v2: None
.../devicetree/bindings/dma/sun6i-dma.txt
The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with
a width of 1, 2, 4 or 8 bytes.
The register value for the the width is log2-encoded, change the
conversion function to provide the correct value for width == 8.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
it in the controller config structure.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v3:
- Check for callback instead of using a no-op callback
Changes in v2:
- Use callback for autogating instead
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Changes in v3: None
Changes in v2:
- Use controller specific callback for burst length setting
drivers/dma/sun6i-dma.c | 36 +++-
1 file changed, 2
layout defined maximum
of 32 is used.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
.../devicetree/bindings/dma/sun6i-dma.txt | 26 ++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
b/Documen
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
Preparatory patch: If the same compatible is used for different SoCs which
have a common register layout, but different number of channels, the
channel count can no longer be stored in the config. Store it in the
device structure instead.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
it in the controller config structure.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index bcd496
ovided in config or devicetree
Stefan Brüns (10):
dmaengine: sun6i: Correct setting of clock autogating register for
A83T/H3
dmaengine: sun6i: Correct burst length field offsets for H3
dmaengine: sun6i: Restructure code to allow extension for new SoCs
dmaengine: sun6i: Enable additio
with a sparse port mapping.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 37 -
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 245a147f718f..b5ecc9
-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 36 +++-
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 45bcd5271d94..a6fc066a0ac6 100644
--- a/drivers/dma/sun6i-dma.c
The spi controller nodes omit the dma controller/channel references, add
it.
This does not yet enable DMA for SPI transfers, as the spi-sun6i driver
lacks support for DMA, but always uses PIO to the FIFO.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
arch/arm64/bo
The A64 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals. The last used DRQ port is 27.
Add a device node for it.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++
1 file c
these out of the
conversion to distinct operations.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 66 -
1 file changed, 38 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma
with a sparse port mapping.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index c69dadb853d2..bd4c2e
ividually is not to meaningful.
Stefan Brüns (10):
dmaengine: sun6i: Correct setting of clock autogating register for
A83T/H3
dmaengine: sun6i: Correct burst length field offsets for H3
dmaengine: sun6i: Restructure code to allow extension for new SoCs
dmaengine: sun6i: Enable additio
The A64 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals. The last used DRQ port is 27.
Add a device node for it.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++
1 file c
will require new compatible strings. These SoCs either follow the A23
register model (e.g. V3s) or the H3 register model (A64, R40), so a new
variable is added to the config struct to group SoCs with common register
models.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drive
-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 1d9b3be30d22..f1a139f0102f 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/d
layout defined maximum
of 32 is used.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
.../devicetree/bindings/dma/sun6i-dma.txt | 26 ++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
b/Documen
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
these out of the
conversion to distinct operations.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 58 +
1 file changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma
Preparatory patch: If the same compatible is used for different SoCs which
have a common register layout, but different number of channels, the
channel count can no longer be stored in the config. Store it in the
device structure instead.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with
a width of 1, 2, 4 or 8 bytes.
The register value for the the width is log2-encoded, change the
conversion function to provide the correct value for width == 8.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen
The A64 SPI controllers are register compatible to the h3/h5 SPI
controllers.
The A64 has two SPI controllers, each with a single chip select.
The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
as the A64 DMA support is currently missing.
Signed-off-by: Stefan Brüns <stefan.
and the driver.
Stefan Brüns (3):
dmaengine: sun6i: Correct DMA support on H3
arm64: allwinner: a64: Add device node for DMA controller
dmaengine: sun6i: Add support for Allwinner A64
.../devicetree/bindings/dma/sun6i-dma.txt | 1 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
is added to the config.
Separating verification of the config and conversion to register values
allows to keep both independent of the used controller.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 128 +---
The A64 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals.
Add a device node for it.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
arch/arm64/boot/dts/allwinner/sun50i-a6
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. Add the proper config data
and compatible string to support it.
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4
drive
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