From: Thomas Gleixner t...@linutronix.de
On x86 the allocation of irq descriptors may allocate interrupts which
are in the range of the GSI interrupts. That's wrong as those
interrupts are hardwired and we don't have the irq domain translation
like PPC. So one of these interrupts can be hooked up
From: Chew, Kean Ho kean.ho.c...@intel.com
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup
From: Chew, Kean ho kean.ho.c...@intel.com
Add Device ID of Intel BayTrail SMBus Controller.
Signed-off-by: Chew, Kean ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Reviewed-by: Jean Delvare jdelv...@suse.de
Signed-off-by: Wolfram Sang w...@the-dreams.de
(cherry
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace. This change will cause
platform device objects to be created for Intel BayTrail PWM
controllers which will allow the pwm-lpss driver to bind to them
and
From: Chew, Chiau Ee chiau.ee.c...@intel.com
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in
From: Chew, Chiau Ee chiau.ee.c...@intel.com
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew,
From: Adrian Hunter adrian.hun...@intel.com
Add functions to request a CD GPIO using the GPIO descriptor API.
Note that the new request function is paired with mmc_gpiod_free_cd()
not mmc_gpio_free_cd(). Note also that it must be called prior to
mmc_add_host() otherwise the caller must also call
From: Adrian Hunter adrian.hun...@intel.com
Intel SDIO has broken card detect so add a quirk to reflect that.
Signed-off-by: Adrian Hunter adrian.hun...@intel.com
Acked-by: Ulf Hansson ulf.hans...@linaro.org
Signed-off-by: Chris Ball ch...@printf.net
(cherry picked from commit
From: Adrian Hunter adrian.hun...@intel.com
Add ACPI HID 80860F16 as a host controller for a SD card.
Signed-off-by: Adrian Hunter adrian.hun...@intel.com
Signed-off-by: Chris Ball ch...@printf.net
(cherry picked from commit aad95dc49c6dad19b49af7cd90c53473ec0536d1)
---
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Similar to CE4100, BayTrail LPSS SPI can be PCI enumerated
as well. Thus, the functions are renamed from ce4100_xxx
to pxa2xx_spi_pci_xxx to clarify that this is a generic
PCI glue layer. Also, added required infrastructure to
support SPI hosts with
From: Alan Cox a...@linux.intel.com
Not all systems enumerate the PWM devices via ACPI. They can also be
exposed via the PCI interface.
Signed-off-by: Alan Cox a...@linux.intel.com
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Reviewed-by: Mika Westerberg mika.westerb...@linux.intel.com
Media force wake get hangs the machine when the system is booted without
displays attached. The assumption is that (at least some versions of)
the firmware has skipped some initialization in that case.
Empirical evidence suggests we need to reset the media force wake
request register in addition
A number of incremental fixes have been made upstream and in linux-next. There
are a couple still under review, but which are functional and useful. All
non-mainline patches are annotated as such in the commit message, but for
reference, the top 7 patches are not yet in mainline:
d0047ab
From: Mika Westerberg mika.westerb...@linux.intel.com
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chang, Rebecca Swee
From: Adrian Hunter adrian.hun...@intel.com
If the SDHCI irq is shared with another device then the interrupt
handler can get called while SDHCI is runtime suspended. That is
harmless but the warning message is not useful so remove it. Also
returning IRQ_NONE is more appropriate.
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This is to disable/enable DW_DMAC hw during late suspend/early resume.
Since DMA is providing service to other clients (eg: SPI, HSUART),
we need to ensure DMA suspends after the clients and resume
before the clients are active.
Signed-off-by: Chew,
From: Thierry Reding thierry.red...@gmail.com
Fixes the following warnings reported by the 0-DAY kernel build testing
backend:
drivers/pwm/pwm-lpss.c: In function 'pwm_lpss_probe_pci':
drivers/pwm/pwm-lpss.c:192:2: warning: passing argument 3 of
'pwm_lpss_probe' discards 'const' qualifier
From: Adrian Hunter adrian.hun...@intel.com
In preparation for adding a descriptor-based CD GPIO API, switch from
recording GPIO numbers to recording GPIO descriptors.
Signed-off-by: Adrian Hunter adrian.hun...@intel.com
Tested-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Chris Ball
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
Signed-off-by: Darren Hart dvh...@linux.intel.com
Cc: Chew, Chiau Ee chiau.ee.c...@intel.com
Cc: Mika Westerberg mika.westerb...@linux.intel.com
---
drivers/clk/clkdev.c |1 +
1
On 14-05-13 12:11 PM, Darren Hart wrote:
A number of incremental fixes have been made upstream and in linux-next. There
are a couple still under review, but which are functional and useful. All
non-mainline patches are annotated as such in the commit message, but for
reference, the top 7 patches
On 5/13/14, 9:29, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 14-05-13 12:11 PM, Darren Hart wrote:
A number of incremental fixes have been made upstream and in
linux-next. There
are a couple still under review, but which are functional and useful.
All
non-mainline patches are
On 14-05-13 12:35 PM, Darren Hart wrote:
On 5/13/14, 9:29, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 14-05-13 12:11 PM, Darren Hart wrote:
A number of incremental fixes have been made upstream and in
linux-next. There
are a couple still under review, but which are functional and
On 14-05-13 12:11 PM, Darren Hart wrote:
A number of incremental fixes have been made upstream and in linux-next. There
are a couple still under review, but which are functional and useful. All
non-mainline patches are annotated as such in the commit message, but for
reference, the top 7 patches
Hi Bruce,
As most of the BSPs from meta-intel layer are using the standard/base
for KBRANCH, these kernel branches from the linux-yocto-3.14 repository
are not needed anymore, and can be deleted to reduce the branch count.
Darren, Tom,
Do you see any of these branches used anywhere else?
On 5/13/14, 9:49, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 14-05-13 12:11 PM, Darren Hart wrote:
A number of incremental fixes have been made upstream and in
linux-next. There
are a couple still under review, but which are functional and useful.
All
non-mainline patches are
On 5/13/14, 10:06, Kamble, Nitin A nitin.a.kam...@intel.com wrote:
Hi Bruce,
As most of the BSPs from meta-intel layer are using the standard/base
for KBRANCH, these kernel branches from the linux-yocto-3.14 repository
are not needed anymore, and can be deleted to reduce the branch count.
On 14-05-13 04:08 PM, Darren Hart wrote:
On 5/13/14, 9:49, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 14-05-13 12:11 PM, Darren Hart wrote:
A number of incremental fixes have been made upstream and in
linux-next. There
are a couple still under review, but which are functional and
On 14-05-13 04:18 PM, Darren Hart wrote:
On 5/13/14, 10:06, Kamble, Nitin A nitin.a.kam...@intel.com wrote:
Hi Bruce,
As most of the BSPs from meta-intel layer are using the standard/base
for KBRANCH, these kernel branches from the linux-yocto-3.14 repository
are not needed anymore, and can
On 14-05-13 01:06 PM, Kamble, Nitin A wrote:
Hi Bruce,
As most of the BSPs from meta-intel layer are using the standard/base
for KBRANCH, these kernel branches from the linux-yocto-3.14 repository
are not needed anymore, and can be deleted to reduce the branch count.
I'll delete the old
On 5/13/2014 2:54 PM, Bruce Ashfield wrote:
On 14-05-13 01:06 PM, Kamble, Nitin A wrote:
Hi Bruce,
As most of the BSPs from meta-intel layer are using the standard/base
for KBRANCH, these kernel branches from the linux-yocto-3.14 repository
are not needed anymore, and can be deleted to
Merged to standard/base (and then propagated out to all BSP branches).
Keep an eye out for issues, but since this is mainline code, it is safe for
all
boards (i.e. not used), so nothing should go wrong :)
Just want to clarify the practice below because it does conflicts with my
understand
On 5/13/14, 20:47, Ong, Boon Leong boon.leong@intel.com wrote:
Merged to standard/base (and then propagated out to all BSP branches).
Keep an eye out for issues, but since this is mainline code, it is safe
for all
boards (i.e. not used), so nothing should go wrong :)
Just want to clarify
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