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> are you sure? I ask because what i am doing on LX (that worked) is to
> enable the cache, copy the stack back over itself, and then wbinvd. It
> worked well, I think it might work on k8.
That what I wrote was from AMD documentation (pre family F)
>
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Carl-Daniel Hailfinger wrote:
> On 12.01.2008 01:18, Rudolf Marek wrote:
>> Imho you must copy the data from CAR, because when it is OFF, no
>> writeback is
>> done to memory: (from BKDG)
>>
>> Temporary data stored i
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Hi,
Imho you must copy the data from CAR, because when it is OFF, no writeback is
done to memory: (from BKDG)
Temporary data stored in the cache during boot cannot be written back to DRAM
after enabling the
DRAM controller using a CLFLUSH or WBINVB i
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Hi again,
Yeah PDF are out there, only look to right place. Maybe not latest but
something.
Rudolf
jjj.cpvfvt.pbz.fcrpvsvpngvbaf.cpvrkcerff.onfr.CPV_Rkcerff_Onfr_Fcrp_Reengn_1.0n_gb_1.cqs
jjj.urc.hpy.np.hx.yp.pnyvpr.QND.Zrrgvatf.YbatGrez_040728.CPV
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> In PCI, the IDSEL pin defines the device number. But in PCIe, there is
> no such pin, how is the device number defined?
Imho for each slot there is PCI-PCI bridge.
00:02.0 PCI bridge: VIA Technologies, Inc. K8T890 PCI to PCI Bridge Controller
00:03
> You might want one other acked by but, that said, I think this is a
> really excellent patch.
Well nope the other one is just experimental, showing how it is done. It might
be useful for v3 development.
Hum this patch has one minor glitch in the comment
/* set memory voltage to 2.75V chipset v
Hi,
> this is wonderful! Thank you very much for your work!
Yeah I'm happy that it works too. It costs me lot of time and I would rather
win
then lose ;) I'm taking this as broading up my know-how. It goes well because I
got nearly all datasheets for all chips on the board except the marvel gi
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Hello,
Attached patch documents the GPIO setup of the board (check board wiki page) and
fixes the W83627EHF settings for suspend.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Thanks,
Rudolf
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Hi all,
I'm pleased to announce that I got S3 working with LinuxBIOSv2 on ASUS A8V-E SE
(K8 + VT8237 + K8T890)!
I'm attaching the patch which is a big mess, but perhaps all are curious how is
it done.
To be able to do S3 we must first set the register values used for sleep in ACPI
DSDT table:
+
Hi,
You need to have CPU of model 9.
What cat /proc/cpuinfo says?
(or apt-get install cpuid; cpuid )
Thanks,
Rudolf
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Hello Marc,
Just a quick note due to total -ENOTIME.
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
You don't need this, the acpi_fill_mcfg is a weak symbol. if it does not exists
everythin
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Hi,
The guide is not finished yet :)
But please try booting with: pci=routeirq
Rudolf
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iD8DBQFHXxcn3J9wPJqZRNURAqPXAKDTpDQ
>Yes, please!
Ok I will try to schedule it to near future.
Rudolf
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Hi all,
Adding ACPI support which should at least do poweroff properly or
deliver power button event is
quite simple. Maybe I can write some howto to wiki?
Rudolf
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>
> I only committed the first patch for now; is the second one ready for
> being committed too or is it work in progress? Does it work?
Yes this is OK. Second is just for illustration. The LB should construct the
bytecode of the second patch in runtime, because the content must be changed
when
Uwe Hermann wrote:
> On Mon, Nov 12, 2007 at 11:24:37PM +0100, Rudolf Marek wrote:
>> Hello,
>>
>> Attached patch fine-tunes the V-link bus between K8T890 and VT8237R and set
>> it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be
>> ne
different).
This patch enables the parity error reporting on V-Link, so it enables NMI
generation for the SERR# errors. The NMI may not be generated, maybe port 61h
needs some tuning too.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Btw there is FID/VID patch pending too.
Rudolf
will try to justify this once
I know what bios to set in SB.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Second patch just gives an example what needs to be in DSDT to make it actually
work. Usually this part is stored in secondary DSDT table (SSDT), which is build
in runtime in BIO
Hi all,
Corey, that patch does not work for me.
PCI: 00:03.3 [1106/f238] enabled
PCI: 00:0c.0 [10ec/8139] enable
Cannot find pci bus operations
...freeze...
If I remove your patch again after 00:0c.0 it will continue with:
PCI: 00:0f.0 enabled
...
Rudolf
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> I'm not seeing that anywhere, is it in the porting guide? All I have is
> the datasheet.
Yes in PG.
Rudolf
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> Very good point! I'll keep it in mind. And you need at least one UHCI
> controller for EHCI to work.
And if you have UHCI fn2 enabled you need to have fn0 and fn1 too... (check VIA
docs)
Rudolf
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Corey Osgood wrote:
> See patch. Rudolf, can you test this one to make sure it works correctly
> on your board?
Hi,
Your patch seems not so solve KBD and RTC correct? This could be implemented in
superio on other board for example. Also the clock gating for Ethernet should
be
made programmable
should be only a wrapper in mb code for some kind of
chipset specific mmconfig fill function.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
Index: src/arch/i386/boot/acpi.c
===
--- src/arch/i386/boot/acpi.c (revisio
>
> This isn't super neat, the else could be removed.
It is prepared for the 2T logic... but I agree the DCL_UnBufDimm; coulde be
before the if...
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out the 2T support? Now it can be triggered with the code change only.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
Index: src/northbridge/amd/amdk8/raminit.c
===
--- src/northbridge/amd/amdk8/raminit.c (revision 2901)
+++
.
PCI: BIOS Bug: MCFG area at e000 is not E820-reserved
PCI: Not using MMCONFIG.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
Index: src/arch/i386/boot/acpi.c
===
--- src/arch/i386/boot/acpi.c (revision 2901)
+++ sr
Hi just a quick question,
Did you check with SVN version that it still needs warming up?
Thanks,
R.
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ff-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
Index: util/k8resdump/k8resdump.c
===
--- util/k8resdump/k8resdump.c (revision 0)
+++ util/k8resdump/k8resdump.c (revision 0)
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the LinuxB
Rudolf Marek wrote:
Hi all,
here is fixed version, writeback is guarded with debug level.
ISA->LPC
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
Hmm my check and send extension overseen that I forgot the attachment :/
Sorry.
Rudolf
Index: src/southbridge/via/vt8237r/
Hi all,
here is fixed version, writeback is guarded with debug level.
ISA->LPC
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
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>> It is in "VT8237R Plus BIOS Porting Guide" just few lines of code, i
>> can write it in next mail so NDA is "satisfied".
>
> OK. Problem is though it has to be taken care of before the devices are
> scanned, so that no device drops off or appears and confuses LB. If the
> lpc bridge were scanne
Hi all,
> Sorry I haven't gotten to this yet, been very busy lately. I'll
> hopefully be back at work on the cn700 tomorrow, trying to get it ready
> to go in the tree, so I'd like to see this in as well. Just a few little
> things:
ok thanks,
>
> Perhaps something like
>
> #if DEFAULT_CONSOLE
t now, since my primary
goal is to make it available.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
Index: src/southbridge/via/vt8237r/vt8237r.c
===
--- src/southbridge/via/vt8237r/vt8237r.c (revision 0)
+++ src/so
> On your special board or on the SB in general?
Asus put Gigabit Ethernet chip. So only on my board.
> I just recently noticed that it _does_ make a big difference whether the
> PCI ID lines are there, at least for the (ISA) bridge. If it's not
> listed (no matter if the function it calls is em
Hello all,
Uwe Hermann wrote:
> Here's one more review:
>
> On Sat, Oct 27, 2007 at 01:16:49AM +0200, Rudolf Marek wrote:
>> +void hard_reset(void)
>> +{
>> +printk_err("NO HARD RESET ON VT8237R! FIX ME!\n");
>> +}
>> +
&g
> Is this board still available?
Its on ebay. (they have like 60 boards) I think I will buy a spare one maybe ;)
> If you don't get an ack soon from someone push me and I will do it. I
> have not done much k8 recently (all geode) so I try to let other
> experts ack. At the same time, I am sorry t
Hi Peter,
> The second line is very long.
Ok.
> I think these should be a doxygen comment around the declaration of
> the fn_ctrl_lo/hi members in src/southbridge/via/vt8237r/chip.h.
Ok.
>
>
>> +/* TODO: if SATA is disabled, move IDE to fn0 to conform PCI specs */
>
> How is that done?
ron minnich wrote:
> Great! What mainboard :-)
Asus A8V-E SE,
I already published Northbridge patch, and southbridge yesterday.
Rudolf
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Hello,
Its Friday night... I have no date...
I think I fixed everything what Uwe wanted. Here comes much better patch (after
five hours ;)
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Corey,
I fixed the SMBus so it does work from the beginning. Please can you test on
your si
Hi All,
Good news everyone, it works!
The problem was that I did not put:
allow_all_aps_stop(bsp_apicid);
into my auto.c code. I did not knew about it :/
The core was never put to sleep and this error was never reached:
print_initcpu8("while waiting for BSP signal to STOP, timeout i
Please always post boot logs and debug output to the list, where it's
archived. We want to be able to read up on old posts, problems, patches,
discussions even in 5 five years from now...
If the size does not matter I will.
R.
LinuxBIOS-2.0.0_Fallback Ãt ÅÃj 23 22:10:56 CEST 2007 starting.
Hi all,
>>> new boot log with log level = 8?
http://assembler.cz/download/dc3.txt
> Check CONFIG_LOGICAL_CPUS=1 is set. I think that is the flag for
> intializing aditional cores on each CPU.
Yes it is correct, rest CPU related looks like this:
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
yhlu wrote:
> On 10/23/07, Rudolf Marek <[EMAIL PROTECTED]> wrote:
>
>> Hello,
>>
>>> default ENABLE_APIC_EXT_ID=0
>>> default APIC_ID_OFFSET=0x10
>>> default LIFT_BSP_APIC_ID=0
>>>
>>>
>> Thanks, it hel
Hello,
> default ENABLE_APIC_EXT_ID=0
> default APIC_ID_OFFSET=0x10
> default LIFT_BSP_APIC_ID=0
>
Thanks, it helped a bit. Now I have APIC ID 0x1 as I expected.
But still same trouble :/
Rudolf
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Forgot:
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
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Hello all,
I have new CPU opteron 175 - sigle cpu dualcore, I'm not able to initialize AP
properly.
http://assembler.cz/download/minicom_dc.txt
It seems I can boot them, but they never arrive to check point.
Any idea what might be wrong? Also I don't know why my core1 have APIC ID 0x11
instead
ry if I already asked that)
What exactly? The BAR addr is computed dynamically.
+ * Modified for K8T890 ROM strap by Rudolf Marek
Uh, "trivial" (well, let say "short" ;-) file, so (C) Rudolf Marek should
suffice, IMHO.
Ok. But I will leave it as it is ;)
+ dump_so
Hi,
Doing ACPI only IRQ routing is quite easy. I'm not going to describe whole ACPI
table stuff just the part you need for the routing:
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025845.html
Check the dsdt.asl file in patch above.
/* top PCI device */
Hi all,
I fiddled bit more of the data corruption problem and it seems to be RAM
related
problem. It only occurs if the RAM is in dual channel mode (DDR400 auto
settings).
I have some other dimms that are same size (512MB) but with CL3, it works fine
with them. What is bit strange, that there
Thanks, I will try to fix it ASAP. I got some problem with data integrity of my
computer. It is not LinuxBIOS fault it seems - it happens with award too ;) I
think my harddrive produces 1bit changes to the data sometimes. Effectively
making mess in / FS. I have my data on RAID5 (except /) and those
you need to supply some routing table to kernel. Any of following:
in DSDT
PIR table
MP Table.
There is some util to dump this table friom original bios, although in my case
MP table was totally b0rked.
I think for a start you may switch off the acpi=off
Rudolf
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Just some comments to more specific issues:
>
> USB will return, unfortunately. Not sure why I need it and he doesn't.
> All of these variables can be dropped for now, we'll add them back
> later. This won't be as bad as the i810, I'll keep working on this to
> make sure it's done right in the l
CHeck the calibrating delay loop code.
Kernel will lockup if the IRQs arent generated at all. Imho there were some
"lpj" options to force at least some value, maybe you can get further.
Rudolf
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Whoops sorry,
I generated the patch from the current directory. It should go to
src/southbridge/via/k8t890
I can generate new patch tomorrow if you need it.
Thanks,
Rudolf
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device is some kind of CPU-PCI bridge...
I dont know...
This patch adds support for K8T890CE northbridge.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
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Hello
Sorry for the delay.
Uwe Hermann wrote:
> On Sat, Sep 29, 2007 at 02:02:48AM +0200, Rudolf Marek wrote:
>> Index: src/northbridge/amd/amdk8/northbridge.c
>> ===
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After nice nine hour sleep ...
The problem is that LXB tables for memory are constructed only from regions
which are OK not which are reserved. So there is currently no way how to pass
the reserved regions to LXB tables and to FILO which also looks on
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Hello all,
I'm attaching quite big patch which adds support for the K8T890/VT8237R chipset
and for my motherboard Asus A8V-E SE.
It works fine except for reboot, I'm using it daily ;) Now I need help with the
release.
I have done some modifications
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Hello,
This patch changes the "if else" style of parameter matching to table and also
changes the rdpreamble parameter, which will cause that more then one DIMM will
work for 939 motherboard.
What about the 2T support?
Please take a look to a patch
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Hello,
Following patch adds MCFG table for ACPI, so linux can find MMCONFIG area for
PCI configuration access.
Please note that you need to hack Linux kernel and remove the check for e820 not
reserved complain.
Signed-off-by: Rudolf Marek <[EM
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This patch fixes the resource end in amdk8/northbridge.c
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Rudolf
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iD
Ok.
This is all about terminology from the LB point of view.
> (what exactly qualifies those bridges as north bridges?)
VIA has some V-link interface, which is partly in SB and in NB (NB as called by
VIA)... well I dont really care, all I need to know was answered in your
previous email,
I will
Hello,
Soon I will need decision where to put the K8T890 (K8 platform) NB code.
Solutions as suggested by uwe_
1) add new "northbridge chip" to config.lb, place it in src/northbridge
This means not only mem cotroller chip are northbridges
2) put "southbridge chip" statement to config.lb place
SIGNATURE-
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Rudolf Marek <[EMAIL PROTECTED]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
* the Free Software Foun
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Corey Osgood wrote:
> Just realized thats where my smbus IO base is. I'll try moving things
> around a bit, I don't even need smbus at the moment.
> Heh, I went ahead and dumped my mptable, even though this is a single
> processor system. The mptable
Thanks, I'll have a look at these tomorrow. For some reason, ACPI on my
> system doesn't work (produces the error I had before) if the base is set
> to 0x500, but it does work with 0x400 (the factory slot). Also, a quick
>
Maybe you have something at 0x500, use the isadump -f 0x500 from
lm-sen
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Oh sorry one more table for a shiny morning ;)
Rudolf
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/enigmail.mozdev.org
iD8DBQFG82Ug3J9wPJqZRNURAqwtAJ9Mm4mwNs6xX2/AHiI/LvC09iUIygCgjzUG
5SUdcLdIMBQSRWe7CW1fS1g=
=q9ho
-END PGP SIGNATURE-
/*
* This file is part of the LinuxBIOS project.
*
* Based on other VIA SB code.
* Copyright (C) 2007 Rudolf Marek <[EMAIL PROTECTED]>
*
* This program is free software; you
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You have undefined NEED_LAPIC
#if NEED_LAPIC == 1
...
#else
printk_info("Disabling local apic...");
#endif...
RTFS ;)
Rudolf
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Hello,
Following patch fixes the resource size, which should be written to register.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Regards
Rudolf
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yhlu wrote:
> it seems your soft-reset never work...
You mean, the soft_reset should reset the CPU too? So never return?
Rudolf
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Hello,
Sorry for the delay, I moved to flat and got no internet for a while.
LinuxBIOS-2.0.0_Fallback Po zář 3 22:17:08 CEST 2007 starting...
now booting... fallback
LinuxBIOS-2.0.0_Normal Po zář 3 22:16:19 CEST 2007 starting...
now booting.
Hi all,
Just an update to this problem, removing soft_reset in cpu_init module does not
help. I added 1s delay before calling the setup_resource map, now it hangs when
it writes third "line" of the the resource table. I dont think there is
anything
significant, yet I dont know what could be wr
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Hello all,
I cant get the reboot working. I have set CPU reboot to INIT in my SB, so INIT
is generated when booting via KBD/92, Linuxbios will jump to real_main, same
way as it boots from cold, but got freeze on setup_default_resource_map();
I'm us
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> According to the datasheet, devid for IT8726 is 0x8716.
Datasheet is wrong, the chip does return 0x8726
http://lists.lm-sensors.org/pipermail/lm-sensors/2007-March/019101.html
Rudolf
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Hi all,
http://www.lm-sensors.org/browser/lm-sensors/trunk/prog/detect/sensors-detect?format=txt
Here is a bunch of superIO detected. Hope it helps,
Rudolf
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> Thank you for the reply, I believe I need some SST 49LF040 or PM 49FL004
I bought some at http://bios-repair.co.uk/bios/eeprom.htm (shipped to Czech Rep
for like 60p iirc;)
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Hi Corey,
I cant tell more than this code:
To be distributed under GPL:
//WARNING NEED to copy some registers from NB to SB (D0F3 -> D0F7)
{
device_t devFUNNB3 = dev_find_device(PCI_VENDOR_ID_VIA, 0x3238, 0);
u8 reg
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Hi all,
Just an update. The "memtester" which is doing the memtesting while in OS will
fail on "solid test".
Has anyone ever succeeded to run more than one dimm DDR unbuffered in single
channel mode on K8?
Thanks,
Rudolf
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> hmm, probably should have tried that first, I suppose. I did a bunch of
> init for it, and it currently causes a kernel panic. Thanks!
It has only set some bits for the SMM by BIOS, which we dont need. So nothing is
needed.
Hre is mu promised upda
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Hmm I tried to set some bits for socket 939 in fun2 0x90 and 0x94, seems that
RAM works now for two dimms ;) Perhaps I need to develop some fix?
I will write about this later.
> USB works?
Yes USB does work. I tried again with my USB stick. Nothing
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Hi Corey,
> Both of these should be solved with ACPI tables, one of the Epia-M pages
> in the wiki has some good info on using iasl. Also make sure
> HAVE_HARD_RESET = 0 in mainboard Options.lb
Ok have there =1 will try it.
>
>> I may write more
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Hello all,
I'm typing this message in Thunderbird from LinuxBIOS booted system. Yeah I told
this last time, but I have still some issues left.
1) Single channel memory problems
I have two 512MB dimms in singe channel, because LinuxBIOS does not han
0xa0);
/* Write SMBus IO base to 0xd0, and enable SMBus */
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
/* Set to Award value */
pci_write_config8(dev, 0xd2, 0x01);
/* make it work for I/O ...*/
pci_write_config16(dev, 0x04, 0x0001);
/* The other, slightly hackish, fixup meth
>
> Slightly off-topic, have you done any more work on the vt8237? I've
> resumed work on it, but I'm still stuck on the northbridge at the moment.
Yes it works now.I have only that problem with the C-E Otherwise it
works. The files are missing copyright and license. If you want I can se
Hello Peter,
Peter Lemenkov wrote:
> Hello Rudolf!
>
> 2007/7/13, Rudolf Marek <[EMAIL PROTECTED]>:
>>
>> > http://lemenkov.googlepages.com/lspsi_xxx.txt
>>
>> Hmm for first quick view I cant tell. Perhaps not everything. Do you
>> want to
>
Rudolf Marek wrote:
>>> BUT! The VGA ROM seems to be mapped to C8000! How is this possible? Why is
>>> linuxbios claiming that the RAM is from C-E???
>> Weird. It should be mapped to C and that is usually hardcoded. What
>> card is that? External? Is the
>
> http://lemenkov.googlepages.com/lspsi_vvv.txt
>
> I included dmidecode log also:
>
> http://lemenkov.googlepages.com/dmidecode.txt
I need -xxx and not -vvv ;)
R.
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Hi Peter!
I dont know how much different is VIA 880 from K8T890. It seems it has no PCIe
correct? Maybe you can send here a lspci -xxx output.
Rudolf
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>> BUT! The VGA ROM seems to be mapped to C8000! How is this possible? Why is
>> linuxbios claiming that the RAM is from C-E???
>
> Weird. It should be mapped to C and that is usually hardcoded. What
> card is that? External? Is there onboard VGA?
Sorry for the noise. It maps to c000
> Great news!
Yeah but I will need some help!
I have still problems with the RAM versus PCI MMIO. I think I found the problem:
LinuxBIOSv2/src/northbridge/amd/amdk8/northbridge.c:559
resource->base = 0xa;
resource->size = 0x2;
/* write the resource to the hardw
Hello all,
I just got four words for you: It boots now yeah!
Yes it boots my standard Linux kernel (2.6.22)
SATA/IDE/USB/soundcard/gigabiteth
and my Radeon seems to work. My MB is Asus A8V-E SE. Which might be
compatible
with A8V-E Duluxe... So someone wants to play too?
However there are
Hi,
Just a short comment:
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) \
+ + sizeof(typeof(int[1 - 2*!!__builtin_types_compatible_p(typeof(arr), \
+typeof(&arr[0]))]))*0)
-- Rusty Russell <
Stefan Reinauer wrote:
> * Rudolf Marek <[EMAIL PROTECTED]> [070628 01:12]:
>> Anyone knows the reason why this register get overwritten?
>
> Maybe hard coded by the south bridge? What does the legacy bios do?
No I'mm talking about 0:18.1 device, which is the AMD NB. I
Hello all,
I have some troubles with my resource map on my VIA/K8 project. I'm working on
K8T890 VIA / VT8237 MB with K8 939.
For some reason my PCI IO limit get set to 0x4000
:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80
> Of course this realmode stuff is of no use under linux.
You can use lrmi lib to do the VM86 call. Best would be to check what the
interryupt is doing. Perhaps fiddling some GPIO lines.
Rudolf
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Hello,
There is one device. It is an extension to thunderbird.
It is called check and send!
https://addons.mozilla.org/cs/thunderbird/addon/2281
Rudolf
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Corey Osgood wrote:
> Corey Osgood wrote:
>> Rudolf Marek wrote:
>>> I'm attaching version which works for me (tm)
>>> //dimm &= 0x0E;
>>> //dimm |= 0xA1;
>> It works without those? Interesting. I'll try it in a few minutes, see
>
Hello again,
>> I'm attaching version which works for me (tm)
>> //dimm &= 0x0E;
>> //dimm |= 0xA1;
> It works without those? Interesting. I'll try it in a few minutes, see
> if it works here.
My address is 0x50 which I get from the rest of Linux Bios for some reason. So
I
just need the
Hi again,
I found bugs in your code:
loops = 0;
/* Yes, this is a mess, but it's the easiest way to do it */
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1 && loops <=
SMBUS_TIMEOUT)
++loops;
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