Re: [LinuxBIOS] Intel refactoring and microcode updates

; >>>> I agree, but we should also try to be even more flexible. I think we >>>> should allow inclusion of 0<=n<=all microcode updates. Definately an >>>> advanced option, but still. >>>> >>> Yep, that's what I meant. It's fine i

Re: [LinuxBIOS] Intel refactoring and microcode updates

icrocode > updates", but there should be an option for advanced users to only use > the one(s) you really want or need in order to save time and space. > > > Uwe. > That makes perfect sense.I like the advanced option idea:-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Intel refactoring and microcode updates

t CPUs they belonged to. In >>>>> truth, Intel uses the same CPU IDs for a variety of CPUs, for instance >>>>> in some cases Celeron, Pentium X, and Xeons all share a common ID, since >>>>> the core is still the same. So we can't really do that any

Re: [LinuxBIOS] Intel refactoring and microcode updates

Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>: > > Do you see any way to solve the "size problem" for sockets with too many > different cores? > > Regards, > Carl-Daniel > Not sure what you mean? How many different cores could you put in even the most

Re: [LinuxBIOS] svn question

th/to/file /patch/to/patchfile.patch > > Here's a couple of examples: http://wiki.creativecommons.org/HOWTO_Patch > Thanks for the help. To be specific I want to test the fedora core 8 patch. So I would just do a: patch ../LinuxBIOSv2 /patch/to/patchfile.patch because the patch was supp

Re: [LinuxBIOS] Intel refactoring and microcode updates

now, I've left the current model_fxx and socket_*60*, so nothing >>> breaks, but IMO the socket_603/604 I've added should be made to work. >>> >>> Both patches Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> >>> >>> >> Hmm looks good

[LinuxBIOS] svn question

Dumb question, but I can't seem to find any real good docs on svn. How to I commit a patch to my local LinuxBIOSV2 copy?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Intel refactoring and microcode updates

k note to each file to what processor it belongs too? I think that would save developers time from having to look it up when writing code for a new board? What do you think? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [PATCH] remove duplicated microcode updates for some Intel processors

Quoting Corey Osgood <[EMAIL PROTECTED]>: > [EMAIL PROTECTED] wrote: >>> Microcode updates coming in the morning, if the abuild passes. >>> >>> -Corey >>> >>> >> SWEET :-) >> >> >> Thanks - Joe > > Well, it fail

Re: [LinuxBIOS] [PATCH] remove duplicated microcode updates for some Intel processors

> Microcode updates coming in the morning, if the abuild passes. > > -Corey > SWEET :-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] april meeting in denver

zers about the denver meeting. I hope to have >> more info next week. >> > > April will be a time when I'm totally busy with finalizing my thesis, so > I'd appreciate if someone could set up a live feed from the meeting. > A live feed would be very cool for t

Re: [LinuxBIOS] Patch file for ld/fedora 8 issue as promised...

hink it would solve your > problem. > > I think here in the US everyone is still on vacation, so we should > wait until next week to resolve this. > > thanks > > ron > Sorry Ron I must have missed that one??? Could you re-attach it? Thanks - Joe -- linuxbios mailing li

Re: [LinuxBIOS] Patch file for ld/fedora 8 issue as promised...

won't be able to try it out until this weekend. If all goes well, you will definatly have my ACK:-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [Patch] Fix CONFIG_CONSOLE_VGA handling in default pci_dev_init.

both are needed. > I think it is pretty clearly stated here: http://linuxbios.org/VGA_support Also this might help some: http://www.linuxbios.org/data/vgabios/ Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Proposed changes to cpu/intel organization

>> for slot 1, we no longer care. Why do we not care about slot 1?? What are the 440BX boards going to do?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [PATCH] remove duplicated microcode updates for some Intel processors

Quoting Corey Osgood <[EMAIL PROTECTED]>: > > Acked-by: Corey Osgood <[EMAIL PROTECTED]> > > how long has it been since we've updated the microcode updates? > No idea, but remember the email below from 12/12/07? Looks like an update is in order, but I wouldn'

Re: [LinuxBIOS] Change BIOS option for end-user?

What would be cool is if someone wrote a gui interface for lxbios that we could run in X. Google summer of code 2008 maybe?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] Lightning talk at FSCONS 2007

So how did the Lightning talk at FSCONS 2007 in Gothenburg go? Do you have any video's for us Peter?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] problem about dram init

st I was sucessfull with was 1MB) or filo chokes. Doesn't LB allocate a bounce buffer just before the payload starts? Is this bounce buffer just below tolm?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [Fwd: Re: Patch file for Fedora 8 compile problems]

uildtarget? > > Marc has already shown us lots of ways of making it automatic. We will > use one of his ideas. > > ron > Yes I do agree that Marc has some very good ideas of making it automatic. Just trying to help with the brain storming process:-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [Fwd: Re: Patch file for Fedora 8 compile problems]

be then how to make this automatic or would you have compile buildtarget with the makefile option (BUILD_ID="blah blah") before you started using LB? Sorry if this question has already been answered Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [Fwd: Re: Patch file for Fedora 8 compile problems]

make this a makefile option. No need to make things more complicated than they need to be. But, I don't really know why we would need to add a seperate build option file that the makfile calls just for one function (assuming it would only be one function), unless your idea is to designate the makefilo.distro file for future distro specific issues? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [Fwd: Re: Patch file for Fedora 8 compile problems]

gt; We have to find a better way. Let's keep thinking. > > Thanks! > > ron > I may be way off here but couldn't you just put in a simple if statment that says something like this: if (ld_version >= XXX) { Use these build Options; } Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Southbridge

Quoting [EMAIL PROTECTED]: > Quoting Cimino Vittorio <[EMAIL PROTECTED]>: > >> Is possible to make a dump of southbridge? >> >> tnx >> > Yup, lsppci -xxx as root > > Sorry only one p lspci -xxx Thanks - Joe -- linuxbios mailing list linuxbios@l

Re: [LinuxBIOS] Southbridge

Quoting Cimino Vittorio <[EMAIL PROTECTED]>: > Is possible to make a dump of southbridge? > > tnx > Yup, lsppci -xxx as root Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Request for superiotool dump support: SMSC LPC47M192

u might be able to do this one while you're at it. >> > >> > Thanks, >> > Corey >> > >> I know the hundreds of pages on the datasheet can get a little >> munotinious. Which values are you confused about? >> >> >> Thanks - Joe >&g

Re: [LinuxBIOS] Request for superiotool dump support: SMSC LPC47M192

g them > (which is a good thing, and I'm glad you're doing it), so I was hoping > you might be able to do this one while you're at it. > > Thanks, > Corey > I know the hundreds of pages on the datasheet can get a little munotinious. Which values are you conf

Re: [LinuxBIOS] [Fwd: Re: Patch file for Fedora 8 compile problems]

Quoting ron minnich <[EMAIL PROTECTED]>: > so can others besides me test this, and, Marc, thanks for the patch. > > ron > I just upgraded my laptop to FC8 x86_64. I will do some test building this weekend and report back. Thanks - Joe -- linuxbios mailing list linuxbios@

Re: [LinuxBIOS] Intel microcode revision code

. > > Just wanted to let you know. > > Best regards, > Martin Karlsson > Hmm, very good question. I think the microcode has been waiting for sommeone to update it. Anyone else have a take on this? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Support for Intel Little Valley

t Intel, please utilize them. They are far and few between. There are a few SIS developers that help out with LB. Maybe they would be of more use? A 512k chip is plenty big enough to fit LB+Payloads. I don't think you would be able to fit a whole LB+Payloads+kernel+minimalOS on it though. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] HP E-Vectra i810e

a bios for this machine? > > It should be pretty easy to setup the i810e. 99% of the work has already been done for you, Thanks to Corey & Uwe. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Vendor contacts - how to proceed

ks > ron > I also think if we did make this a page on the wiki it could be a positive impact on other venders browsing the site. They will see that their competitors are onboard with LinuxBIOS and want to get involved?? What do you think? Thanks - Joe -- linuxbios m

Re: [LinuxBIOS] Vendor contacts - how to proceed

lp us. > That's great and I'd like to tell them: "Yes, we care, we can set up > something." > > Regards, > Carl-Daniel > That's great. We should add something like this to a vender contacts wiki page. I think it should be up to each vender contact on what information is shared. Especially since the web is public access. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Link error on Fedora 8

lect2: ld returned 1 exit status > > Any clues about this one? The ldscript.ld is attached. > > --Ed > Ed, I was having problems building with FC7. I think it may have had to do with eithor binutils or gcc. I never ended up figuring it out and just did a fresh install choosing the &qu

Re: [LinuxBIOS] Socket 370 thought....

is a bit generic. All it needs to do is get Linux going and as long as the Linux kernel is able to detect the processor (vender/device id, etc) it can take over and unleash the processors full capabilities? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Socket 370 thought....

0-CPU-Celeron-3-Converter-Socket-for-Tualatin_W0QQitemZ230192200737QQcmdZViewItem?hash=item230192200737 >> >> Here is one for 15$ >> >> Thanks - Joe >> > > Joe - What chipsets have they been working with? They should work just > fine with LinuxBIOS if we have the chipsets ported. > > Back around 9

Re: [LinuxBIOS] Socket 370 thought....

ferences, but this would allow >> much faster processors, up to 1.4Ghz :-) >> >> Thanks - Joe Quoting popkonserve <[EMAIL PROTECTED]>: > most boards are incompatible because intel chose a different pinout for > fcpga-ii cpus on purpose. a hardware modification (or an

[LinuxBIOS] Socket 370 thought....

processors, up to 1.4Ghz :-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [PATCH] lbsysinfo -- tool to gather system information

or BIOS with the output from LinuxBIOS. > > If we feel this is useful, we could add it as util/lbsysinfo/lbsysinfo. > Cool Uwe, This could potentially be a great asset to developers:-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Intel 865 GBF motherboard support

support will there be new version would be >> released which could possibly support Intel 865 GBF mother boards. > > There has been some work done on the 865 chipset, but it still > requires some (much?) work. I don't know if there is a timeframe, > I think the people who start

[LinuxBIOS] FSCONS 2007

( But, if they do you can count me in!! Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] r2951 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx

on Bus 1 down >> > from the PCI Bus. >> >> Interesting, I'll have a look at that tomorrow. This isn't a change in >> the code in any way though, just fixing a comment. > > Yep. But Joe is correct, the code probably needs fixing. > > Looking at the c

Re: [LinuxBIOS] r2951 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx

Little confused by this. Isn't this supposed to be posted to the list first for review, before being commited? Is it ok for the same person to "Signed-off-by:" and "Acked-by:"?? See comments below... Thanks - Joe Quoting [EMAIL PROTECTED]: > Author: uwe >

Re: [LinuxBIOS] mptable util not working?

tem. I'm not entirely sure it's the _correct_ fix, but it _does_ > fix the issue I have seen on the 440BX boards. > > > Uwe. > Thanks Uwe I will give that a try. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] mptable util not working?

data though. I think this is my problem, CPU to IO doesn't seem to >> be communicating, and I thought the mptable might help. I'm >> stumped But Corey maybe able to help me figure this out very soon. >> >> Thanks - Joe > > Yeah, there's probably no mp

Re: [LinuxBIOS] mptable util not working?

7;s probibly why. It seems to contain alot of IO data though. I think this is my problem, CPU to IO doesn't seem to be communicating, and I thought the mptable might help. I'm stumped But Corey maybe able to help me figure this out very soon. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] mptable util not working?

Hello, I am having prolems with the mptable utility. I keeps telling me "MP FPS NOT found, suggest trying -grope option!!!". If I try the grope option it still spits out the same message. Am I doing something wrong? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbio

Re: [LinuxBIOS] GRUB 2 and LinuxBIOS

following the page on the wiki, but I was under the asumption that is was still being developed:-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] GRUB 2 and LinuxBIOS

linuxbios.org/mailman/listinfo/linuxbios > Do you mean GRUB2 as a Payload? If so, SWEET!! Great work. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc R3

's weird. It built ok against my local repository ok. I will > try a new build against the new revision. > Builds just fine. Thanks again - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc R3

ed the changes from the patch to the svn file, > hope I didn't accidentally break something. I also fixed some more > cosmetics in the patch (but no code changes). > > > Uwe. > Hmm that's weird. It built ok against my local repository ok. I will try a new build agains

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc R3

idn't apply for some reason). > > > Uwe. > -- Thanks Uwe. What did you have to change to apply the patch?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc R3

>>>> >>>> 3. The rest of the fixups were trivial. >>>> >>>> Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> >>> >>> Ok, here is the revised patch per Uwe's and Corey's suggestions. >>> >> OK, Now here is th

[LinuxBIOS] IRQ Routing info tool for DOS

Hello, Just wanted to let everyone know I found another IRQ routing info tool. It only works for DOS and Win. But It may be handy for other people having problems. Maybe add to Wiki?? http://members.datafast.net.au/~dft0802/downloads.htm Thanks - Joe -- linuxbios mailing list linuxbios

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc R3

ch #3. Thanks - Joe Thanks for not shooting me ;) Acked-by: Corey Osgood <[EMAIL PROTECTED]> Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> Thanks - Joe Index: src/southbridge/intel/i82801xx/i82801xx_lpc.c === --- sr

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc R3

by irq_tables.c or by acpi_tables.c on a mainboard level. 3. The rest of the fixups were trivial. Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> Ok, here is the revised patch per Uwe's and Corey's suggestions. OK, Now here is the final revised patch #3. Thanks - Joe Index:

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc

gt;> - * 1 == S5 Soft Off >>>> - */ >>>> -pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); >>>> -printk_info("Set power %s if power fails\n", pwr_on ? "on" : >>>> "off"); >>>> +/* Set the state of the gpio lines */ >>>> +gpio_init(dev, ich_model); >>>> >>>> -/* Set up NMI on errors */ >>>> -byte = inb(0x61); >>>> -byte &= ~(1 << 3);/* IOCHK# NMI Enable */ >>>> -byte &= ~(1 << 2);/* PCI SERR# Enable */ >>>> -outb(byte, 0x61); >>>> -byte = inb(0x70); >>>> - >>>> -nmi_option = NMI_OFF; >>>> -get_option(&nmi_option, "nmi"); >>>> -if (nmi_option) { >>>> -byte &= ~(1 << 7);/* Set NMI */ >>>> -outb(byte, 0x70); >>>> -} >>>> - >>>> /* Initialize the real time clock */ >>>> i82801xx_rtc_init(dev); >>>> >>>> +/* Route DMA */ >>>> i82801xx_lpc_route_dma(dev, 0xff); >>>> >>>> -/* Initialize isa dma */ >>>> +/* Initialize ISA DMA */ >>>> isa_dma_init(); >>>> >>>> -i82801xx_1f0_misc(dev); >>>> +/* Setup Decode Ports and LPC I/F Enables */ >>>> +i82801xx_lpc_decode_en(dev, ich_model); >>>> + >>>> /* Initialize the High Precision Event Timers, if present */ >>>> enable_hpet(dev); >>>> } >>>> Index: src/southbridge/intel/i82801xx/i82801xx.h >>>> === >>>> --- src/southbridge/intel/i82801xx/i82801xx.h(revision 2901) >>>> +++ src/southbridge/intel/i82801xx/i82801xx.h(working copy) >>>> @@ -35,16 +35,24 @@ >>>> >>>> #define PCICMD0x04 >>> >>> This is already defined in pci.h (I think). It's PCI_COMMAND, IIRC >>> >> OK, but is it being used by the other c files? > > Yes, but I can't seem to find one at the moment. I know that it's > included with (which in turn includes pci_def.h, where > PCI_COMMAND is defined). IIRC the fresh vt8237r uses it. > >>> >>>> #define PMBASE0x40 >>>> -#define PM_BASE_ADDR0x1100 >>>> #define ACPI_CNTL0x44 >>>> #define BIOS_CNTL0x4E >>>> #define GPIO_BASE0x58 >>>> -#define GPIO_BASE_ADDR0x1180 >>>> +#define GPIOBASE0x48 >>> >>> What's GPIO_BASE vs GPIOBASE? Better names possible? >>> >> GPIOBASE is what intel calls it in the ICH6-9 datasheets. >> What should I name this?? > > GPIOBASE makes perfect sense, the confusion is, what's the difference > between that and GPIO_BASE > The register address 0x58 (ICH0-ICH5) vs 0x48 (ICH6-ICH9). > >>> >>>> #define GPIO_CNTL0x5C >>>> +#define GC0x4C >>> >>> Again, what's GC? GameCube? :p >>> >> GC is what intel calls it in the ICH6-9 datasheets. >> What should I name this?? > > What's it actually control/do? I'm sure you can come up with something. > Perhaps even just leave the define and include a comment stating what it > is. Up to you. > Same as GPIO_CNTL but for (ICH6-ICH9). The register address 0x5C (ICH0-ICH5) vs 0x4C (ICH6-ICH9). There is a comment in the gpio_init() function. > >>> >>>> #define PIRQA_ROUT0x60 >>>> +#define PIRQB_ROUT0x61 >>>> +#define PIRQC_ROUT0x62 >>>> +#define PIRQD_ROUT0x63 >>>> #define PIRQE_ROUT0x68 >>>> +#define PIRQF_ROUT0x69 >>>> +#define PIRQG_ROUT0x6A >>>> +#define PIRQH_ROUT0x6B >>>> #define COM_DEC0xE0 >>>> +#define LPC_IO_DEC0x80 >>>> #define LPC_EN0xE6 >>>> +#define LPC_EN20x82 >>>> #define FUNC_DIS0xF2 >>>> >>>> #define CMD0x04 >>> >>> Is this used the same as PCICMD above? If so, both should be nuked in >>> favor of PCI_COMMAND >>> >> Agree, no need for duplicated code. But again, is it being used by the >> other c files? >>> >>> Damn, I made one hell of a mess when I hacked this together, didn't I? >>> Well, thanks for cleaning it up :) >>> >>> Cheers, >>> Corey Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc

;/* Set NMI */ >> -outb(byte, 0x70); >> -} >> - >> /* Initialize the real time clock */ >> i82801xx_rtc_init(dev); >> >> +/* Route DMA */ >> i82801xx_lpc_route_dma(dev, 0xff); >> >> -/* Initialize isa

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc

acpi_tables.c on a mainboard level. 3. The rest of the fixups were trivial. Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> Ok, here is the revised patch per Uwe's and Corey's suggestions. Thanks - Joe Index: src/southbridge/intel/i82801x

Re: [LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc

> /* Initialize isa dma */ >> isa_dma_init(); >> >> -i82801xx_1f0_misc(dev); >> + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. >> + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F >> + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 >> + */ >> +pci_write_config8(dev, COM_DEC, 0x10); > > COM_DEC won't work for ICH8. We can commit this right now, but please > add a comment that it'll only work for ICH-ICH5 (or so) for now. OK > > >> + >> +/* Set the value for LPC I/F Enables Register */ >> +pci_write_config16(dev, LPC_EN, 0x300F); > > Same for LPC_EN, different on ICH8. OK > > >> + >> /* Initialize the High Precision Event Timers, if present */ >> enable_hpet(dev); >> } >> Index: src/southbridge/intel/i82801xx/i82801xx.h >> === >> --- src/southbridge/intel/i82801xx/i82801xx.h(revision 2899) >> +++ src/southbridge/intel/i82801xx/i82801xx.h(working copy) >> @@ -42,7 +42,13 @@ >> #define GPIO_BASE_ADDR 0x1180 >> #define GPIO_CNTL 0x5C >> #define PIRQA_ROUT 0x60 >> +#define PIRQB_ROUT 0x61 >> +#define PIRQC_ROUT 0x62 >> +#define PIRQD_ROUT 0x63 >> #define PIRQE_ROUT 0x68 >> +#define PIRQF_ROUT 0x69 >> +#define PIRQG_ROUT 0x6A >> +#define PIRQH_ROUT 0x6B >> #define COM_DEC 0xE0 >> #define LPC_EN 0xE6 >> #define FUNC_DIS0xF2 > > Yep, looks good. > > > Uwe. > -- > http://www.hermann-uwe.de | http://www.holsham-traders.de > http://www.crazy-hacks.org | http://www.unmaintained-free-software.org > Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] [v2][PATCH] Trivial fixups for i82801xx_lpc

level. 3. The rest of the fixups were trivial. Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> Thanks - Joe Index: src/southbridge/intel/i82801xx/i82801xx_lpc.c === --- src/southbridge/intel/i82801xx/i82801xx_lpc.c (re

[LinuxBIOS] EHCI Debug Port

Hello, I just wanted to let everyone know I found his cool article on EHCI USB Debugging. It goes a little further into detail about cables that can be used for this. Possible to add it to the Wiki?? http://www.intel.com/technology/magazine/computing/it09021.pdf Thanks - Joe -- linuxbios

Re: [LinuxBIOS] [PATCH] Common code base for Intel 440BX boards

it undecided if it should be > src/mainboard/common/i440bx-base > or > src/mainboard/i440bx-base > (i.e. put the "base" code parts in an extra directory or not). Opinions? > > > Uwe. Why couldn't there just be a src/northbridge/intel/common/ directory? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Building an irq table - Help

>>>> irc_tablec.c >>>> How do I tell?? Also where does the value for the "bitmap" come from? >>>> >>>> Thanks for your help - Joe >>>> >>>> /* bus, dev|fn, >>>> {0x01,(0x08<<3)|0x0, >>&g

Re: [LinuxBIOS] Building an irq table - Help

Quoting Marc Jones <[EMAIL PROTECTED]>: [EMAIL PROTECTED] wrote: Ok I am a little confused on how to tell what devices are what in irc_tablec.c How do I tell?? Also where does the value for the "bitmap" come from? Thanks for your help - Joe /* bus, dev|fn, {0x01,(0x0

Re: [LinuxBIOS] [PATCH] Common code base for Advantech PCM-5820, ASI MB_5BLMP, BCOM WinNET100

> Alot of the intel chipsets have common functions. Maybe some other ones can be included? I think this is a good Idea. Eliminating duplicated code and adding it globaly can simplify things when adding support for a new chip. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] Building an irq table - Help

Ok I am a little confused on how to tell what devices are what in irc_tablec.c How do I tell?? Also where does the value for the "bitmap" come from? Thanks for your help - Joe /* bus, dev|fn, {0x01,(0x08<<3)|0x0, {0x00,(0x1f<<3)|0x0, {0x00,(0x1d<<3)|0x0, {0x00,(

Re: [LinuxBIOS] Kernel lock-ups??

is isn't just related to a Read issue with the Upper >> Bios Area 0x0F(960K) - 0x0F(1MB)?? That is why I would like to >> diagnos that first. So I ask is there a way to dump (printk) this area >> in human readable format right after the check_pirq_routing_table() >&

Re: [LinuxBIOS] Kernel lock-ups??

Interrupt Link [LNKC] enabled at IRQ 9 > ACPI: PCI interrupt :00:1d.2[C] -> GSI 9 (level, low) -> IRQ 9 > ACPI: PCI Interrupt Link [LNKH] enabled at IRQ 10 > ACPI: PCI interrupt :00:1d.7[D] -> GSI 10 (level, low) -> IRQ 10 > ACPI: PCI interrupt :00:1f.1[A] -> GSI

Re: [LinuxBIOS] Kernel lock-ups??

CI Interrupt Link [LNKB] enabled at IRQ 11 ACPI: PCI interrupt :00:1f.3[B] -> GSI 11 (level, low) -> IRQ 11 ACPI: PCI interrupt :00:1f.5[B] -> GSI 11 (level, low) -> IRQ 11 ACPI: PCI Interrupt Link [LNKE] enabled at IRQ 11 ACPI: PCI interrupt :01:08.0[A] -> GSI 11 (level, low) -> IRQ 11 Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Kernel lock-ups??

is going on here? By the way I used getpir.c to get my irq_tables.c file. Could this be messed up? If so how come the functions above do not detect any errors? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [v2][PATCH] Mobile Intel Celeron CPU Support

Quoting [EMAIL PROTECTED]: > Quoting Corey Osgood <[EMAIL PROTECTED]>: > >> [EMAIL PROTECTED] wrote: >>> This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA) >>> >>> Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> >&g

Re: [LinuxBIOS] Kernel lock-ups??

00530 - 06ec checksum 622a Heck, I just attached my whole bootlog. Please take a look and see if you can see anything wrong. I would really appreciate it. Thanks - Joe LinuxBIOS-2.0.0.0RM4100 Mon Oct 15 07:42:50 EDT 2007 starting... Setting initial registers Initial registers have been se

Re: [LinuxBIOS] Kernel lock-ups??

gt; > I think for a start you may switch off the acpi=off > > Rudolf I have HAVE_PIRQ_TABLE=1 and irq_tables.c. What is the utility for the MP table? Anyways I tried these kernel options acpi=off irqpoll lpj=720896 and it gets a little further. Now it locks-up on this line: Checking 

Re: [LinuxBIOS] Kernel lock-ups??

IRQs arent generated have anything to do with this: ACPI: Unable to locate RSDP Also, it is a custom kernel config. I will try the normal one and see if that helps. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] [v2][patch] Mobile Intel Celeron CPU Support

Quoting Corey Osgood <[EMAIL PROTECTED]>: > [EMAIL PROTECTED] wrote: >> This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA) >> >> Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> >> >> Thanks - Joe > > Acked-by: Corey Osg

[LinuxBIOS] Kernel lock-ups??

: Initializing. SELinux: Starting in permissive mode selinux_register_security: Registering secondary module capability --- Is there some kind of a bug between LB and SELinux?? Is there a command line option to just ignore SELinux? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org

Re: [LinuxBIOS] BIOS-provided physical RAM map

t;> >>>> BIOS-provided physical RAM map: >>>> >>>> BIOS-e820: 1000 - 000a (usable) >>>> >>>> BIOS-e820: 0010 - 0800 (usable) >>>> >>>> 128MB LOWMEM available. >>> >&

Re: [LinuxBIOS] Mobile Intel Celeron CPU Question

ce_id be then? 0x06B4 right? >>> >>> Yep, I think so. >> >> You could also run 'cpuid -a' or 'x86info -a' for lots more >> information... >> >> apt-get install cpuid >> apt-get install x86info >> >> >&g

Re: [LinuxBIOS] BIOS-provided physical RAM map

1000 - 000a (usable) >>> >>> BIOS-e820: 0010 - 0800 (usable) >>> >>> 128MB LOWMEM available. >> >> hi joe, I am not sure I understand your question? what is the value of >> tolmk in this case? &

Re: [LinuxBIOS] MSI MS-6337 (i815 based)

were supposed to be reserved but they are not. I set those and boom it booted:-) Hope that helps. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] BIOS-provided physical RAM map

gt;> Because mine does not look the same. >> >> ram_resource(dev, idx++, 0, 640); >> ram_resource(dev, idx++, 1024, tolmk - 1024); >> >> BIOS-provided physical RAM map: >> >> BIOS-e820: 1000 - 000a (usable) >> >> BIOS-e820: 0

[LinuxBIOS] BIOS-provided physical RAM map

p: BIOS-e820: 1000 - 000a (usable) BIOS-e820: 0010 - 0800 (usable) 128MB LOWMEM available. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Mobile Intel Celeron CPU Question

gt; information... > > apt-get install cpuid > apt-get install x86info > > > Uwe. Ok, I will try that before someone acks my patch. I was just going by the datasheet: Reserved [31:14] - 0x Type [13:12] - 0x Family[11:8] - 0x0600 Model [7:4] - 0x00B0 Stepping [3:0] 0x0004 = 0x06B4 Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] [v2][patch] Mobile Intel Celeron CPU Support

This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA) Signed-off-by: Joseph Smith <[EMAIL PROTECTED]> Thanks - Joe Index: src/cpu/intel/model_6xx/model_6xx_init.c === --- src/cpu/intel/model_6xx/model_6xx_

Re: [LinuxBIOS] Mobile Intel Celeron CPU Question

;, also considering the processors mentioned are: >> >> From model_6dx_init.c >> { X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 >> cache */ >> >> From model_69x_init.c >> { X86_VENDOR_INTEL, 0x0695 }, /* Pentium M */ >> >>

Re: [LinuxBIOS] Mobile Intel Celeron CPU Question

cache */ From model_69x_init.c { X86_VENDOR_INTEL, 0x0695 }, /* Pentium M */ It just seems a little silly to setup a whole new directory of exactly the same code as these. Except mine would say: model_6bx_init.c { X86_VENDOR_INTEL, 0x06B4 }, /* Mobile Celeron FCBGA 479*/ Corey, you should be able to relate with all your i82801xx code condensing. Good work by the way (if I hadden't mentioned that already):-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Mobile Intel Celeron CPU Question

ae mce cx8 sep mtrr pge mca cmov pat > pse36 mmx fxsr sse > bogomips : 1445.88 > > What would my cpu_device_id be then? 0x06B4 right? Can this be > combined with the model_69x then? They are very close. > > Thanks - Joe > Or possibly we can condense them into a model_6xxm (

[LinuxBIOS] Mobile Intel Celeron CPU Question

cpu_device_id be then? 0x06B4 right? Can this be combined with the model_69x then? They are very close. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] ram_resource question

le 1: >>>> tolmk -= IGD_MEMORYK >>>> ram_resource(dev, idx++, 1024, tolmk - 1024; >>>> >>>> OR >>>> >>>> Example 2: >>>> ram_resource(dev, idx++, 1024, (tolmk - IGD_MEMORYK) - 1024); >>>> ram_resource(dev, i

[LinuxBIOS] ram_resource question

(dev, idx++, 1024, (tolmk - IGD_MEMORYK) - 1024); ram_resource(dev, idx++, (tolmk - IGD_MEMORYK) - 1024, tolmk - IGD_MEMORYK); Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] MSI MS-6337 (i815 based)

t assigned PNP: 002e.7 60 <- [0x0024c0 - 0x0024c0] io ERROR: PNP: 002e.7 62 io size: 0x02 not assigned ERROR: PNP: 002e.7 70 irq size: 0x000001 not assigned If I was you I would look deeper into these errors. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] i82830 memory initialization - FIXED

hard set these registers for testing and boom, memtest completed successfully. Yep, it was a wacky Intel thing just like I thought. I attached the bootlog. I hope this will help anyone else working on intel northbridges. Thanks - Joe I am still getting a weird APIC error when I enable VGA

Re: [LinuxBIOS] MSI MS-6337 (i815 based)

/pnp not available could be cause by your LPC Interface Bridge. Eithor it is not enabled or not configured for PNP maybe? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] i845-zhu shi song-Are you out there?

me with my i82830 problem:-) Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Mode Register Set raminit.c

nderstand where 0x1D0 is coming from. Can anyone > point me to a datasheet that expains this?? > OK, i figured out they are the correct settings << 3. But why do they need to be bitshifted over three spaces?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http:

[LinuxBIOS] Mode Register Set raminit.c

datasheet that expains this?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Problems with Filo booting - HELP

Aperture all togethor for now but the i82830 is not designed to run in headless mode (no graphics). I will try this out and report back. I don't know where to go from here.. Thanks - Joe Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00 1

Re: [LinuxBIOS] Problems with Filo booting - HELP

It looks like the original bios alocates the memory region 0xf000 - 0xf7ff for the Aperture how would I force LinuxBIOS to do this?? Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

Re: [LinuxBIOS] Problems with Filo booting - HELP

. Set register GCC0 Bit 9 to 1. This enables access to the Aperture allowing LB to configure an address range. I wish there was a way to just disable the Aperture all togethor for now but the i82830 is not designed to run in headless mode (no graphics). I will try this out and report back. Thanks - Joe -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios

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