, I need this all calls for more debugging, but I just wanted to
get some logs up before I split for the week.
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S1832DL boot
session log:
http://www.eskimo.com/~roger/programming/linuxbios/index.html
http://www.eskimo.com/~roger/files/linuxbios/440BX.S1832DL/session-20070528.log
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Mon May 28
On Mon, 2007-05-28 at 23:24 -0400, Corey Osgood wrote:
On Mon, 2007-05-28 at 14:56 -0700, roger wrote:
On a side note, I'm having to use your tyan/s1846 profile instead of the
asus/p2b profile (after patching it with my superio) because I think the
asus/p2b/auto.c is buggy (... think Corey
On Tue, 2007-05-29 at 06:46 +0200, Uwe Hermann wrote:
Hi,
On Mon, May 28, 2007 at 08:20:30PM -0700, roger wrote:
It lives! ... well, until the kernel gets to init. The kernel usually
states my root partition is /dev/sda2 because of the usual add-in SATA
pci card. However, Filo
carrying service to
USPS... maybe more.
I already have a couple of 440bx boards around (asus p2b).
I might be interested.
Also, if there's a developer on this list interested working with the
440BX, I also might be willing to donate shipping costs.
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Roger
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int as a return type?
Stefan
Just posted to the list on this question, confirming i get a hang
without the above fix for asus/p2b/auto.c on generic DFI P2XBL board.
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Roger
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Tue May 15 09
)
+static inline int spd_read_byte(unsigned int device, unsigned
int
address)
{
- uint8_t c;
- c = smbus_read_byte(device, address);
- return c;
+ return smbus_read_byte(device, address);
}
--
Roger
http
BIOS for s2912? Thanks for your help and advices!
See the Linuxbios FAQ on VGA support. (There's a howto on the wiki
page.)
Best,
Ning
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Roger
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Tue May 15 15:13:17 PDT 2007
As I was looking, noticed several other chip.h files needing cosmetic
changes. (Pushed includes to top of source code and included a license
within all three chip.h files.)
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Tue
On Mon, 2007-05-14 at 14:07 +0800, Yuning Feng wrote:
2007/5/14, roger [EMAIL PROTECTED]:
Would it help any if I made a list of items needed for proper Intel
northbridge (and possibly southbridge/smbus) initialization?
This is helpful.
I think 440bx might be a good mainboard to start
of fact, even installed FreeDOS to a 2nd partition with Uniflash.
Uniflash supports a vast number of flash parts.
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Sun May 13 23:31:49 PDT 2007
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ff ff ff ff ff ff ff
am i looking at this right?
Row 0x70, and count in hex.
The values at 0x7e 0x7f respectively are; 0x64 0xa4?
Looking at the other 2 sticks of sdram I have:
0x64, 0xf6
0x64, 0xf7
(0x64, 0xff are all on my Mushkin in my S1832DL)
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motherboards?
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pertaining to what should be set
before/after SPD.
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Mon May 14 17:23:51 PDT 2007
(P 29)
In addition to reserved bits within a register, PAC contains address locations
Is this right? Push #includes to the top of the file.
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Mon May 14 22:57:38 PDT 2007
Push includes to the top of the file.
Signed-off-by: Roger Zauner [EMAIL PROTECTED]
Index
the 0x 0xff00a00c values are calculated by
somehow adding all the settings possible for NBX and somehow, the value
is uniquely recognized by the Northbridge??
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Sun May 13 01:39:19
On Sun, 2007-05-13 at 01:39 -0700, roger wrote:
I'm kind of confused on this one...
How would I specify a DRAMC or CAS setting (after referring to the 440BX
intel spec pdf)?
For example:
--- Snip from Intel pdf ---
NBXCFG—NBX Configuration Register (Device 0)
Offset: 50–53h
Default
/winbond/w83977tf/w83977tf_early_serial.c
-#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
+#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
- pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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Roger
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seen also, the info is there, it's just
categorized instead of listing chronologically.)
(I've read/scanned most of the northbridge pdf files, and starting to
get an understanding of i440bx/raminit.c)
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Roger
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Key fingerprint = 8977 A252 2623 F567 70CD 1261
On Sun, 2007-05-13 at 19:09 -0400, [EMAIL PROTECTED] wrote:
Roger this would be very helpful. I have been working on other Intel
chipsets (cousins of the i440bx) and something to go by would be great!!
Thanks - Joe
ok.. i'll start taking notes tonight.
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Roger
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On Mon, 2007-05-14 at 00:02 -0400, Corey Osgood wrote:
roger wrote:
On Sun, 2007-05-13 at 19:09 -0400, [EMAIL PROTECTED] wrote:
Roger this would be very helpful. I have been working on other Intel
chipsets (cousins of the i440bx) and something to go by would be great!!
Thanks - Joe
are basically
bricks until somebody adds some code to firebrand for USB support.
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00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
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http
On Thu, 2007-05-10 at 00:08 -0400, Corey Osgood wrote:
roger wrote:
BTW: I've set up my asus/p2b/auto.c to mimmick the tyan/s1846/auto.c
So DRAM *should* be working and getting to at least elfboot.
Only things I can think of would be DRAM timing too.
roger, only test with one dimm
get as far as:
DRAM range verified.
Done.
Copying LinuxBIOS to RAM.
Jumping to LinuxBIOS.
LinuxBIOS-2.0.0.0Fallback Thu May 10 00:25:28 PDT 2007 booting...
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Thu May 10 00:27:31 PDT
On Wed, 2007-05-09 at 22:45 -0700, roger wrote:
Ram4
Testing DRAM : -0009
DRAM fill: -0009
000a
DRAM filled
DRAM verify: -0009
000a
DRAM range verified.
Done.
Testing DRAM : 0010-007c
DRAM fill: 0010-007c
007c
DRAM
On Fri, 2007-04-27 at 03:15 -0400, Corey Osgood wrote:
roger wrote:
On Thu, 2007-04-26 at 23:35 -0700, roger wrote:
On Fri, 2007-04-27 at 00:45 +0200, Uwe Hermann wrote:
Strange, the patch looks correct. Have you tried all variations in this
line (0x2e, 0x4e, 0x3f0
superio chips to see if
this is needed as well as I have the chip spec pdf files here as well.
I noticed the other winbond chips use different addresses and values.)
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Wed May 9 07:25:26
to SDRAM init: and then I
still get random hangs about this point. Patch doesn't seem to break
anything here. Since I'm hacking on my DFI P2XBL w/ w83977tf, I can't
easily test on my Tyan S1832DL with S1846 profile right now.)
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Key fingerprint = 8977
On Wed, 2007-05-09 at 07:48 -0700, roger wrote:
The superio needs 0x87 sent twice to 0x3f0 to enable extended function
(power-on strapping). Although this is already done in superio.c, it's
not being done when w83977tf_early_serial.c is executed. As such, no
console_init -- atleast in my
I don't have this chip, but while this chip specific documentation says
this is needed. (The rest of the winbond superio's within the
v2_linuxbios tree has this code already.)
So I'm entering it untested, but should work according to documentation.
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an educational target, we should not drop the stuff that we
call our selling points.
Unfortunately, Qemu still requires those ram patches that I know of.
Wish the dev of qemu would apply them. :-/ ... or at least apply them
with a configure switch --use-linuxbios. (ie. ifdef)
--
Roger
http
On Wed, 2007-05-09 at 19:58 +0200, Uwe Hermann wrote:
On Wed, May 09, 2007 at 08:20:56AM -0700, roger wrote:
I get random hangs during sdram init.
Hm. My guess is that some RAM parameters don't match your system
(66 MHz vs. 100 MHz system bus frequency, or such), or are just plain wrong
BTW: I've set up my asus/p2b/auto.c to mimmick the tyan/s1846/auto.c
So DRAM *should* be working and getting to at least elfboot.
Only things I can think of would be DRAM timing too.
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005
On Thu, 2007-05-10 at 00:08 -0400, Corey Osgood wrote:
roger wrote:
BTW: I've set up my asus/p2b/auto.c to mimmick the tyan/s1846/auto.c
So DRAM *should* be working and getting to at least elfboot.
Only things I can think of would be DRAM timing too.
roger, only test with one dimm
.
Sounds too new to be stocked.
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to fiddle with this.
Did you enable full visibility of the flash chip? (PAM something)
Interesting.
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On Sun, 2007-04-29 at 10:38 -0700, roger wrote:
On Sun, 2007-04-29 at 14:50 +0200, Uwe Hermann wrote:
Hi,
here's a first patch for the 440BX code and the Tyan S1846 and the 82371EB
southbridge which gets my Tyan S1846 a lot further in the boot process.
However, it cannot boot
and how many years it took for it to
become usable (without data loss) and then stable (bug free).
irssi (ncurse based irc suits me just fine dandy ;-).
Plus, it doesn't require a lot of overhead, if any at all. :-)
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On Mon, 2007-04-30 at 17:19 +0800, AlexHuang wrote:
Hi all,
I got an error message from linuxbios as below:
No memory for this cpu
RAM Cache feauture?
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Mon Apr 30 11
an ebuild for LinuxBIOS or just Flashrom.
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Interesting... seems this patch is creating a cpu run when compiling.
Within ASM code maybe?
Roger
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Mon Apr 30 15:18:19 PDT 2007
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On Tue, 2007-05-01 at 01:12 +0200, Uwe Hermann wrote:
On Mon, Apr 30, 2007 at 12:19:46PM -0700, roger wrote:
Or have we verified writing to memory is successful?
Well, yes, at least I think so :) -- lol.
However, we only know for sure when we
booted a payload successfully (which
Pro
100] (rev 08)
(...Deleted Other Additional PCI Devices...)
fyi, similar layout here too.
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Sun Apr 29 10:28:23 PDT 2007
LinuxBIOS-2.0.0.0Fallback Sun Apr 29 09:50:22 PDT 2007
of addition/subtraction in
src/mainboard/tyan/s1846/Config.lb, the tyan/s2895 had specified a
different order... wasn't it, i think.
Also tried using lzma on file.elf.
Would love to see more debug output from elfboot. :-/
The patch looks good to me as is.
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Roger
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for
willem.org products. (Or at least this is what I gathered from
mcumall.com customer service.)
But googling, you'll find some such as Firebrand:
http://www.astro.gla.ac.uk/users/paulm/Code/eprom.html
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to me directly
and I'll try on my similar S1832DL.
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Sat Apr 28 14:55:12 PDT 2007
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.)
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On Fri, 2007-04-27 at 00:45 +0200, Uwe Hermann wrote:
On Wed, Apr 25, 2007 at 11:43:49PM -0700, roger wrote:
Index: LinuxBIOSv2.20070425/src/mainboard/tyan/s1846/auto.c
===
--- LinuxBIOSv2.20070425/src/mainboard/tyan/s1846
for bus 00
PCI: 00:00.0 Cannot find pci bus operations
--- End Snip ---
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Thu Apr 26 23:54:57 PDT 2007
LinuxBIOS-2.0.0.0Fallback Thu Apr 26 23:24:18 PDT 2007 starting...
SMBus
On Thu, 2007-04-26 at 23:35 -0700, roger wrote:
On Fri, 2007-04-27 at 00:45 +0200, Uwe Hermann wrote:
Strange, the patch looks correct. Have you tried all variations in this
line (0x2e, 0x4e, 0x3f0, 0x3f8)?
I'm not sure exactly which iobase ports I haven't tried.
But I just realized
On Fri, 2007-04-27 at 00:01 -0700, roger wrote:
I just used Uwe's Tyan S1846 tree and everything *just* worked. :-)
However, I don't mean everything worked.
I've attached a log file of the boot for those curious.
Here's Failure #1 - DRAM Verify Failure
--- Begin Snip ---
DRAM filled
On Fri, 2007-04-27 at 12:13 -0700, roger wrote:
On Fri, 2007-04-27 at 00:01 -0700, roger wrote:
I just used Uwe's Tyan S1846 tree and everything *just* worked. :-)
However, I don't mean everything worked.
I've attached a log file of the boot for those curious.
Here's Failure
denoting what needs work.
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?
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and
0x0400dff8
to 0x0400 and
0x0400dff8
RAM Enable 4: Mode register
set
Computed cas value =
0x01d0
Sending RAM command 0x03addr =
01d0
to 0x01d0 and
0xde28
to 0x040001d0 and 0x0400de28
etc
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Key fingerprint = 8977 A252 2623
On Fri, 2007-04-27 at 17:33 -0700, roger wrote:
I've tried this for tyan/s1846 (adding to intel/440bx/raminit.c) and I
see no change after a diff of my before/after console output log files.
Is there another function I need to add to get output?
ah.. sorry! Figured it out. I should add
of this when I was working on it.
And please always do svn diff from the root of the tree.
sorry.
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console to init. But, I've posted a patch here:
http://www.eskimo.com/~roger/files/linuxbios/440BX.P2XBL/
or, top page where you can see the 440BX boards I own.
http://www.eskimo.com/~roger/programming/linuxbios/index.html
Really, the northbridge problem seems more trivial then a big issue.
IMO, it's
On Wed, 2007-04-25 at 19:26 -0700, roger wrote:
Using a PCI Bios Postcard here and seeing some random Bios Postcodes.
0x80, 0x88, E7
0x80, 0x88, 27
0x80, 0x88, A1, AC
(Notice the 3rd and 4th post_code reported appear random.)
From what I'm guessing, superio devices are configured
LinuxBios Dev guidelines.
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Wed Apr 25 23:32:37 PDT 2007
Add initial support for the following flash chips:
- Atmel AT29C020
- STMicroelectronics M29F002B
- STMicroelectronics M29F002T
displayed here.
Attached a quick patch for review if anybody's interested.
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Wed Apr 25 23:38:18 PDT 2007
Index: LinuxBIOSv2.20070425/src/mainboard/tyan/s1846/auto.c
On Thu, 2007-04-26 at 00:36 -0700, roger wrote:
One last note, with LinuxBiosv2 code that was imported from LinuxBiosv1:
The w83977ef code used in LinuxBiosv1 had an ifdef for the TF chip version to
enabled CIR_DEVICE=6.
For the EF chip version, this isn't needed.
The LinuxBiosv1 code defined
On Fri, 2007-04-27 at 00:49 +0200, Uwe Hermann wrote:
On Wed, Apr 25, 2007 at 07:26:21PM -0700, roger wrote:
I don't know if the above are listed in an order that states these
postcodes should be reported on the device or any order, but I do get
the following reported on my postcard
On Fri, 2007-04-27 at 00:45 +0200, Uwe Hermann wrote:
On Wed, Apr 25, 2007 at 11:43:49PM -0700, roger wrote:
Index: LinuxBIOSv2.20070425/src/mainboard/tyan/s1846/auto.c
===
--- LinuxBIOSv2.20070425/src/mainboard/tyan/s1846
, roger wrote:
diff -uN ./flashrom/README ./flashrom.mine/README
--- ./flashrom/README 2007-04-09 15:59:22.0 -0700
+++ ./flashrom.mine/README 2007-04-20 14:03:52.0 -0700
Try 'svn diff', that's a lot easier :)
+ {M29F040B,ST_ID, ST_M29F040B,NULL
what I'm guessing, superio devices are configured by the 0x88
post_code, but enabling the devices fails???
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You take the time to write an entire o/s in Assembly. :-)
http://www.hermann-uwe.de/
http://www.menuetos.net/
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On Fri, 2007-04-20 at 11:11 +0200, Uwe Hermann wrote:
On Thu, Apr 19, 2007 at 06:17:10PM -0700, roger wrote:
Is it possible to add these parts to FlashRom?
Atmel AT29C020 256k
Read Write seems ok for this Atmel. I've checked using a factory
bios.bin and also writing a linuxbios.rom file
On Thu, 2007-04-19 at 17:46 -0700, roger wrote:
On Fri, 2007-04-20 at 01:20 +0200, Uwe Hermann wrote:
I have ordered a BIOS Post card from siliconkit.com (along with the
recommended extension cable).
Should be getting it this Monday. Got the info from the linuxbios faq
about post codes being
On Wed, 2007-04-18 at 23:23 +0200, Stefan Reinauer wrote:
* roger [EMAIL PROTECTED] [070418 22:26]:
I induced the hang with loading l440gx and then using flashrom.
I then unloaded l440gx and retried executing flashrom which hung.
could you report the problem to david woodhouse
, I'll yank parts out of this Tyan 1832DL to see if the
s1832 built flash boots on it.)
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On Thu, 2007-04-19 at 13:46 +0200, Uwe Hermann wrote:
On Thu, Apr 19, 2007 at 04:09:15AM -0700, roger wrote:
I just built Uwe's s1846 target and saw no output on /dev/ttyS* (serial
port).
What differences should I be concerned about using the s1846 target for
this motherboard 440BX
the source?
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Basically, I should be getting some linuxbios specific output on ttyS*.
Yes. You can put some
print_debug(Hello world!\r\n);
Ok... loaded with Hello world!. ;-)
Shouldn't the DEBUG options in Options.lb Config.lb cover this?
I'll be flashing with these changes until tomorrow.
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.
Currently, I'm just rebooting using a FreeDOS livecd and using UniFlash.
Tedious, but it works. :-/
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Thu Apr 19 18:17:08 PDT 2007
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On Thu, 2007-04-19 at 18:07 -0400, Corey Osgood wrote:
roger wrote:
src/superio/winbond/w83977tf/w83977tf.h appears to me it's in decimal
format compared to src/superio/nsc/pc87309/pc87309.h which is in
hexadecimal format. Could this be an issue?
Also, still not getting output after
}, NULL) = 0
gettimeofday({1176875336, 764059}, NULL) = 0
gettimeofday({1176875336, 764059}, NULL) = 0
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Roger
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Tue Apr 17 23:21:41 PDT 2007
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, but I think what we
want is just the memory location of the flash bios chip (0xfffc)?
I'm taking a quick break and will be back in 30 minutes and will apply
the patch.
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Roger
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Wed Apr 18
part isn't in the flashrom source?
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Roger
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Wed Apr 18 01:49:01 PDT 2007
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-size.patch applied) on my machine, but it failed.
Output from configure:
qemu-0.9.0 $ ./configure --target-list=i386-softmmu
WARNING: gcc looks like gcc 4.x
Looking for gcc 3.x
Found gcc32
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Roger
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F
the lead project engineers gagging in the background
with this one! lol.
Roger
http://www.eskimo.com/~roger/index.html
Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Tue Apr 10 20:26:34 PDT 2007
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actively
working. Another, Dell laptop using the successor to 440bx (can't
remember the chipset off hand).
I've built for Qemu and have a couple of DOC laying around. When I get
time, I'll start building again.
For now, I'm just monitoring the mailing lists with what free time I
get.
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Roger
Not fully working yet, but I do get serial output...
Acked-by: Ronald G. Minnich [EMAIL PROTECTED]
Thanks, committed in r2580.
Uwe.
Just to let you know, my Tyan 1832 also has a 440BX chipset.
Also keeping up to date with by reading all 440 related posts.
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Roger
http
.
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Roger
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Tue Feb 27 13:12:39 PST 2007
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English was (is) bad, so the README should be re-written anyway
to clarify things.
What you just wrote, sounds excellent to me.
(Is it more proper to post Filo related material to the openbios.org
mailing list. If so, I have done so.)
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Roger
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Key fingerprint
-off_Procedure
Cheers, Uwe.
Got it.
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Roger
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Mon Jan 29 11:19:07 PST 2007
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motherboards to provide space for a ziff socket.
From your notes, I'm speculating too Filo is probably working ok and it
might just be having issues under the Qemu emulator.
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Roger
http://www.eskimo.com/~roger/index.html
Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Sun Jan 28
anybody comment on the authenticity of this company?
I was curious about purchasing a PRG-001 Enhanced Willem Universal
EPROM Programmer.
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Roger
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Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Fri May 12 19:09:44 PDT 2006
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