< 0) {
required_modes = clock_required_modes(p->clock);
if (!interface_tsmodes_supported(p->iface,
required_modes)) {
pr_err("interface '%s' does not support
requested "
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is priority1. It is 0 in the working case and 128 in the
failing case. Have you tried changing that?
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ounce
messages with control of 0 and it works, even with dataset_comparison
set to G.8275.x.
It might help if you could provide a packet capture.
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https://
setting up ptp4l with one of regular
> > servos and use the phc2sys to transfer the offset to the NTP daemon.
>
> But that wouldn't work iwith software time stamping, would it?
It wouldn't. phc2sys is needed when ptp4l synchronizes a PHC. With
software timestamping it should be ptp
ers and other fields in the header, or TLVs. It cannot be
prevented.
As PTP is not normally used over Internet, I'd expect any PTP message
routed to Internet to trigger an alarm.
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anyway, is there a configuration you suggest?
I don't know what options are there on Azure. Try something different than
what you are using now.
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ent kernel version.
Issues in SW timestamping are rare.
>
> My system is an Ubuntu 20.04 VM hosted on MS Azure.
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.
That shouldn't matter. The switch should forward unmodified follow-up
messages.
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ces?
If they share the PHC, as suggested by the timemaster output, you
would need to use the new virtual clock feature of the kernel
(available since 5.14, but 5.18+ is recommended) in order to get
hardware timestamping working on both of them. You would need to build
linuxptp from
r our requirements?
Run multiple phc2sys instances configured to not control the clock,
but feed another process like chronyd/ntpd which can select good
sources and combine them for the synchronization of the clock.
With the timemaster program included in linuxptp it is easy to
configur
m network with strace
like this:
strace -erecvmsg ptp4l -m -q -i eth0 -s
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uration? Usually it's a firewall
issue. If the issue was with missing timestamps, ptp4l would print an
error. In my experience, BCM5720 works fine with UDPv4 PTP.
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g and depending on how much you
want to avoid asymmetries in your measurements, it might be better to
have both ports as PPS input timestamping an external PPS signal
instead of connecting one port as PPS output to the other as PPS
input.
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-1 ens3.
> I have used all the default configurations, using the default ptp4l.conf
> file.
Have you allowed the PTP ports (319 and 320) in firewall?
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rently they are at 2
> and 2 respectively.
The example output posted here didn't have the SYNCHRONIZATION_FAULT
messages, so I assumed you were doing something with the servo.
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uld better if
the threshold was automatically adjusted based on the jitter. For an
example, see the "Popcorn spike suppressor" in RFC5905 (NTPv4).
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ing
> the PHC time closer to an imaginary target.
I don't agree with that, but it's not a big deal for me.
I'm just trying to point out that the magnitude of an acceptable clock
error depends on the context. A clock being synchronized is not a
boolean. An initial value
On Fri, Mar 25, 2022 at 02:45:04AM +0200, Vladimir Oltean wrote:
> In general, we all seem to agree that the initial PTP time is largely
> irrelevant until you start looking at it for some particular reason
> (debugging). Or at least, almost everyone seems to agree. I remember
> Miro
d be implemented in the kernel to shorten
that time. I don't know why it takes so long. What is your
logAnnounceInterval and announceReceiptTimeout? Could they be
increased?
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be the same model. That will cancel out
asymmetries in the HW timestamping errors, which can be larger than
the PCIe asymmetry.
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I understand this correctly, you would like to limit the frequency
offset of the clock. ptp4l has the max_frequency option for that. See
the man page.
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pps0 -c CLOCK_REALTIME -o 0
> phc2sys -s CLOCK_REALTIME -c /dev/ptp0 -o 0"
This could work, assuming /dev/pps0 is not a PPS device of /dev/ptp0.
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to be incompatible with '-a'
> flag.
> Should this be reason for that strange behavior?
Yes, without -a phc2sys is not monitoring the port state. It doesn't
matter if it's phc2sys or ntpd via SHM correcting the clock.
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behavior? Is it
> targeted for custom PTP devices that have much better holdover than ntpd
> could ever have?
No, ntpd should be getting samples only when the port is in the slave
state. Did you start phc2sys with the -a option?
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On Tue, Feb 22, 2022 at 05:10:06PM +0100, Jakub Raczyński wrote:
> > 21.02.2022 09:43 Miroslav Lichvar wrote:
> > It might help if you could post some logs that show the problem with
> > corresponding packet capture.
>
> Sure thing.
> So here is a setup - devic
bout it much sooner.
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r 2021 )
>
> please suggest: can expiration_date_ntp be read from config as to avoid
> frequent runtime check .
The leap table can be read from the file specified by the leapfile
option. That includes the expiration date. See the ts2phc man page.
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call of the function instead of just once per the minimum interval.
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ting
> in variation of min and max freq_offset calculation.
The timestamp checked in the clockcheck code should always be a
timestamp of the clock synchronized by phc2sys, not the clock to which
it is synchronized (what I assume you mean by "remote"). Can you point
to the
is needed, the PTP specification allows messages to be
padded to (almost) any length with the PAD TLV, but I'm not sure if it
is supposed to be the only way.
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to
about -68135 seconds. That is very suspicious.
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of the protocol.
There is a testsuite using simulations:
https://github.com/mlichvar/linuxptp-testsuite
Depending on what exactly you need to test, you could just modify one
of the existing scripts.
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configuration is ok.
Try to get ptp4l working with SW timestamping first. Then you can
enable HW timestamping and only when that works, you should switch to
timemaster.
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pr_debug?
That might not be necessary. There was a change in the development
code to suppress that message in the client-only mode. It would be
good to confirm whether this configuration is still affected.
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ve mode.
AFAIK that's not possible with the current ptp4l design as it works
only with a single clock at a time. With the other bonding modes the
timestamping interface can change with each message. If ptp4l tried to
follow that, it would not synchronize.
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a PTP
> clock? Or that maybe its receiving a hardware clock?
That field is an index or "none". If it's 1, it means you have
multiple PTP clocks and this is the second one. The first one has 0.
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expected that
under a higher PTP load it will not be able to timestamp all received
packets? Not saying that is what is happening in this case, but I
think people sometimes seeing the "received SYNC/DELAY_REQ without
timestamp" message is expected.
-
tp4l
> consistently?
> Logs on Slave:
>
> ptp4l[1323.209]: master offset -74 s3 freq -123 path delay 15014
> ptp4l[1324.209]: master offset -114 s3 freq -185 path delay 15014
The measured delay is very large. Are there any switches between
into pmc, and to avoid the time it takes to execute
> a system command integrated pmc into our process.
Instead of changing the hardcoded values, maybe a new option could be
considered?
Thanks,
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have an option to specify the namespace, but I think you
could write a script to execute it there and specify it as the ptp4l
path in the timemaster configuration.
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f stepping.
Have you set the step_threshold option for ptp4l and -S for phc2sys?
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locksource, e.g.
echo hpet > /sys/devices/system/clocksource/clocksource0/current_clocksource
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rested in
the kernel version, NIC and its driver.
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w CPU load
could trigger those warnings. I suspect it's a HW/driver specific
issue. Do you have any details on that?
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ntpd service and killing the timemaster's ntpd process
for an NTP server received from DHCP? Do you see anything in the
system log around that time it happens?
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c2sys and chronyd/ntpd would
need to be able to reverse the direction of the synchronization using
the SHM refclock.
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ds to be synchronized.
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econds, not much worse
than on real computers with NICs on PCIe. The absolute TX/RX errors
were significantly larger (around 60-80 microseconds).
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ficient ethernet (EEE) - this helps with HW
timestamping too
To improve accuracy, use the same HW, SW, and configuration on the
master and slave, so the errors in RX/TX timestamping cancel out.
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ot when you added everything your can think of, but instead
> have removed everything you can.
If you have only one PTP time source, you can use the default paths.
With multiple sources that won't work.
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On Wed, May 13, 2020 at 09:02:09AM -0700, Gary E. Miller wrote:
> > ntpd expects samples relative to the system clock, so feeding it
> > samples relative to the NIC clock from ptp4l won't work.
>
> Yeah, clearly broken. Why would ptp4l ever send anything to ntpd that
> ntpd can not understand?
offset between the two clocks. The
timemaster program can show you the right configuration or run the
programs.
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her HW, like an Intel CPU with the ART.
Assuming you can measure the timestamping errors of the onboard NIC
(which doesn't have a PPS input or output), right?
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o system clocks. That includes the PCIe delay, delays in HW
timestamping and the network delay. Of course, if you had some magic
hardware that allowed you to measure the error directly, you could
compensate for it in ptp4l/phc2sys configuration.
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e output is as follow:
> phc2sys[482428.142]: failed to adjust the clock: Invalid argument
That's odd.
What linuxptp and kernel versions are you using?
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cted. How is the PHC on master
synchronized? By phc2sys to the system clock? How is the system clock
synchronized? PTP, NTP, reference clock?
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ssion denied
It's a selinux issue:
https://bugzilla.redhat.com/show_bug.cgi?id=1759212
A workaround is to add a custom rule (module), or disable selinux.
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ore independent time sources, it should work even when one
of them starts providing wrong time (due to a leap second, buggy/old
GPS firmware, etc.).
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ble if you start timemaster in terminal.
# timemaster -f /etc/timemaster.conf
254 is an out of range value for option domainNumber at line 3
failed to parse configuration file /var/run/timemaster/ptp4l.0.conf
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Start=/usr/sbin/phc2sys $OPTIONS (code=exited,
> status=255)
> Main PID: 4169 (code=exited, status=255)
>
> But phc2sys -w -s eno2 -m output work properly
What is in the /etc/sysconfig/phc2sys file?
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t; ptp4l[82815.946]: master offset -6397699726 s2 freq -32767999 path delay
>-889
This doesn't look right to me. Either the HW/driver is broken, or the
master is correcting a large offset too.
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o be the GM before the real one is running, or allow multiple
steps, assuming that's really the problem you are hitting.
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documented in the man page.
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On Tue, Jul 02, 2019 at 09:31:44AM -0700, Richard Cochran wrote:
> On Tue, Jul 02, 2019 at 09:36:50AM +0200, Miroslav Lichvar wrote:
> > So, with two
> > directly connected I210s (short cable) the measured delay should be
> > close to zero.
>
> That is true of any t
ugh. Note that
the timestamping errors may depend on the network load and
configuration of the NIC, so make sure your testing environment is
similar to the production environment.
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he values you have provided, as I have explained in a previous
post.
769 + 169 = 938
(769 - 169) / 2 = 300
This assumes the timestamping on the I210 is perfectly compensated,
which it is not. And that the cable has zero length. You can tweak it
as neces
and see which brings the offset between the two PPS signals closer to
zero.
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measuring. It would help if
you could describe your setup in more detail. What is connected to
what and how it is synchronized.
As a quick test I'd suggest to set ingressLatency and egressLatency on
the non-I210 clock to 470. That may fix the delay, but not offset.
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mestamping error of the other end. If the clocks can be
synchronized independently from their HW timestamping (e.g. PPS
input/output), the measured offset should correspond to the (TX-RX)/2
error. When both TX+RX and (TX-RX)/2 are known, TX and RX can be
ry it with the latest linuxptp code in git. It may already be
supported.
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nce in the HW. If the two
boards performed exactly the same, there should be no difference in
the measured offset.
I'm not sure what that could be. Maybe the CPU is throttling due to
high temperature? On x86_64 frequency scaling (power saving, turbo) is
a major problem for phc2sys, causing unstable mea
051-g450b1ed" when "-v") for
> 24h the result is even worse? (figure attached)
Hm. Interesting. If the HW, SW and PPS are identical, I'm not sure
what else it could be.
What happens when you swap the master/slave roles? Does the offset
c
it?
Another explanation might a difference in the PPS signals. Do they
come from one GPS receiver, or are there two receivers (using the same
model, firmware, configuration and located at the same place)?
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50380 ns
XXV710 250 ns
BCM5720 600 ns
MT27800 250 ns
If someone could figure out the minimum possible time a PCIe message
of a specific length needs to get from the CPU to the NIC, that could
be subtracted from those maximums.
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it path in the driver:
>
> skb_tx_timestamp(skb);
> if I modify the nic driver with above changes then will ptp4l able to
> start the ptp service ?
Yes.
I'd suggest to look at the current Linux code. It's likely the driver
already has this call and you would just backport that change to y
_SOFTWARE capability, which is not printed by
ethtool.
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k with -r -r). When server 1 is back, they
will quickly resynchronize with it. That may or may not be what you
want.
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stants I should use are not exactly self
> evident for a PTP beginner – and likewise for which algorithms will give the
> most accuracy. Based on my readings, I assume a stable jitter around 50 ns
> should be possible.
With good switches with PTP support jitter of 50 nanosecond might be
a blog post showing how this HW can be used for NTP. The same
could be done with PTP. (There is actually a related discussion on the
-devel list about adding the PPS support to phc2sys)
https://blog.dan.drown.org/apu2-ntp-server-2/
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in your mail is ok, but the text version is bad.
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On Mon, Nov 05, 2018 at 08:52:02AM +0100, Miroslav Lichvar wrote:
> On Mon, Nov 05, 2018 at 11:38:47AM +0530, Dolly Gyanchandani wrote:
> > *phc2sys Command on Slave*
> >
> > phc2sys -s em1 -c CLOCK_REALTIME -w -m
>
> Can you please try "phc2sys -a -m&
t;
> *phc2sys Command on Slave*
>
> phc2sys -s em1 -c CLOCK_REALTIME -w -m
Can you please try "phc2sys -a -m" ?
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On Fri, Nov 02, 2018 at 04:05:12PM +0100, Miroslav Lichvar wrote:
> For setting the UTC-TAI offset there is also ntptime from ntp and a
> (slightly?) different adjtimex(8) which is packaged in some
> distributions:
>
> http://ftp.debian.org/debian/pool/main/a/adjtimex/
Which a
rg/debian/pool/main/a/adjtimex/
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t also the slave's phc2sys command line?
> Is there any other way to access TAI time / UTC-TAI offset
> programmatically?
You could program a pmc client.
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t being set (verified by
> ntptime command)
Is ptpTimescale 1?
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tpTimescale 1?
Are you using phc2sys -a?
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CLOCK_TAI shows
> the same time as the CLOCK_REALTIME.
>
> Does PTP not override the kernel parameter tai_offset?
Both ptp4l and phc2sys should do that. Does pmc on the slave print
"currentUtcOffsetValid 1" and "timeTraceable 1" ?
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k. But is there a way to get TAI time?
The kernel provides the CLOCK_TAI clock for applications. It can be
read with the clock_gettime() function.
If you just need the UTC-TAI offset, there is the ntp_gettime()
function.
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ivers (which might be fixed in near future).
Measuring accuracy of the system clock has the same problem.
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o 13611908ns (7237916ns) in ca 4.h min.
Is testptp using the right clock? I think by default it uses
/dev/ptp0. If eth1 has a different PHC index, you need to specify it
with -d. You can check it with ethtool -T eth1.
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d be to add an option for dropping root
privileges to ptp4l. Start with root, open all PHCs, bind sockets, etc
and then drop the privileges, keeping only the SYS_TIME and maybe the
BIND_SERVICE capabilities.
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t ppb: 2faf07
> elay 3752
This does look like a HW/driver issue. The local PTP clock is suddenly
behind by 199 milliseconds, so ptp4l speeds up the clock to catch up
with the true time.
Or the GM is skipping ahead. But I assume you have tried it with SW
timestamping and it
have a ptp4l/phc2sys log showing
the offset and frequency values increasing?
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e. There should be an error
message in the system log pointing to the line which caused the parser
to fail. You will need to include the settings from the file in
timemaster.conf prefixed with "ptp4l_option".
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On Wed, May 02, 2018 at 06:58:56AM -0700, Richard Cochran wrote:
> On Tue, Apr 24, 2018 at 09:15:49AM +0200, Miroslav Lichvar wrote:
> > I have a pair of directly connected X550 cards, which behave a bit
> > like SyncE with the frequency. Their clocks seem to be locked to each
&g
s://i.imgur.com/jp3ZE3Z.png
Unless they have a hidden chip-scale atomic clock, I think they must
be synchronized to each other in some way. Maybe something was
implemented in preparation for SyncE support?
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Miroslav Lichvar
-
ds out to other PTP clients?
No, that's not supported. You need to synchronize the system clock or
a PHC with another program and then you can use the clock to serve
time to PTP slaves with ptp4l.
--
Miroslav Lichvar
-
into a pure "P" servo.
--
Miroslav Lichvar
--
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