On Mon, 2017-01-23 at 14:12 -0800, Jason Ekstrand wrote:
> As per VK_KHR_maintenance1, setting a negative height in the viewport
> can be used to get flipped coordinates. This is, aparently, very
> useful
> when porting D3D apps to Vulkan. All we need to do to support this
> is
> to make sure we
On Mon, 2017-01-23 at 14:12 -0800, Jason Ekstrand wrote:
> As of VK_KHR_maintenance1, these are supposed to be reported for any
> formats on which we support transfer operations. For us, this is
> anything that we can texture from.
> ---
> src/intel/vulkan/anv_formats.c | 9 -
> 1 file ch
I dropped a couple of minor comments on patches 1 and 3, but otherwise
the series is:
Reviewed-by: Iago Toral Quiroga
On Mon, 2017-01-23 at 14:12 -0800, Jason Ekstrand wrote:
> This little series implements the new VK_KHR_maintenance1
> extension. Most
> of the patches are pretty t
FWIW, vulkan-cts seems happy.
Reviewed-by: Iago Toral Quiroga
On Thu, 2017-01-26 at 09:27 -0800, Jason Ekstrand wrote:
> I'm pretty sure we've kept up with the bug fixes.
> ---
> src/intel/vulkan/anv_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Topi, could you review this one?
This was introduced recently with the implementation of Queries in the
Vulkan driver and since the CTS OOM tests have not landed yet Jenkins
won't catch these issues for now.
Iago
On Wed, 2017-03-22 at 10:15 +0100, Iago Toral Quiroga wrote:
> We don&#
On Wed, 2017-03-22 at 21:01 -0700, Jason Ekstrand wrote:
---
src/intel/vulkan/anv_private.h | 6 ++
src/intel/vulkan/genX_cmd_buffer.c | 141
-
src/intel/vulkan/genX_pipeline.c | 10 ++-
3 files changed, 152 insertions(+), 5 deletions(-)
diff --git a/
On Thu, 2017-03-23 at 14:28 +0100, Iago Toral wrote:
> The proposed implementation makes sense to me, I looked through
> patches
> 1-8 and they all look good as well, so those are:
Pateches 9, 19 and 12 are also:
Reviewed-by: Iago Toral Quiroga
I left some comments in patch 11.
>
On Fri, 2017-03-24 at 16:57 -0700, Jason Ekstrand wrote:
> On Fri, Mar 24, 2017 at 5:53 AM, Iago Toral
> wrote:
> > On Wed, 2017-03-22 at 21:01 -0700, Jason Ekstrand wrote:
> > ---
> > src/intel/vulkan/anv_private.h | 6 ++
> > src/intel/
On Tue, 2017-03-28 at 08:28 -0700, Jason Ekstrand wrote:
> Sorry I haven't gotten back on this. It got lost somehow.
>
> On Fri, Mar 10, 2017 at 1:56 AM, Iago Toral
> wrote:
> > On Thu, 2017-03-09 at 14:05 -0800, Jason Ekstrand wrote:
> > > -
Can anyone review this one?
On Wed, 2017-03-29 at 08:58 +0200, Iago Toral Quiroga wrote:
> Writing and testing are two different things and they can be set
> separately
> by the application. If an application wants to record depth data
> without
> caring for the depth test, it c
On Mon, 2017-04-03 at 08:55 -0700, Nanley Chery wrote:
> On Mon, Apr 03, 2017 at 08:02:54AM +0200, Iago Toral wrote:
> >
> > Can anyone review this one?
> >
> > On Wed, 2017-03-29 at 08:58 +0200, Iago Toral Quiroga wrote:
> > >
> > > Writing and tes
On Tue, 2017-04-04 at 19:21 -0700, Jason Ekstrand wrote:
> Before, we were just looking at whether or not the user wanted us to
> wait and waiting on the BO. This instead makes us busy-loop on each
> query until it's available. This reduces some of the pipeline
> bubbles
> we were getting and imp
Reviewed-by: Iago Toral Quiroga
On Tue, 2017-04-04 at 15:38 -0700, Jason Ekstrand wrote:
> We already provide a default LOD for textureQueryLevels and texture()
> on
> non-fragment stages. However, there are more cases where one is
> needed
> such as textureSize(gsampler2
On Wed, 2017-04-05 at 09:31 -0700, Jason Ekstrand wrote:
> On Wed, Apr 5, 2017 at 12:24 AM, Iago Toral
> wrote:
> > On Tue, 2017-04-04 at 19:21 -0700, Jason Ekstrand wrote:
> > > Before, we were just looking at whether or not the user wanted us
> > to
> > &g
Reviewed-by: Iago Toral Quiroga
On Thu, 2017-04-06 at 14:43 +1000, Timothy Arceri wrote:
> This doesn't do anything useful so just remove it.
> ---
> src/mesa/main/shaderimage.c | 5 +++--
> src/mesa/main/texobj.c | 17 ++---
> src/mesa/main/texobj.h
Reviewed-by: Iago Toral Quiroga
On Wed, 2017-04-05 at 21:16 -0700, Jason Ekstrand wrote:
> Commit f938354362655a378d474c5f79c52cea9852ab91 recently increased
> the
> alignment on vertex buffer data from 32 to 64. This caused us to
> consume a bit more batch than we were before a
All 3 patches (assuming Dylan's fine with patch 1) are:
Reviewed by: Iago Toral Quiroga
On Wed, 2017-04-19 at 17:17 -0700, Jason Ekstrand wrote:
> ---
> src/intel/genxml/gen_pack_header.py | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --gi
s/order/sort :)
Reviewed-by: Iago Toral Quiroga
On Thu, 2017-04-20 at 14:02 +0200, Samuel Iglesias Gonsálvez wrote:
> It helps to find the envvar you are looking for.
>
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> docs/en
Reviewed-by: Iago Toral Quiroga
On Thu, 2018-05-31 at 17:21 -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Some trivial help now, but it also prevents ~40 regressions caused by
> Samuel's "nir: implement the GLSL equivalent of if simplication in
> nir_opt
On Fri, 2018-06-01 at 11:25 +0200, Juan A. Suarez Romero wrote:
> On Wed, 2018-05-30 at 15:10 -0700, Eric Anholt wrote:
> > "Juan A. Suarez Romero" writes:
> >
> > > Implement ir_binop_vector_extract using NIR operations. Based on
> > > SPIR-V
> > > to NIR approach.
> > >
> > > This fixes:
> > >
On Fri, 2018-06-01 at 12:26 +0200, Iago Toral wrote:
> On Fri, 2018-06-01 at 11:25 +0200, Juan A. Suarez Romero wrote:
> > On Wed, 2018-05-30 at 15:10 -0700, Eric Anholt wrote:
> > > "Juan A. Suarez Romero" writes:
> > >
> > > > Implement ir
This isn't reviewed yet, any feedback?
Iago
On Tue, 2018-05-15 at 13:05 +0200, Iago Toral Quiroga wrote:
> NIR assumes that all booleans are 32-bit, so drivers need to produce
> 32-bit
> booleans even if they can produce native booleans of a different bit-
> size, like
> In
On Fri, 2018-06-15 at 00:20 +0200, Chema Casanova wrote:
>
> On 14/06/18 03:26, Jason Ekstrand wrote:
> > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo
> > mailto:jmcasan...@igalia.com>> wrote:
> >
> > do_untyped_vector_read is used at load_ssbo and load_shared.
> >
> > The
On Thu, 2018-06-14 at 17:43 -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> fs_visitor::set_gs_stream_control_data_bits generates some code like
> "control_data_bits | stream_id << ((2 * (vertex_count - 1)) % 32)" as
> part of EmitVertex. The first time this (dynamically) occurs in the
> sha
On Thu, 2018-06-14 at 17:43 -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Skylake
> total instructions in shared programs: 14399081 -> 14399010 (<.01%)
> instructions in affected programs: 26961 -> 26890 (-0.26%)
> helped: 57
> HURT: 0
> helped stats (abs) min: 1 max: 6 x̄: 1.25 x̃: 1
> hel
I dropped a suggestion in patch 1 that also applies to patch 3, feel
free to take it or not, and then I pointed out a small issue in patch 6
that I think should be addressed that I think should be fixed.
Otherwise, the series is:
Reviewed-by: Iago Toral Quiroga
On Thu, 2018-06-14 at 17:43 -0700
uldn't you also update the if condition on line 178? Otherwise,
> you won't reach the if tree you change when the vertex shader is
> missing (unless that was intended - I am not really familiar with how
> fixed function shaders work alongside new features).
You don't have Te
On Mon, 2018-06-18 at 10:45 +0200, Gustaw Smolarczyk wrote:
> 2018-06-18 10:39 GMT+02:00 Iago Toral :
> > On Mon, 2018-06-18 at 09:43 +0200, Gustaw Smolarczyk wrote:
> > > 2018-06-18 4:39 GMT+02:00 Timothy Arceri :
> > > > This is required for
t;Const.GLSLVersionCompat = ctx->Version * 10;
> + }
> break;
Looks like we should be able to just do this after the switch right?:
ctx->Const.GLSLVersionCompat = ctx->Const.GLSLVersion;
I'd prefer this unless there is something I am missing.
With that:
Reviewed-by: Iago Toral Quiroga
>}
> }
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Reviewed-by: Iago Toral Quiroga
On Mon, 2018-06-18 at 11:40 +0100, Eric Engestrom wrote:
> Fixes: 67f40dadaadacd90 "mesa: add support for
> ARB_sample_locations"
> Cc: Rhys Perry
> Cc: Brian Paul
> Signed-off-by: Eric Engestrom
> ---
> src/mesa/main/fbobje
Hi Andrii,
thanks for the fix!
Kenneth, this patch makes it so that we end the GS program with and
ENDIF. I remember that back in the day when I wrote this code you had
concerns about that (that's why I added that comment), but that was a
long time ago so maybe things have changed, do you know if
On Tue, 2018-06-19 at 17:06 +0300, Andrii Simiklit wrote:
> We can not use the VUE Dereference flags combination for EOT
> message under ILK and SNB because the threads are not initialized
> there with initial VUE handle unlike Pre-IL.
> So to avoid GPU hangs on SNB and ILK we need
> to avoid usage
o manage
>the resources (e.g., scratch space) allocated to those threads.
>
>Programming Note: [Pre-DevIL] GS and Clip threads must terminate
>by sending a URB_WRITE message (with EOT set) with the Complete
> bit also
>set (therein returning a URB handle marke
Hi Andrii,
thanks for verifying my suggestion and sending the new patch.
However, this patch is the diff against your previous patch, please
merge both patches into a single patch so we get a single patch with
all the changes against current master. Once we have that I'll run the
resulting patch
Thanks Andrii, this version looks good to me.
Mark: this change fixes a GPU hang in sandy bridge with geometry
shaders (the change itself affects a path in the driver that is only
executed in SNB with GS, so nothing else is affected). While I think
the change in here is correct according to the PR
Thanks for testing Mark.
Andrii, I'll add my Reviewed-by and and push the patch to master later
today (I'll also queue it for the next stable release).
Thanks for fixing this!
Iago
On Fri, 2018-06-22 at 13:18 -0700, Mark Janes wrote:
> Tested-by: Mark Janes
>
>
On Tue, 2018-06-26 at 10:59 -0700, Jason Ekstrand wrote:
> On Tue, Jun 26, 2018 at 4:08 AM, Iago Toral Quiroga m> wrote:
> > Storage images require to patch push constant stateto work, which
> > happens during
> >
> > binding table emision. In the scenario where ou
On Wed, 2018-06-27 at 09:13 -0700, Jason Ekstrand wrote:
> On Wed, Jun 27, 2018 at 2:25 AM, Iago Toral
> wrote:
> > On Tue, 2018-06-26 at 10:59 -0700, Jason Ekstrand wrote:
> > > On Tue, Jun 26, 2018 at 4:08 AM, Iago Toral Quiroga > > a.com> wrote:
> > >
On Thu, 2018-06-28 at 08:47 +0200, Iago Toral wrote:
> On Wed, 2018-06-27 at 09:13 -0700, Jason Ekstrand wrote:
> > On Wed, Jun 27, 2018 at 2:25 AM, Iago Toral
> > wrote:
> > > On Tue, 2018-06-26 at 10:59 -0700, Jason Ekstrand wrote:
> > > > On Tue, Jun 26,
On Sun, 2018-07-01 at 18:30 -0500, Jason Ekstrand wrote:
> On June 29, 2018 03:11:00 Iago Toral Quiroga
> wrote:
>
> > ---
> > src/intel/vulkan/anv_private.h | 5 +
> > src/intel/vulkan/genX_cmd_buffer.c | 12 +++-
> > 2 files chang
On Sun, 2018-07-01 at 18:32 -0500, Jason Ekstrand wrote:
> 1-3 are R-b me. Should we cc stable?
Yes, I think these should go to stable.
> On June 29, 2018 03:11:00 Iago Toral Quiroga
> wrote:
>
> > Every time we emit a new state base address we will need to re-emit
> >
Sure, I will add that.
> Regardless this series is :
>
> Reviewed-by: Lionel Landwerlin
Thanks, I'll push the first 3 for now.
> Thanks!
>
> On 29/06/18 09:10, Iago Toral Quiroga wrote:
> > If we have to re-emit push constant data, we need to re-emi
For the series:
Reviewed-by: Iago Toral Quiroga
On Fri, 2018-06-29 at 17:13 -0700, Jason Ekstrand wrote:
> This little series adds an optimization pass to NIR and wires up up
> in anv
> that moves large constant variables to a UBO. This fixes a farily
> common
> case in some fi
On Mon, 2018-07-02 at 08:23 -0500, Jason Ekstrand wrote:
> On July 2, 2018 01:09:38 Iago Toral wrote:
>
> > On Sun, 2018-07-01 at 18:30 -0500, Jason Ekstrand wrote:
> > > On June 29, 2018 03:11:00 Iago Toral Quiroga
> > > wrote:
> > >
> > > >
On Tue, 2018-07-03 at 18:45 -0700, Caio Marcelo de Oliveira Filho
wrote:
> Hi,
>
>
> > + /* Look for any follow-up instructions that sources from the
> > boolean
> > +* result of the producer instruction and rewrite them to use
> > the correct
> > +* bit-size.
> > +*/
> > + foreac
Reviewed-by: Iago Toral Quiroga
On Wed, 2018-04-18 at 22:57 +0200, Jose Maria Casanova Crespo wrote:
> All operations with offset_reg at do_vector_read are done
> with UD type. So copy propagation was not working through
> the generated MOVs:
>
> mov(8) vgrf9:UD, vgrf7:D
>
&g
Hi,
while developing support for Vulkan shaderInt16 on Anvil I came across
a feature of NIR that was a bit inconvenient: bools are always 32-bit
by design, but the Intel hardware produces 16-bit bool results for 16-
bit comparisons, so that creates a problem that manifests like this:
vec1 32 ssa_
On Fri, 2018-04-20 at 17:16 -0700, Jason Ekstrand wrote:
> On Fri, Apr 20, 2018 at 5:16 AM, Nicolai Hähnle
> wrote:
> > On 20.04.2018 10:21, Iago Toral wrote:
> >
> > > Hi,
> > >
> > >
> > >
> > > while developing support for
2018 at 9:56 AM, Jason Ekstrand >
> wrote:
> It may be useful to just use nir_algebraic for this. We already do
> for
> trig
> workarounds. It's more painful from a build-system perspective but,
> in
> general, the fewer hand-rolled algebraic lowering passes we have, t
On Tue, 2018-04-24 at 07:58 -0700, Jason Ekstrand wrote:
> On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga om> wrote:
> > The lowering pass was specialized to act on 64-bit to 32-bit
> > conversions only,
> >
> > but the implementation is valid for other cas
Thanks Neil!
Reviewed-by: Iago Toral Quiroga
Maybe we need other drivers (radv?) to double-check that this doesn't
break stuff for them either?
Iago
On Tue, 2018-04-24 at 16:55 +0200, Neil Roberts wrote:
> For all of the OpFOrd* comparisons except OpFOrdNotEqual the hardware
> shou
On Wed, 2018-04-25 at 07:05 -0700, Jason Ekstrand wrote:
> Some of these comments may be duplicates of ones I made the first
> time through.
>
> On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga om> wrote:
> > The hardware doesn't support 16-bit integer types, s
On Mon, 2018-04-30 at 14:43 -0700, Jason Ekstrand wrote:
> On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga m> wrote:
> > NIR assumes that booleans are always 32-bit, but Intel hardware
> > produces
> >
> > 16-bit booleans for 16-bit comparisons. This mea
On Wed, 2018-05-02 at 17:57 -0700, Jason Ekstrand wrote:
> Reviewed-by: Jason Ekstrand
>
> Have I reviewed everything? Can we land shaderInt16 now?
Yes, all patches are reviewed now, thanks Jason.I'll send the final set
of patches to Jenkins one last time and push them today if we don't
see an
On Thu, 2018-05-03 at 08:39 +0200, Iago Toral wrote:
> On Wed, 2018-05-02 at 17:57 -0700, Jason Ekstrand wrote:
> > Reviewed-by: Jason Ekstrand
> >
> > Have I reviewed everything? Can we land shaderInt16 now?
>
> Yes, all patches are reviewed now, thanks Jason.
&
On Thu, 2018-05-03 at 11:44 -0700, Clayton Craft wrote:
> Quoting Iago Toral Quiroga (2018-04-30 07:18:08)
> > This version addresses the feedback received to v1, which includes
> > moving the
> > bit-size lowering pass from intel to core NIR (patch 8) and a
> > separa
On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> Now that anv uses blorp_ccs_op for everything, we no longer need to
> expose the ccs_ambiguate function directly. It's much better tucked
> away as an implementation detail.
> ---
> src/intel/blorp/blorp.h | 5 -
> src/intel/bl
On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index dab04f2..b6097f5 100
On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> ---
> src/intel/blorp/blorp_clear.c | 199 +++-
> --
> 1 file changed, 88 insertions(+), 111 deletions(-)
>
> diff --git a/src/intel/blorp/blorp_clear.c
> b/src/intel/blorp/blorp_clear.c
> index 39bc0c6
On Wed, 2018-05-16 at 13:34 +0200, Iago Toral wrote:
> On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> > ---
> > src/intel/blorp/blorp_clear.c | 199 +++---
> > --
> > --
> > 1 file changed, 88 insertions(+), 111 delet
case, patches 3-9 are:
Reviewed-by: Iago Toral Quiroga
Iago
On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> This little series makes a bunch of mostly small changes to
> blorp. The end
> objective is to get to the point where you just call blorp_ccs_op and
> hand
> it an i
On Wed, 2018-05-16 at 08:44 -0700, Jason Ekstrand wrote:
> On Wed, May 16, 2018 at 4:00 AM, Iago Toral
> wrote:
> > On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> >
> > > Now that anv uses blorp_ccs_op for everything, we no longer need
> > to
&g
On Thu, 2018-05-17 at 06:59 -0700, Jason Ekstrand wrote:
>
> On May 17, 2018 01:47:11 Iago Toral Quiroga
> wrote:
>
> > ---
> > src/compiler/spirv/vtn_alu.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/compile
On Mon, 2018-05-21 at 13:49 +0300, Eero Tamminen wrote:
> Hi,
>
> On 21.05.2018 10:42, Iago Toral wrote:
> > On Fri, 2018-05-18 at 12:08 +0300, Eero Tamminen wrote:
> > > On 17.05.2018 14:25, Eero Tamminen wrote:
> > > > On 17.05.2018 11:46, Iago Toral Quir
Hi Andrey,
Thanks for the report and all the analysis work on your side. I am on
holidays at the momentand from tomorrow onwards I won't have reliable
internet access but Samuel will be back fromhis vacaction next week and
he might be be able to have a look at the problem and your patch.
Thanks,Iag
On Mon, 2018-09-17 at 09:43 -0500, Jason Ekstrand wrote:
> This pass re-materializes deref instructions on a per-block basis to
> ensure that every use of a deref occurs in the same block as the
> instruction which uses it.
> ---
> src/compiler/nir/nir.h | 1 +
> src/compiler/nir/nir_deref
Should we add a similar check to validate_phi_src in nir_validate.c?
On Mon, 2018-09-17 at 09:43 -0500, Jason Ekstrand wrote:
> The lcssa and phis_to_regs passes are used by various NIR
> optimizations
> that modify the CFG. Putting a couple of asserts will help ensure
> that
> we don't accidenta
Hi Jason,
I left a few comments in patches 1 and 4, feel free to ignore them if
you think they are not relevant. Either way the series is:
Reviewed-by: Iago Toral Quiroga
On Mon, 2018-09-17 at 09:43 -0500, Jason Ekstrand wrote:
> This pass re-materializes deref instructions on a per-bl
On Tue, 2018-09-18 at 07:27 -0500, Jason Ekstrand wrote:
> On Tue, Sep 18, 2018 at 4:11 AM Iago Toral wrote:
> > Hi Jason,
> >
> >
> >
> > I left a few comments in patches 1 and 4, feel free to ignore them
> > if
> >
> > you think they are n
Reviewed-by: Iago Toral Quiroga
Grabriel: do you need someone else to push the patch for you?
Iago
On Sun, 2018-08-26 at 21:48 +0300, Gabriel Majeri wrote:
> This is the minimum value according to the spec.
> ---
> src/intel/vulkan/anv_device.c | 2 +-
> 1 file changed, 1 ins
On Sat, 2018-09-22 at 16:39 -0500, Jason Ekstrand wrote:
> Previously, we would create temporary variables and fill them out.
> Instead, we create as many function parameters as we need and pass
> them
> through as SSA defs.
(...)
> void
> vtn_handle_function_call(struct vtn_builder *b, SpvOp o
On Sat, 2018-09-22 at 16:39 -0500, Jason Ekstrand wrote:
> If the block in which the jump is inserted is the predecessor of a
> phi
> then we need to remove phi sources otherwise the phi may end up with
> things improperly connected. Found by running the Vulkan CTS with
> SPIR-V optimizations enab
Letf a couple of minor comments, but otherwise the series is:
Reviewed-by: Iago Toral Quiorga
On Sat, 2018-09-22 at 16:39 -0500, Jason Ekstrand wrote:
> This little series fixes three bugs encountered while running the
> Vulkan
> CTS with SPIR-V optimizations enabled. The opti
On Tue, 2018-10-02 at 12:54 +0200, Iago Toral wrote:
> Letf a couple of minor comments, but otherwise the series is:
>
> Reviewed-by: Iago Toral Quiorga
s/Quiorga/Quiroga
> On Sat, 2018-09-22 at 16:39 -0500, Jason Ekstrand wrote:
> > This little series fixes three bugs
On Tue, 2018-10-02 at 07:50 -0500, Jason Ekstrand wrote:
> On Tue, Oct 2, 2018 at 7:30 AM Jason Ekstrand
> wrote:
> > On Tue, Oct 2, 2018 at 5:53 AM Iago Toral
> > wrote:
> > > On Sat, 2018-09-22 at 16:39 -0500, Jason Ekstrand wrote:
> > >
> > > &g
Hi Vadym,
I think this looks correct, but I was wondering if you considered
implementing this check in ir_reader::read_function_sig (ir_reader.cpp)
instead, which runs at compile time. My rationale is that given the
option, I think it is preferable to push work to compile time rather
than link tim
tinct
> shader objects.
>
> What do you think ?
Since we need to keep the link-time check, any compile-time checks we
add would be redundant with that, so I think we should just go with the
link-time check only (your original patch)
Once you have addressed Tapani's comment feel free
Jenkins is good, I have pushed the patch with a small style fix and a
v2 tag in the commit log.
Iago
On Thu, 2018-10-04 at 10:15 +0300, Vadim Shovkoplias wrote:
> Thanks, I'll appreciate if you will push the patch once test will be
> finished.
> чт, 4 окт. 2018 г. в 9:52, Iago Tora
I was about to write about this too. I think the patch is not
correct for a couple of reasons:
1. GL_FRAMEBUFFER_INCOMPLETE_DIMENSIONS is not defined for OpenGL,
only for GL ES. The GL definition has the _EXT suffix and is included
with a specific extension, so I don't think we can use it like th
On Mon, 2018-11-19 at 10:21 +0100, Iago Toral wrote:
> I was about to write about this too. I think the patch is not
> correct for a couple of reasons:
>
> 1. GL_FRAMEBUFFER_INCOMPLETE_DIMENSIONS is not defined for OpenGL,
> only for GL ES. The GL definition has the _EXT suffix
Thanks!
Reviewed-by: Iago Toral Quiroga
On Mon, 2018-11-19 at 10:36 +0100, Gert Wollny wrote:
> FRAMEBUFFER_INCOMPLETE_DIMENSIONS is not supported for GLES 3.0 and
> later and
> not defined for Desktop OpenGL. Instead use FRAMEBUFFER_UNSUPPORTED
> like it
> was done before.
For both patches:
Reviewed-by: Iago Toral Quiroga
On Wed, 2018-11-21 at 17:20 -0600, Jason Ekstrand wrote:
> It affects apply_pipeline_layout. Shaders compiled with the wrong
> value
> will work but they may not be robust as requested by the app.
>
> Cc: mesa-sta...@lists.
Reviewed-by: Iago Toral Quiroga
On Tue, 2018-11-27 at 15:34 -0800, Kenneth Graunke wrote:
> Vulkan and Gallium don't use Mesa's gl_program data structure, so
> they
> can't poke at 'prog'. But we can simply use the copy of the shader
> info
> stored wit
On Tue, 2018-12-04 at 18:10 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 02:33:25PM +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 08:16:34AM +0100, Iago Toral Quiroga wrote:
> > > Signed-off-by: Samuel Iglesias Gonsálvez
> > > --
On Tue, 2018-12-04 at 14:57 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:35AM +0100, Iago Toral Quiroga wrote:
> > From: Samuel Iglesias Gonsálvez
> >
> > It is not supported directly in the HW, we need to convert to a 32-
> > bit
> >
On Wed, 2018-12-05 at 11:08 +0200, Pohjolainen, Topi wrote:
> On Wed, Dec 05, 2018 at 09:49:29AM +0100, Iago Toral wrote:
> > On Tue, 2018-12-04 at 14:57 +0200, Pohjolainen, Topi wrote:
> > > On Tue, Dec 04, 2018 at 08:16:35AM +0100, Iago Toral Quiroga
> > > wrote:
&g
On Tue, 2018-12-04 at 18:16 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:36AM +0100, Iago Toral Quiroga wrote:
> > Since we handle booleans as integers this makes more sense.
>
> If this is applied before patch 10, can we merge 10 and 13?
We can't apply
On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> I remember people preferring to order things 16, 32, 64 before.
> Should
> we follow that here as well?
Yes, it makes sense. I'll change that.
> On Tue, Dec 04, 2018 at 08:16:46AM +0100, Iago Toral Quiroga wrote:
On Wed, 2018-12-05 at 13:20 +0200, Pohjolainen, Topi wrote:
> On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote:
> > On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> > > I remember people preferring to order things 16, 32, 64 before.
> > > Should
&
On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> > Source0 and Destination extract the floating-point precision
> > automatically
> > from the SrcType and DstType instruction fields respectiv
On Wed, 2018-12-05 at 11:33 -0600, Jason Ekstrand wrote:
> On Tue, Dec 4, 2018 at 1:17 AM Iago Toral Quiroga
> wrote:
> > ---
> >
> > src/compiler/spirv/vtn_glsl450.c | 36 +---
> >
> >
> > 1 file changed, 24 insertions(+
On Fri, 2018-12-07 at 15:06 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:58AM +0100, Iago Toral Quiroga wrote:
> > We use ALign16 mode for this, since it is more convenient, but the
> > PRM
> > for Broadwell states in Volume 3D Media GPGPU, Chapter
-0600, Jason Ekstrand wrote:
> Now I'm wondering even more about my previous question about just
> splitting it into two instructions in NIR.
>
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > From: Samuel Iglesias Gonsálvez
> >
> >
> >
Yeah, maybe. I'll do that.
On Fri, 2018-12-07 at 11:31 -0600, Jason Ekstrand wrote:
> I think it's probably less code to just make a separate 16-bit case.
>
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > ---
> >
> >
On Fri, 2018-12-07 at 11:57 -0600, Jason Ekstrand wrote:
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > From the Skylake PRM, Extended Math Function:
> >
> >
> >
> > "The execution size must be no more than 8 when half-floats
>
else.
On Fri, 2018-12-07 at 12:22 -0600, Jason Ekstrand wrote:
> Seems reasonable though I thought you had patches to the constant
> combining to fix this. Maybe they'll be ready in time that we won't
> need this?
>
>
> On Tue, Dec 4, 2018 at 1:18 AM Iago
On Fri, 2018-12-07 at 13:13 -0600, Jason Ekstrand wrote:
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > The implementation of these opcodes in the generator assumes that
> > their
> >
> > arguments are packed, and it generates regi
gt; conversion function that just does it all? Maybe some NIR lowering?
> In any case, I think we can do better than the pile of special cases
> we are starting to accumulate.
>
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > Section Register Region Restri
ogether,
> add one or two for the extension and the enables?
>
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > ---
> >
> > src/intel/vulkan/anv_device.c | 2 +-
> >
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >
On Fri, 2018-12-07 at 14:25 -0600, Jason Ekstrand wrote:
> On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga
> wrote:
> > There are no 8-bit immediates, so assert in that case.
> >
> > 16-bit immediates are replicated in each word of a 32-bit
> > immediate, so
>
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