I sent a message dated last Sunday to the dxp forum to a similar problem, but
nobody answered till now.
What I found out is, you can export and import design rules from a file,
but only a specific rule is imported, not the complete set. In the doc from Altium is
suggested,
if one want to import al
For this purpose, I use square pads with a gap of 0.2mm ( 8 mil )
This works fine. Don't forget to remove the solder mask between the
pads.
Georg
-Urspr ngliche Nachricht-
Von: Steve Smith [mailto:[EMAIL PROTECTED]]
Gesendet: Donnerstag, 5. September 2002 15:03
An: 'Protel EDA Forum'
Bet
where did you find export to DSN ?
i couldn't' find it
neither was a question about this answered on the DXP list
Dennis Saputelli
Georg Beckmann wrote:
>
> Hi Gisbert,
>
> you can export a *.dsn file. But till now, I didn't try it, because about
> other
> p
Hi Gisbert,
you can export a *.dsn file. But till now, I didn't try it, because about
other
problems.
Georg
-Urspr ngliche Nachricht-
Von: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Gesendet: Dienstag, 27. August 2002 14:56
An: Protel EDA Forum
Betreff: [PEDA] DXP and Specctra
Hell
Hi Peder,
after beta testing the DXP, I suggest to upgrade, if protel is the tool
you do your daily work.
Nevertheless you should know :
- DXP is a new system, you have to invest some time to learn new methodes.
- the global select and change is fully changed, also not fully understood,
Bob and all,
I can say the same, I bought a full version for about US$ 6000,- instead of
US$ 30.000,- two years ago, because I'm protel user, I got this as a 'cross
update'.
I just use specctra, the rest is still packed here and waits for somebody
who wants it.
The logic of this is very simple:
Hi Ivan,
just a practical advice,
why not write JUL-24-2002 or like we did for years 24-JUL-2002
or 2002-JUL-24 like we have to do it now here in Eurpoe.
The trick is, if you use 4 numbers for the year and letters for the month,
everybody can interpret it correctly. ( Opposite 07-01-02 )
BTW. Me
We use templates for any pcb. I just made separate pcb files with all border
and company header
for all different sizes on the mech-layer.
A5, A4, A3 Portait and landscape. Together with the lib I use this is in a
DDB called
library.DDB.
For a new project, I copy the file from there.
Georg
Hi Gary,
I want to use the simulator for a Monte carlo analyse for the following
question.
To simplify what I mean is, imagine a bridge circuit with four resistors of
1% tolerance.
The circuit is usable, if the bridge - voltage is below a certain limit. How
many
percent of my circuits are usable
EMAIL PROTECTED]]
Gesendet: Mittwoch, 26. Juni 2002 01:43
An: Protel EDA Forum
Betreff: Re: [PEDA] AW: PCB breakoffs
On 11:55 AM 25/06/2002 +0200, Georg Beckmann said:
>If the breakaway is a straight line over the whole board, I suggest a V -
>cut
>from both sides. V cuts can only be made o
-Urspr ngliche Nachricht-
Von: Brad Velander [mailto:[EMAIL PROTECTED]]
Gesendet: Freitag, 17. Mai 2002 18:08
An: 'Protel EDA Forum'
Betreff: Re: [PEDA] Too many hole sizes
Are there any IPC Certified designers who can confirm or deny the need for a
fab dwg?
What is the current
I do not understand, what a drill drawing is good for. I only use the drill
file and the
board shop read this to the drill machine.
Since I have a computer and CAD program, I'm happy
not to fill out a drill drawing sheet with any hole marked with a secret
label and wether I or
the man in the board
For to do this, I use dummy parts usually 0402 resistors for the routing.
You have different nets for current and sense, you can also give them
different rules.
After finishing the routing and checks, I short this parts in the schematic,
do an update pcb
and short this parts in the pcb manually.
The protel related advice is short. switch all routing layers except the
bottom layer off.
Make some parts for jumper wire. ( Not any size but a few ).
Add teardrops, use not less than pad - hole shoud be not less than 0.8mm.
Tracks should be not
smaller than 0.5mm. Holes should be very thight to
We buy a custom LCD's from a far east factory. For that we send them
a acad file with the signs and mechanical outline of the glass, and all
other parameter needed. Some factories have a checklist for the information
needed.
They all like to do the routing themselves, and it is included in the
to
Altium is now selling to different systems. Protel and Accel.
Does anybody work with both systems. ?
Which is better, or are they similar. ?
Whats the major difference ?
Georg
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave
Thanks for your help, I'm now able to do what I want.
I can export a spread with all parts, sort for values, that
the parts with (*) asterix are at the geginning. Than I give all
this parts the value 'NOTUSED' and update schematic and later pcb.
Now it's possible to manipulate all parts with th
-Original Message-
From: Georg Beckmann
Sent: Monday, January 28, 2002 10:41 PM
Hi,
Abdulrahman Lomax told me how to export data to spread.
When I export the data from a schematic project to spread, I'm not able to
sort the items.
I also tried to cut
gs... :)
Sincerely,
Juha Pajunen
-Original Message-
From: Georg Beckmann [mailto:[EMAIL PROTECTED]]
Sent: 28. tammikuuta 2002 16:51
To: [EMAIL PROTECTED]
Subject: AW: Converting gerbers to Protel99SE
Hi Juha,
can you send me a sample file that I can check it.
Or first check, if you use em
Hi,
Abdulrahman Lomax told me how to export data to spread.
When I export the data from a schematic project to spread, I'm not able to
sort the items.
I also tried to cut and paste to excel.
What I want to do is to change the value of optional parts. Optional parts
are marked with
a asterix be
-Urspr ngliche Nachricht-
Von: Gene Silvernail [mailto:[EMAIL PROTECTED]]
Gesendet: Donnerstag, 24. Januar 2002 23:07
An: Protel EDA Forum
Betreff: [PEDA] Specctra Autorouter
Any wise words on using Specctra autorouter 7.1 before I attempt it
I use the specctra router for digital layo
I strongly suggest to not use the option for more than one footprint in a
schematic part. I have one schematic part for each different footprint.
The parts can be named like 74HC00_SO, 74HC00_DIP and so on.
Georg
-Ursprungliche Nachricht-
Von: Wayne Trow [mailto:[EMAIL PROTECTED]]
Gesend
<..snip >
Thanks all of you, I got all the information I needed and saved
a lot of time.
With help of you, I found a source to get the original parts.
Georg
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
ch better to have the design files rather than just the
jedec.
Good Luck,
Jason.
-Original Message-
From: Georg Beckmann [mailto:[EMAIL PROTECTED]]
Sent: 17 January 2002 06:49
To: 'Protel EDA Forum'
Subject: [PEDA] Lattice pld
Sorry, if this is a bit off topic,
I have to pr
Sorry, if this is a bit off topic,
I have to program iSPLSI 1016 devices from lattice. The design was made
long
ago ( 1993 ) and I have a valid jed - file.
Lattice sells only the update of the iSPLSI 1016 called iSPLSI 1016E.
My programmer detects a wrong device and can't program it.
So I tri
: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Gesendet: Freitag, 11. Januar 2002 19:47
An: Protel EDA Forum
Betreff: Re: [PEDA] update sch from sread
At 04:14 PM 1/11/2002 +0100, Georg Beckmann wrote:
>I know that's somehow possible to update sch and pcb components from a bom
>or
Hi,
I know that's somehow possible to update sch and pcb components from a bom
or export the database to spread and edit it.
The hell I don't find any source or notice.
Georg
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave
some boards are party assembled and some places for components left free.
For this purpose the production wants a paste mask with closed pads for this
parts.
Has anybody an idea how this is done clever.
Georg
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mail
Ein Loch mit Senkung fur versenkte Schrauben
Georg
-Ursprungliche Nachricht-
Von: Edi Im Hof [mailto:[EMAIL PROTECTED]]
Gesendet: Donnerstag, 10. Januar 2002 08:40
An: Protel EDA Forum
Betreff: Re: [PEDA] Countersunk holes
At 17:17 09.01.02 -0500, you wrote:
>I would forsee no technica
I had to organize my sch-lib for the same fact. It is possible to add more
than one footprint to each schematic component, but I woudn't do that,
because
some parts have different numbering for different footprints. ( And perhaps
some pins more or less which have to be treated in different ways.
Tools, preferences Interactive routing to push obstacle.
That it.
Georg
-Urspr ngliche Nachricht-
Von: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Gesendet: Dienstag, 8. Januar 2002 08:23
An: Protel EDA Forum
Betreff: [PEDA] Push Ostacle for VIA
Hi,
my problem is. I have route many pa
;; '[EMAIL PROTECTED]'
Betreff: [PEDA] CAMTASTIC GERBER TO PROTEL TRANSLATOR?
Georg Beckmann mentioned having a little utility to convert the GERBER
output from CAMTASIC to PROTEL compatible Gerber for import to Protel.
Does anyone have this file they can make available to me? I woul
-Ursprungliche Nachricht-
Von: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Gesendet: Samstag, 1. Dezember 2001 21:00
An: Protel EDA Forum
Betreff: Re: [PEDA] Tasking Offer
warning: long, probably too long and rambling
<.. snip ..>
I think that altium try to learn how busines
This was discussed a lot of times here. The best way is, forget the 'hidden'
stuff, change all your parts with the power- pins displayed.
For multiple part components, delete all the hidden power pins on all parts,
draw visible power pins on the first item.
>From now on, you have total control on
-Ursprungliche Nachricht-
Von: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Gesendet: Dienstag, 27. November 2001 21:29
An: Protel EDA Forum
Betreff: Re: [PEDA] Layer Specific Keep out.
At 02:31 PM 11/27/01 -0400, Tim Fifield wrote:
>Is it possible to have a layer specific keep out?
>From this point, look how easy physics can be, if you are using the metric
system.
Georg
-Urspr ngliche Nachricht-
Von: Brooks,Bill [mailto:[EMAIL PROTECTED]]
Gesendet: Montag, 19. November 2001 21:58
An: 'Protel EDA Forum'
Betreff: Re: [PEDA] Copper Calculations
Hi Rene,
I believe t
I used the protel router for a lot of succsessful designs. Since about a
year
I have the specctra too.
This weeks I was on a 2 days seminar about specctra.
Here some general information about autorouter discussion.
- You cannot expect, that you push a button and get the ready done board you
thin
Some time ago, I had trouble with a fuse value of 1A. This was interpreted
as a
HEX NUMBER means 26 or so. The work around was to name the fuse 1.0AMP.
Try if it works with different net names.
Georg
-Urspr ngliche Nachricht-
Von: Thomas [mailto:[EMAIL PROTECTED]]
Gesendet: Freitag, 16.
-Ursprungliche Nachricht-
Von: Steve Baldwin [mailto:[EMAIL PROTECTED]]
Gesendet: Freitag, 2. November 2001 21:46
An: Protel EDA Forum
Betreff: Re: [PEDA] Altium changes.
> At 11:59 AM 11/2/01 +1200, Steve Baldwin wrote:
> >My understanding is that the dividend doesn't exist in the US.
Thanks for the advice, someone made me a simple program to convert the
gerber files generated by camtastic that protel can inport it.
The program adds the Dnn and cuts the first 3 lines of the gerber
that protel don't understand.
It is a simple DOS program you can start in a dos-box with the name
This is short for the German word Antwort, what means answer or response.
Georg
> -Urspr ngliche Nachricht-
> Von: Andrew W. Riley III [mailto:[EMAIL PROTECTED]]
> Gesendet: Freitag, 19. Oktober 2001 07:12
> An: Protel EDA Forum
> Betreff: [PEDA] OT: stupid question - "AW:" <--?
>
>
> He
I think there is no possibility in protel to do it.
In the .txt file is the information of all the holes
position and tool number.
The .drr file containes the tool information.
Tool number := diameter := plated or not.
In the *.drr file, you see, which is plated and which is not.
Since the *.txt
I had to do a similar job and found a way to increase productivity.
1. get gerber files of your old boards. If you have films of it, some
pcb - maker has a raster scanner to make it.
2. import the files, edit and make a netlist from the routed board.
3. Have or make a n
You can build an object class, give it a name and add the pads you want.
than you can set a design rule to this class.
Georg
> -Urspr ngliche Nachricht-
> Von: Waldemar Kulajew [mailto:[EMAIL PROTECTED]]
> Gesendet: Donnerstag, 20. September 2001 11:20
> An: ProtelForum
> Betreff: [PEDA]
Just place an item on the solder-mask layer. ( track, fill polygone. )
If you don't want a soldermask at all, advise the board maker to not use
it.
That it.
Georg
> -Urspr ngliche Nachricht-
> Von: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
> Gesendet: Dienstag, 18. September 2001
Hi Florian,
for what do you need teardrops. Do you design single - side boards of FR2
for consumer - products ?
I think there is no sense to do this for plated FR4 boards.
I would be glad to hear about other opinions about that.
Georg
> -Urspr ngliche Nachricht-
> Von: Florian Finst
The regulations differ a bit nationally and for what the
equipment might be. ( Industrie, office, medical, aircraft, military )
you have to check it.
A general clearance of 3 mm between L and N and PE for 230V and class I.
8 mm between L and secondary or metal ca
I had to import files from an old ( 89 ) EE-designer. For files with little
or no change you should
import the gerber data.
If you have to change many things it's less work to do it completly new and
have correct
schematic-sheets and netlists after this process.
For difficult footprints you can i
I read this thread for about two days and would like to tell you what I do
with the library stuff.
First, I only use my private library which contains only footprints and
parts
I used in a design.
Any footprint has a dedicated reference from a schematic part.
The schematic part has a reference to
Hi John,
why not scaling it to 50% and make a gerber of twice the size with
a gerber tool.
Or just leave it to the board maker to zoom it. ?
But I think the most logical way is to think it over and use a cable
construction, what Mr Lomax already said.
Georg
> -Ursprüngliche Nachricht-
Just select to make ? - marks of of all the component designators in
the annotation menue.
Then make a new annotation of all ? marked parts.
Don't forget to select all sheets of hierarchy.
Georg Beckmann
[EMAIL PROTECTED]
> -Ursprüngliche Nachricht-
> Von: Coleman, Tim [ma
and calculates the
other units wrong ( as a general rule ).
If you copy your footprint from somewhere, you'll learn, that there
are a lot of different possibilities to make a 3.5 mm PhoneJack
or even a D-sub connector which are correct, but do not fit your connector.
Georg Beckmann
> --
rica, they changed to the metric system.
The old version of the school-book : a lion can jump about 25 feet.
the new version : a lion can jump 7.625 m.
you see the advantage of metric system !
Georg Beckmann
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht-
> V
fill in between the pad you get connected with the pcb command 'connect
primitives from
pads '
Hope it helps
Georg Beckmann
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht-
> Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
> Auftrag von Mamdouh Wahab
> Gesendet: Samst
e GND and VCC to the top and bottom layer, there is more space
for routing.
Even more space I could get with the use of blind vias.
What does you mean is the better solution: six layer standard or 4 layer
with planes at top
and bottom and perhaps blind vias.
Georg Beckmann
[EMAIL PROT
I calculate ( pad-size - hole size )/2 = annular ring
perhaps kangaroos do it with new math. :-)
Georg
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht-
> Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
> Auftrag von Micky Blain
> Gesendet: Mittwoch, 14. Februar 2001 17:56
> An: Multiple r
Yes, I think it is the same as I had with the company - logo on the
schematic.
In the sheet ( or library part ) there is a link to the graphic file and not
the
graphic itself. Your collegue has probably not the same graphic in the same
path.
Georg
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht
This is exactly my opinion. Additional, schematics later printed on
paper and should be to understand. Often I've seen a netlabel on one
sheet and the wire ends somewhere. In one or more sheets you have to
search where it is also connected.
So, to understand such a schematic, you need the netlist
We, here in the south of germany, call this a
' muggeseckele'
what is real small.
I do not translate it.
Georg
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht-
> Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
> Auftrag von Darren Moore
> Gesendet: Freitag, 9. Februar 2001 06:07
> An: Multip
A real good idea,
That means, that you see a percentage of board space used every time
you place a new part in schematic.
Relatively easy would be a sum of all the part-space divides the total
board - space.
But does this help ?
Example: a 100 by 100 board can't have to parts 51 x 51, even only
> -Urspr ngliche Nachricht-
> Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
> Auftrag von Terry Harris
> Gesendet: Dienstag, 6. Februar 2001 19:58
> An: Multiple recipients of list proteledausers
> Betreff: Re: [PROTEL EDA USERS]: Suggestions for improving Protel...
>
>
> On Mon, 5 Feb
Thanks a lot Ian,
people who can read have an advantage to those who only looking at the
pictures.
Georg
[EMAIL PROTECTED]
>
>
> (I know someone responded with the recently but I can't find who.)
> In PCB type M-C (Move Component) and click on a blank part of the
> board. A dialog pops up th
The trick is, to do the save lib command before the update schematic,
otherwise the schematic are not updated with the changes made in the lib
part.
Georg
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht-
> Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
> Auftrag von Gene Silvernail
> Gesend
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