On Tue, 5 May 2015 11:00:01 +1000
David Gibson wrote:
> qemu currently implements the hypercalls H_LOGICAL_CI_LOAD and
> H_LOGICAL_CI_STORE as PAPR extensions. These are used by the SLOF firmware
> for IO, because performing cache inhibited MMIO accesses with the MMU off
> (real mode) is very a
On Fri, Apr 24, 2015 at 01:28:45PM -0700, Peter Crosthwaite wrote:
> Create a new header for Cadence GEM to allow using the device with
> modern SoC programming conventions. The state struct needs to be
> visible to embed the device in SoC containers.
>
> Reviewed-by: Alistair Francis
> Reviewed-
As it is more fully featured. It has multi-endian, thumb and AArch64
support whereas the existing monitor disas support only has vanilla
AA32 support.
E.G. Running an AA64 linux kernel the follow -d in_asm disas happens
(taget_disas()):
IN:
0x4000: 58c0 ldr x0, pc+24 (addr 0
Add the ARM specific disassembly flags setup, so ARM can be correctly
disassembled from the monitor.
Signed-off-by: Peter Crosthwaite
---
monitor.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/monitor.c b/monitor.c
index d831d98..9d9f1e2 100644
--- a/monitor.c
+++ b/monitor.c
In a normal disassembly flow, the printf and stream being used varies
from disas job to job. In particular it varies if mixing monitor_disas
and target_disas.
Make both the printfer function and target stream settable in the
QEMUDisassmbler class. Remove the stream_ initialisation from the
constru
Cris has the complication of variable length instructions and has
a check in place to clamp memory reads in case the disas request
doesn't have enough bytes for the instruction being disas'd. This
breaks down in the case where disassembling for the monitor where
the buffer length is defaulted to 0.
The monitor_ and target_ disas function do mostly the same thing.
One dissambles target instructions on behalf of the log, the other
for the monitor command "xp/i" and friends.
There is a #if defined TARGET_FOO switch duplicated between both
functions and arch-specific setup for disas is copied be
Migrate the target_disas TARGET_CRIS code to common code, so that
the disassambly works for the monitor (as well the log).
E.g.
(qemu) xp 0x40004000
40004000: 0x1e6f25f0
And before this patch:
(qemu) xp/i 0x40004000
0x40004000: Asm output not supported on this arch
After:
(qemu) xp/i 0x4
There two functions are mostly trying to do the same thing, which is
disassemble a target instruction (sequence) for printfing. The
architecture specific setup is largely duped between the two functions.
Most architectures are carbon copy and can be factored out without
issue (P1). Three architectu
Migrate the target_disas TARGET_MICROBLAZE code to common code, so
that the disassambly works for the monitor (as well the log).
E.g.
(qemu) xp 0x9000
9000: 0x94208001
And before this patch:
(qemu) xp/i 0x9000
0x9000: Asm output not supported on this arch
After:
(qemu) xp
On Mon, May 04, 2015 at 09:00:46PM -0700, Peter Crosthwaite wrote:
> On Mon, May 4, 2015 at 8:26 PM, Edgar E. Iglesias
> wrote:
> > On Fri, Apr 24, 2015 at 01:28:48PM -0700, Peter Crosthwaite wrote:
> >> Add a machine model for the Xilinx ZynqMP SoC EP108 board.
> >
> > hmm, I think xlnx-ep108 is
On Mon, May 4, 2015 at 8:26 PM, Edgar E. Iglesias
wrote:
> On Fri, Apr 24, 2015 at 01:28:48PM -0700, Peter Crosthwaite wrote:
>> Add a machine model for the Xilinx ZynqMP SoC EP108 board.
>
> hmm, I think xlnx-ep108 is quite cryptic as user input. Can't we just
> name this xilinx-ep108?
>
So I wa
On Fri, Apr 24, 2015 at 01:28:44PM -0700, Peter Crosthwaite wrote:
> Connect the GPIO outputs from the individual CPUs for the timers to the
> GIC.
>
> Tested-by: Alistair Francis
> Signed-off-by: Peter Crosthwaite
Reviewed-by: Edgar E. Iglesias
> ---
> changed since v4:
> Use macro for GIC_
On Fri, Apr 24, 2015 at 01:28:42PM -0700, Peter Crosthwaite wrote:
> With quad Cortex-A53 CPUs.
>
> Use SMC PSCI, with the standard policy of secondaries starting in
> power-off.
>
> Tested-by: Alistair Francis
> Reviewed-by: Alistair Francis
> Signed-off-by: Peter Crosthwaite
Reviewed-by: Ed
On Fri, Apr 24, 2015 at 01:28:42PM -0700, Peter Crosthwaite wrote:
> Add the GIC and connect IRQ outputs to the CPUs.
This will not work with device-trees that place the GICC maps at the
top of the 64K (due to the 64K address swizzling) which I expect to
be the default.
Maybe we can just model th
On Fri, Apr 24, 2015 at 12:17:29PM +0530, Bharata B Rao wrote:
> From: Andreas Färber
>
> Signed-off-by: Andreas Färber
> Signed-off-by: Bharata B Rao
So, how to organize this generically is still under discussion. For
now, I don't think this generic outline is really worth it. In any
case I
On Fri, Apr 24, 2015 at 01:28:48PM -0700, Peter Crosthwaite wrote:
> Add a machine model for the Xilinx ZynqMP SoC EP108 board.
hmm, I think xlnx-ep108 is quite cryptic as user input. Can't we just
name this xilinx-ep108?
Cheers,
Edgar
>
> Reviewed-by: Alistair Francis
> Reviewed-by: Peter M
On Fri, Apr 24, 2015 at 01:28:47PM -0700, Peter Crosthwaite wrote:
> Create a new header for Cadence UART to allow using the device with
> modern SoC programming conventions. The state struct needs to be
> visible to embed the device in SoC containers.
>
> Reviewed-by: Alistair Francis
> Reviewed
On Fri, Apr 24, 2015 at 01:28:46PM -0700, Peter Crosthwaite wrote:
> Clean up some variable names in preparation for migrating the state struct
> and type cast macro to a public header. The acronym "UART" on it's own is
> not specific enough to be used in a more global namespace so preface with
> "
On Fri, Apr 24, 2015 at 01:28:44PM -0700, Peter Crosthwaite wrote:
> Cleanup some variable names in preparation for migrating the state
> struct and type cast macro to a public header. The acronym "GEM" on
> its own is not specific enough to be used in a more global namespace
> so preface with "cad
On Fri, Apr 24, 2015 at 01:28:41PM -0700, Peter Crosthwaite wrote:
> Add the ARM cortex A53 processor definition. Similar to A57, but with
> different L1 I cache policy, phys addr size and different cache
> geometries. The cache sizes is implementation configurable, but use
> these values (from Xil
On Fri, Apr 24, 2015 at 01:28:41PM -0700, Peter Crosthwaite wrote:
> Rename some A57 CP register variables in preparation for support for
> Cortex A53. Use "a57_a53" to describe the shareable features. Some of
> the CP15 registers (such as ACTLR) are specific to implementation, but
> we currently j
For zero write, qiov passed by callers (qemu-io "write -z" and scsi-disk
"write same") is NULL.
Commit fc3959e466 fixed bdrv_co_write_zeroes which is the common case
for this bug, but it still exists in bdrv_aio_write_zeroes. A simpler
fix would be in bdrv_co_do_pwritev which is the NULL dereferen
Test zero write in byte range 512~1024 for 4k alignment.
Signed-off-by: Fam Zheng
---
tests/qemu-iotests/033 | 13 +
tests/qemu-iotests/033.out | 30 ++
2 files changed, 43 insertions(+)
diff --git a/tests/qemu-iotests/033 b/tests/qemu-iotests/033
ind
An unaligned zero write causes NULL deferencing in bdrv_co_do_pwritev. That
path is reachable from bdrv_co_write_zeroes and bdrv_aio_write_zeroes.
You can easily trigger through the former with qemu-io, as the test case added
by 61815d6e0aa. For bdrv_aio_write_zeroes, in common cases there's alway
This reverts commit fc3959e4669a1c2149b91ccb05101cfc7ae1fc05.
The core write code already handles the case, so remove this
duplication.
Because commit 61007b316 moved the touched code from block.c to
block/io.c, the change is manually reverted.
Signed-off-by: Fam Zheng
---
block/io.c | 45
On Mon, May 04, 2015 at 11:41:54PM +0200, Igor Mammedov wrote:
> It's not really split implementation, it's installing an additional
> table which is purely SeaBIOS specific since QEMU doesn't care about
> PPID data at all nor does it need to do so.
If both SeaBIOS and QEMU provide acpi tables, it
On 2015/4/15 21:25, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Signed-off-by: Shannon Zhao
> Signed-off-by: Shannon Zhao
> Reviewed-by: Alex Bennée
> ---
> hw/acpi/aml-build.c | 9 +
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/h
On Thu, 04/30 15:34, Kevin Wolf wrote:
> Am 27.04.2015 um 15:18 hat Fam Zheng geschrieben:
> > An unaligned zero write causes NULL deferencing in bdrv_co_do_pwritev. That
> > path is reachable from bdrv_co_write_zeroes and bdrv_aio_write_zeroes.
> >
> > You can easily trigger through the former wi
> -Original Message-
> From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
> Sent: Monday, May 04, 2015 11:36 PM
> To: Xu, Quan; stefano.stabell...@eu.citrix.com; ebl...@redhat.com
> Cc: qemu-devel@nongnu.org; wei.l...@citrix.com; dgde...@tycho.nsa.gov;
> xen-de...@lists.xen.org
> Sub
> -Original Message-
> From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
> Sent: Monday, May 04, 2015 11:30 PM
> To: Xu, Quan; stefano.stabell...@eu.citrix.com; ebl...@redhat.com
> Cc: qemu-devel@nongnu.org; wei.l...@citrix.com; dgde...@tycho.nsa.gov;
> xen-de...@lists.xen.org
> Sub
> -Original Message-
> From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
> Sent: Monday, May 04, 2015 11:26 PM
> To: Xu, Quan; stefano.stabell...@eu.citrix.com; ebl...@redhat.com
> Cc: qemu-devel@nongnu.org; wei.l...@citrix.com; dgde...@tycho.nsa.gov;
> xen-de...@lists.xen.org
> Sub
On Fri, May 01, 2015 at 06:50:26PM +0100, Peter Maydell wrote:
> This patch series adds support for GICv1 and GICv2 security
> extensions, as well as support for GIC interrupt grouping on GICv2.
A question. Once we enable the the security extensions on the GICs,
do you have any suggestions on howt
On Fri, May 01, 2015 at 06:50:42PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> Connect FIQ output of the GIC CPU interfaces to the CPUs.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
> Message-id: 1429113742-8371-3-git-send-email-greg.bell...@linaro.org
> [PMM: min
On Fri, May 01, 2015 at 06:50:40PM +0100, Peter Maydell wrote:
> Add support to gic_update() for determining the current IRQ
> and FIQ status when interrupt grouping is supported. This
> simply requires that instead of always raising IRQ we
> check the group of the highest priority pending interrup
On Fri, May 01, 2015 at 06:50:41PM +0100, Peter Maydell wrote:
> From: Greg Bellows
>
> Connect FIQ output of the GIC CPU interfaces to the CPUs.
>
> Signed-off-by: Greg Bellows
> Message-id: 1429113742-8371-4-git-send-email-greg.bell...@linaro.org
> [PMM: minor format tweak]
> Signed-off-by: P
On Fri, May 01, 2015 at 06:50:39PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> Grouping (GICv2) and Security Extensions change the behavior of IAR
> reads. Acknowledging Group0 interrupts is only allowed from Secure
> state and acknowledging Group1 interrupts from Secure state is only
On Fri, May 01, 2015 at 06:50:38PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> Grouping (GICv2) and Security Extensions change the behavior of EOIR
> writes. Completing Group0 interrupts is only allowed from Secure state.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellow
Signed-off-by: zhanghailiang
---
block/sheepdog.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index 2d5f06a..bd7cbed 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -2341,6 +2341,7 @@ static int sd_snapshot_create(BlockDriverState *bs,
QEMUSnap
On Fri, May 01, 2015 at 06:50:37PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> Grouping (GICv2) and Security Extensions change the behaviour of reads
> of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bel
On Fri, May 01, 2015 at 06:50:35PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> For GICs with Security Extensions Non-secure reads have a restricted
> view on the current running priority.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
> Message-id: 1429113742-8371-1
On Fri, May 01, 2015 at 06:50:36PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> GICs with Security Extensions restrict the non-secure view of the
> interrupt priority and priority mask registers.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
> Message-id: 1429113742
qemu currently implements the hypercalls H_LOGICAL_CI_LOAD and
H_LOGICAL_CI_STORE as PAPR extensions. These are used by the SLOF firmware
for IO, because performing cache inhibited MMIO accesses with the MMU off
(real mode) is very awkward on POWER.
This approach breaks when SLOF needs to access
On Fri, May 01, 2015 at 06:50:34PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> ICCICR/GICC_CTLR is banked in GICv1 implementations with Security
> Extensions or in GICv2 in independent from Security Extensions.
> This makes it possible to enable forwarding of interrupts from
> the CPU
On Fri, May 01, 2015 at 06:50:33PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> This register is banked in GICs with Security Extensions. Storing the
> non-secure copy of BPR in the abpr, which is an alias to the non-secure
> copy for secure access. ABPR itself is only accessible from s
On Fri, May 01, 2015 at 06:50:32PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> ICDDCR/GICD_CTLR is banked if the GIC has the security extensions,
> and the S (or only) copy has separate enable bits for Group0 and
> Group1 enable if the GIC implements interrupt groups.
>
> EnableGroup0
On Fri, May 01, 2015 at 06:50:30PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> The Interrupt Group Registers allow the guest to configure interrupts
> into one of two groups, where Group0 are higher priority and may
> be routed to IRQ or FIQ, and Group1 are lower priority and always
>
On Fri, May 01, 2015 at 06:50:29PM +0100, Peter Maydell wrote:
> Switch the GIC's MMIO callback functions to the read_with_attrs
> and write_with_attrs functions which provide MemTxAttrs. This will
> allow the GIC to correctly handle secure and nonsecure register
> accesses.
>
> Signed-off-by: Pet
On 2015/5/4 23:28, Cornelia Huck wrote:
> Let's move operations that are only valid after the backend has been
> realized to a ->device_plugged callback, just as virtio-pci does.
> Also reorder setting up the host feature bits to the sequence used
> by virtio-pci.
>
> While we're at it, also add
On 2015/5/4 23:28, Cornelia Huck wrote:
> We used to avoid enabling event_idx for virtio-blk devices via
> s390-virtio, but we now have a workaround in place for guests trying
> to use the device before setting DRIVER_OK. Therefore, let's add
> DEFINE_VIRTIO_COMMON_FEATURES to the base device so a
On Fri, May 01, 2015 at 06:50:28PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> Add a QOM property which allows the GIC Security Extensions to be
> enabled. These are an optional part of the GICv1 and GICv2 architecture.
> This commit just adds the property and some sanity checks that i
On Fri, May 01, 2015 at 06:50:27PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler
>
> Create the outbound FIQ lines from the GIC to the CPUs; these are
> used if the GIC has security extensions or grouping support.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
> Message-i
Hi Kevin,
I understand. In this case (where the gluster process was killed or
crashed) I guess the best option would be to poweroff and restart the
VM, which can be done client-side (ovirt + libvirt)
Please mark as "Won't fix".
Thanks.
--
You received this bug notification because you are a me
On Mon, 04 May 2015 14:39:32 -0400
Stefan Berger wrote:
> On 05/04/2015 12:16 PM, Kevin O'Connor wrote:
> > On Mon, May 04, 2015 at 11:22:25AM -0400, Stefan Berger wrote:
> >> On 05/04/2015 05:16 AM, Igor Mammedov wrote:
> >>> On Wed, 29 Apr 2015 12:42:21 -0400
> 2 choices now -- which one t
On Fri, Apr 17, 2015 at 03:22:37PM +0100, Daniel P. Berrange wrote:
> This integrates support for QIOChannelTLS object in the TCP
> chardev backend. If the 'tls-cred=NAME' option is passed with
> the '-chardev tcp' argument, then it will setup the chardev
> such that the client is required to estab
On 05/04/2015 01:15 PM, Max Reitz wrote:
> Expose the two new options for controlling the memory usage of the
> overlap check implementation via QAPI.
>
> Signed-off-by: Max Reitz
> ---
> qapi/block-core.json | 37 +
> 1 file changed, 37 insertions(+)
>
> dif
On 05/04/2015 01:15 PM, Max Reitz wrote:
> Later, a mechanism to set a limit on how much memory may be used for the
> overlap prevention structures will be introduced. If that limit is about
> to be exceeded, a QMP event should be emitted. This very event is
> specified by this patch.
>
> Signed-o
On 05/04/2015 01:09 PM, Eduardo Habkost wrote:
> This will allow clients to query additional information directly using
> qom-get on the CPU objects.
>
> Signed-off-by: Eduardo Habkost
> ---
> Reference to previous discussion:
>
> Date: Mon, 4 May 2015 15:37:40 -0300
> From: Eduardo Habkost
This patch adds some test cases for the memory limit concerning the
in-memory structures used to detect and prevent accidental metadata
overlaps.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/060 | 222 +
tests/qemu-iotests/060.out | 47
Ping
(I should've CC'd Luiz to begin with ...)
Eric's given this series the once over and Kashyap has tested it, so it
should in theory be good to go.
On 04/29/2015 03:14 PM, John Snow wrote:
The qmp-shell is a little rudimentary, but it can be hacked
to give us some transactional support wit
Keep track of the inactive L2 tables in the metadata list to protect
them against accidental modifications.
Signed-off-by: Max Reitz
---
block/qcow2-refcount.c | 20
block/qcow2-snapshot.c | 43 ---
2 files changed, 60 insertions(+), 3
Add runtime options to qcow2 to control the size of the structures used
for metadata overlap prevention (one option to control the size of the
bitmap cache, another one to control the total memory size limit).
Signed-off-by: Max Reitz
---
block/qcow2.c | 35 +--
b
This adds an adjustable limit for the total memory usage of the overlap
prevention structures.
Signed-off-by: Max Reitz
---
block/qcow2-overlap.c | 145 +++---
block/qcow2.c | 2 +-
block/qcow2.h | 2 +-
3 files changed, 139 inserti
Keep track of the snapshot table in the metadata list to protect it
against accidental modifications.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2-snapshot.c | 10 ++
block/qcow2.c | 6 ++
2 files changed, 16 insertions(+)
diff --git a/block/qcow2-snap
Make the static new overlap check function global and drop the old
function.
Signed-off-by: Max Reitz
---
block/qcow2-overlap.c | 8 +---
block/qcow2-refcount.c | 120 -
2 files changed, 2 insertions(+), 126 deletions(-)
diff --git a/block/qcow
Keep track of the refcount blocks in the metadata list to protect them
against accidental modifications.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2-refcount.c | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/block/q
Keep track of the active L2 tables in the metadata list to protect them
against accidental modifications.
Signed-off-by: Max Reitz
---
block/qcow2-cluster.c | 2 ++
block/qcow2-refcount.c | 6 ++
block/qcow2-snapshot.c | 21 +
block/qcow2.c | 8 +++-
4 fi
Later, a mechanism to set a limit on how much memory may be used for the
overlap prevention structures will be introduced. If that limit is about
to be exceeded, a QMP event should be emitted. This very event is
specified by this patch.
Signed-off-by: Max Reitz
---
docs/qmp/qmp-events.txt | 28 +
Enter the image header into the metadata list to protect it against
accidental modifications.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/block/qcow2.c b/block/qcow2.c
index b15a612..fc53b34 100644
--- a/block/qcow2.c
Keep track of the inactive L1 tables in the metadata list to protect
them against accidental modifications.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2-snapshot.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/block/qcow2-snapshot.c b/block/q
Keep track of the refcount table in the metadata list to protect it
against accidental modifications.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2-refcount.c | 18 ++
block/qcow2.c | 4
2 files changed, 22 insertions(+)
diff --git a/block/qcow
Expose the two new options for controlling the memory usage of the
overlap check implementation via QAPI.
Signed-off-by: Max Reitz
---
qapi/block-core.json | 37 +
1 file changed, 37 insertions(+)
diff --git a/qapi/block-core.json b/qapi/block-core.json
index
Pull up the absorption of the qcow2-relevant command line options and
the evaluation of the overlap check options in qcow2_open().
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2.c | 96 +--
1 file changed, 48 insertions(+
Create and destroy the metadata list on creation and destruction of a
qcow2 BDS, respectively. Skip creation if no overlap checks should be
performed.
Signed-off-by: Max Reitz
---
block/qcow2.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/block/qcow2.c b/block/qcow2.c
index c
The existing qcow2 metadata overlap detection function used existing
structures to determine the location of the image metadata, from plain
fields such as l1_table_offset and l1_size in the BDRVQcowState, over
image structures in memory such as the L1 table for the L2 tables'
positions, or it even
Keep track of the active L1 table in the metadata list to protect it
against accidental modifications.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/qcow2-cluster.c | 11 +++
block/qcow2-snapshot.c | 10 ++
block/qcow2.c | 4
3 files changed, 25 inse
This is a continuation of previous versions of this series. v2's cover
letter was the most elaborate, which you can find here (includes
benchmarks):
http://lists.nongnu.org/archive/html/qemu-devel/2014-11/msg03430.html
See patch 1 for an explanation of why this series exists and what it
does. Patc
This will allow clients to query additional information directly using
qom-get on the CPU objects.
Signed-off-by: Eduardo Habkost
---
Reference to previous discussion:
Date: Mon, 4 May 2015 15:37:40 -0300
From: Eduardo Habkost
Message-ID: <20150504183740.gm17...@thinpad.lan.raisama.net>
On 05/04/2015 12:16 PM, Kevin O'Connor wrote:
On Mon, May 04, 2015 at 11:22:25AM -0400, Stefan Berger wrote:
On 05/04/2015 05:16 AM, Igor Mammedov wrote:
On Wed, 29 Apr 2015 12:42:21 -0400
2 choices now -- which one to take?
I'd try installing extra SSDT table first as a cleanest way (seabios
On Mon, May 04, 2015 at 05:53:59PM +0200, Paolo Bonzini wrote:
>
>
> On 04/05/2015 16:05, Eduardo Habkost wrote:
> > On Mon, May 04, 2015 at 03:19:32PM +0200, Paolo Bonzini wrote:
> >>
> >>
> >> On 04/05/2015 15:16, Igor Mammedov wrote:
> > Can we use the APIC id then? Perhaps wrapped with a
Hello Alexandre,
Thank you for your response. I came upon that patch on the Libvirt mailing
list, too. However, the following comment makes me think that it's not likely
to be merged:
https://www.redhat.com/archives/libvir-list/2015-February/msg00415.html
Also, later in the thread, the author
Eric Blake writes:
> We want to eventually allow qapi defaults, by making:
> 'data':{'*flag':'bool'}
> as shorthand for something like:
> 'data':{'flag':{'type':'bool', 'optional':true}}
> so that the default can be specified:
>'data':{'flag':{'type':'bool', 'optional':true, 'default':t
Eric Blake writes:
> Our type inheritance for both 'struct' and for flat 'union' merges
> key/value pairs from the base class with those from the type in
> question. Although the C code currently boxes things so that there
> is a distinction between which member is referred to, the QMP wire
> fo
Eric Blake writes:
> The handling of \ inside QAPI strings was less than ideal, and
> really only worked JSON's \/, \\, \", and our extension of \'
> (an obvious extension, when you realize we use '' instead of ""
> for strings). For other things, like '\n', it resulted in a
> literal 'n' instea
Eric Blake writes:
> Now that we no longer have nested structs to visit, the use of
> prefix strings is no longer required. Remove the code that is
> no longer reachable.
>
> Signed-off-by: Eric Blake
Reviewed-by: Markus Armbruster
On 05/04/2015 08:07 AM, Kevin Wolf wrote:
Am 30.04.2015 um 20:07 hat John Snow geschrieben:
libqos.c:
-set_context for addressing which commands go where
-migrate performs the actual migration
malloc.c:
- Structure of the allocator is adjusted slightly with
a second-tier
Hi,
they are a lot of patches sent on the mailing list recently,
cpu hotplug|unplug with device_add|del
https://www.redhat.com/archives/libvir-list/2015-February/msg00084.html
- Mail original -
De: "Fahri Cihan Demirci"
À: "qemu-devel"
Envoyé: Lundi 4 Mai 2015 18:24:43
Objet: [Qemu-
Eric Blake writes:
> Referring to "type" as both a meta-type (built-in, enum, union,
> alternate, or struct) and a specific type (the name that the
> schema uses for declaring structs) is confusing. The confusion
> is only made worse by the fact that the generator mostly already
> refers to stru
Eric Blake writes:
> Previous commits demonstrated that the generator overlooked various
> bad naming situations:
> - types, commands, and events need a valid name
> - enum members must be valid names, when combined with prefix
> - union and alternate branches cannot be marked optional
>
> Valid
Eric Blake writes:
> For a few QMP commands, we are forced to pass an arbitrary type
> without tracking it properly in QAPI. Among the existing clients,
> this unnamed type was spelled 'dict', 'visitor', and '**'; this
> patch standardizes on '**', matching the documentation changes
> earlier in
Hello,
We are interested in being able to remove a VCPU from an active Libvirt domain
running under QEMU/KVM. However, currently that does not seem to be possible
because QEMU does not provide an interface for hot-unplugging a VCPU. The
corresponding feature page [1] on the QEMU wiki mentions t
On Mon, May 04, 2015 at 11:22:25AM -0400, Stefan Berger wrote:
> On 05/04/2015 05:16 AM, Igor Mammedov wrote:
> >On Wed, 29 Apr 2015 12:42:21 -0400
> >>2 choices now -- which one to take?
> >I'd try installing extra SSDT table first as a cleanest way (seabios only)
> >and if it fails fallback to TI
On Fri, 24 Apr 2015 12:17:28 +0530
Bharata B Rao wrote:
> Factor out bits of sPAPR specific CPU initialization code into
> a separate routine so that it can be called from CPU hotplug
> path too.
>
> Signed-off-by: Bharata B Rao
> Reviewed-by: David Gibson
> ---
> hw/ppc/spapr.c | 54
Let's move operations that are only valid after the backend has been
realized to a ->device_plugged callback, just as virtio-pci does.
Also reorder setting up the host feature bits to the sequence used
by virtio-pci.
While we're at it, also add a ->device_unplugged callback to stop
ioeventfd, just
virtio-ccw has an odd sequence of realizing devices: first the
device-specific relization (net, block, ...), then the generic
realization. It feels less odd to have the generic realization
callback trigger the device-specific realization instead (and this
also matches what virtio-pci does).
One th
Hi,
here are some virtio-related s390x patches. I'd like to submit them
before sending any further s390x patches, simply to get them out of
the way and to allow the various virtio-related patchsets to proceed
without generating needless conflicts in s390x code.
After applying these patches, both
From: Christian Borntraeger
Feature updates are not a synchronuous operation for the legacy
s390-virtio transport. This transport syncs the guest feature bits
(those from finalize) on the set_status hypercall. Before that qemu
thinks that features are zero, which means QEMU will misbehave, e.g.
i
On 05/04/2015 05:16 AM, Igor Mammedov wrote:
On Wed, 29 Apr 2015 12:42:21 -0400
2 choices now -- which one to take?
I'd try installing extra SSDT table first as a cleanest way (seabios only)
and if it fails fallback to TIS path.
I did some experiment where I tried to use AML's Store() call
Demonstrate that the qapi generator silently parses confusing
types, which may cause other errors later on. Later patches
will update the expected results as the generator is made stricter.
Most of the new tests focus on blatant errors. But
returns-whitelist is a case where we have historically a
We used to avoid enabling event_idx for virtio-blk devices via
s390-virtio, but we now have a workaround in place for guests trying
to use the device before setting DRIVER_OK. Therefore, let's add
DEFINE_VIRTIO_COMMON_FEATURES to the base device so all devices get
those common features - and make s
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