On Mon 24 Aug 2015 08:54:56 PM CEST, Max Reitz wrote:
[bdrv_fill_options()]
> User-specified options should always have precedence over any other
> option. The thing is, we consider the filename to be specified by the
> user.
For user-specified options like the "lazy-refcounts" case that I
ment
On 2015/8/24 22:38, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
This is the 8th version of COLO.
I'm seeing an occasional error:
pcibus_reset: Assertion `bus->irq_count[i] == 0' failed.
on the secondary; have you seen that?
bus->irq_count[4] is -
On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
wrote:
> Hi,
>
>
> On 25.08.2015 04:19, David Kiarie wrote:
>>
>> From: David
>>
>> Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
>> emulation that only does translation and some basic Event logging.
>> Guest translation enable
Public bug reported:
2.3.0 (manjaro distro package) works fine. 2.4.0 (manjaro or the arch
vanilla one) hangs on the SeaBIOS screen when saying "Press F12 for boot
menu". All tested with the same hardware, OS, command and configuration.
It also starts without the GPU passed through, even with the
On Tue, Aug 25, 2015 at 10:31 AM, Valentine Sinitsyn
wrote:
>
>
> On 25.08.2015 12:25, David kiarie wrote:
>>
>> On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
>> wrote:
>>>
>>> Hi,
>>>
>>>
>>> On 25.08.2015 04:19, David Kiarie wrote:
From: David
Add AMD IOMMU emula
Programmingkid writes:
> On Aug 24, 2015, at 12:38 PM, Markus Armbruster wrote:
>
>> Programmingkid writes:
>>
>>> On Aug 24, 2015, at 5:45 AM, Markus Armbruster wrote:
>>>
Copying the USB maintainer.
Programmingkid writes:
> On Aug 8, 2015, at 8:48 AM, Programmingki
On Mon, Aug 24, 2015 at 4:36 PM, Alistair Francis
wrote:
> On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
> wrote:
>> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber wrote:
>>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
wrot
Also, am not sure what HATS, GATS and sizes of virtual addresses(for
both guest and host) I should be using.
On Tue, Aug 25, 2015 at 10:41 AM, David kiarie wrote:
> On Tue, Aug 25, 2015 at 10:31 AM, Valentine Sinitsyn
> wrote:
>>
>>
>> On 25.08.2015 12:25, David kiarie wrote:
>>>
>>> On Tue, Aug
Am 25.08.2015 um 08:44 schrieb Artyom Tarasenko:
>your patch gives the worst result in stream benchmark but nearly the best in
>pugixml compile times and prime.c runtime
>every tried patch or branch nearly halfs the speed of the stream benchmark
>comapred to qemu-git-master
This is very surprisi
Eric Blake writes:
> On 08/24/2015 11:07 AM, Markus Armbruster wrote:
>
>>> You can prevent GTK+ from calling setlocale() by using
>>> gtk_disable_setlocale() before gtk_init(), but note that setlocale() is
>>> needed for gettext.
>>
>> We can
>>
>> (A) Internationalize our complete code base
>
On Tue 25 Aug 2015 09:54:42 AM CEST, Markus Armbruster wrote:
> Switching back to C locale whenever some unwanted locale-dependency
> breaks the code is problematic, because it involves finding all the
> places that break, iteratively (euphemism for "we debug one breakage
> after the other, adding
Hi Christian:
Test case 068(qemu/tests/qemu-iotests/068, which is for loading a saved
VM state from a qcow2 image)
was broken because s390-virtio-ccw uses the new bootloader of
s390-ccw.img, instead of s390-zipl.rom.
1. qemu-img create -f qcow2 scratch/t.qcow2 64M
2. [root@r17lp42 qemu-iotest
Eric Blake writes:
> On 08/24/2015 10:55 AM, Markus Armbruster wrote:
>
>> Our motivation for dropping nested structs was to avoid burning the
>> 'name': {} struct member syntax on a trivial and rarely used
>> convenience, and instead make it available for a way to specify member
>> attributes be
On 08/21/2015 12:54 AM, Eduardo Habkost wrote:
Now all TYPE_MACHINE subclasses use MACHINE_TYPE_NAME to generate the
class name. So instead of requiring each subclass to set
MachineClass::name manually, we can now set it automatically at the
TYPE_MACHINE class_base_init() function.
Signed-off-by
On 08/24/2015 12:54 PM, Markus Armbruster wrote:
John Snow writes:
On 08/19/2015 02:55 AM, Dr. David Alan Gilbert wrote:
* Eduardo Habkost (ehabk...@redhat.com) wrote:
Migration with q35 was not possible before commit
04329029a8c539eb5f75dcb6d8b016f0c53a031a, because q35 unconditionally crea
On 08/21/2015 12:54 AM, Eduardo Habkost wrote:
The macro will be useful to ensure the machine class names follow the
right format to make machine class lookup by class name work correctly.
Signed-off-by: Eduardo Habkost
---
include/hw/boards.h | 6 ++
vl.c| 2 +-
2 files
On 08/21/2015 12:54 AM, Eduardo Habkost wrote:
Now that all non-abstract TYPE_MACHINE subclasses have the -machine
suffix, add an assert to ensure this will be always true.
Signed-off-by: Eduardo Habkost
---
hw/core/machine.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/co
On 08/07/2015 10:15 PM, Eduardo Habkost wrote:
The existing i440fx initialization code sets a PCI config register that
isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is
DRAMC (DRAM Control) and has nothing to do with the RAM size.
This was implemented in commit ec5f92ce6ac
On 08/17/2015 09:42 PM, Eduardo Habkost wrote:
Remove arguments that can be found in PCMachineState.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Change prototype on xen-hvm-stub.c too
---
hw/i386/pc_piix.c| 4 +---
hw/i386/pc_q35.c | 4 +---
include/hw/xen/xen.h | 4 ++
On Wed, Aug 19, 2015 at 09:30:20AM -0700, Eduardo Habkost wrote:
> On Wed, Aug 19, 2015 at 10:55:26AM +0100, Dr. David Alan Gilbert wrote:
> > * Eduardo Habkost (ehabk...@redhat.com) wrote:
> > > Migration with q35 was not possible before commit
> > > 04329029a8c539eb5f75dcb6d8b016f0c53a031a, becau
On 25 August 2015 at 10:29, françois Guerret
wrote:
> I want to execute a realtime software which executes periodically the same
> loop.
> On multicore target, I set one periodic loop per core.
>
> I need the time to be synchronized between the cores at least with the
> granularity of a loop perio
Hello,
Thanks for your concern.
I want to execute a realtime software which executes periodically the same
loop.On multicore target, I set one periodic loop per core.
I need the time to be synchronized between the cores at least with the
granularity of a loop period.For instance I want to prevent
On 08/12/2015 02:50 PM, Denis V. Lunev wrote:
The monivation of this set is simple. Recently we have proposed patch
to monitor.c with specific x86 APIC HMP commands. The patchset was denied
with the main motivation "No more arch specific code in monitor.c"
This patchset is the first step to move
On Fri, Aug 21, 2015 at 05:05:49PM +0800, Jason Wang wrote:
> We used to use mmio for notification. This could be slow on some arch
> (e.g on x86 without EPT). So this patch introduces pio bar and a pio
> notification cap for modern device. This ability is enabled through
> property "modern-pio-not
There are some flaws in qemu_put_compression_data so that it can't not operate
on an normal QEMUFile, improve it so as to use it later.
Signed-off-by: Liang Li
---
migration/qemu-file.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/migration/qemu-file.c b/migratio
When the compression thread count is set to 1, the current implementation
is inefficient because of the following reason:
1. Thread synchronization cost;
2. Data copy;
3. No benefit from the separate compression thread;
This patch optimizes the performance for the case of 1 compress thread.
In thi
When the (de)compression thread count is set to 1, the current implementation
is inefficient because of the data copy and thread syncronization cost, a
separate
single (de)compression thread is useless for performance improvement and will
result in performance degradation.
If (de)compression thre
When decompression thread count is set to 1, the current implementation
is inefficient because of the following reason:
1. Thread syncronization cost;
2. Data copy;
This patch optimizes the performance for the case of 1 decompress thread.
In this case, the compression is done in process_incoming_m
Implement property instead of direct assignment of cpu->env.irqchip
Signed-off-by: Pavel Fedin
---
hw/arm/armv7m.c | 5 ++---
target-arm/cpu.c | 6 ++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 19742b7..8905e97 100644
--- a/hw/arm/
This name seems to be more appropriate because ARMv8 also needs a link
with GICv3 for CPU interface to work
Signed-off-by: Pavel Fedin
---
hw/arm/armv7m.c | 2 +-
target-arm/cpu.h| 5 -
target-arm/helper.c | 12 ++--
3 files changed, 11 insertions(+), 8 deletions(-)
diff -
ARMv7m CPU needs a link to NVIC instance for processing interrupts.
Similarly ARMv8 needs a link to GICv3 for its CPU interface.
This series builds upon existing mechanism for linking irqchip and
CPU, bringing the code up to date and making it reusable. Another small
step towards complete GICv3 im
You're proposing to revise a qdev design decision, namely the purpose of
IDs. This has been discussed before, and IDs remained unchanged.
Perhaps it's time to revisit this issue. Cc'ing a few more people.
Relevant prior threads:
* [PATCH] qdev: Reject duplicate and anti-social device IDs
http:
My other reply is about design issues. This one is about the actual
code. Until we get rough consensus on the former, the latter doesn't
really matter, but here goes anyway.
Eric Blake writes:
> On 08/24/2015 12:53 PM, Programmingkid wrote:
>> Add device ID generation to each device if an ID i
Alberto Garcia writes:
> On Tue 25 Aug 2015 09:54:42 AM CEST, Markus Armbruster wrote:
>
>> Switching back to C locale whenever some unwanted locale-dependency
>> breaks the code is problematic, because it involves finding all the
>> places that break, iteratively (euphemism for "we debug one bre
On 8/25/15 12:15, Richard Henderson wrote:
> On 08/24/2015 09:17 AM, Richard Henderson wrote:
>> Signed-off-by: Richard Henderson
>> ---
>> target-tilegx/translate.c | 50
>> ++-
>> 1 file changed, 49 insertions(+), 1 deletion(-)
>>
>> diff --git a/targe
> From: xili_gchen_5...@hotmail.com
> To: r...@twiddle.net; qemu-devel@nongnu.org
> CC: w...@tilera.com; cmetc...@ezchip.com; peter.mayd...@linaro.org
> Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic
> instructions
> Date: Tue, 2
On 19/08/15 17:58, Eduardo Habkost wrote:
> On Wed, Jul 22, 2015 at 03:59:50PM +0200, Thomas Huth wrote:
>> The code in smp_parse already checks the topology information for
>> sockets * cores * threads < cpus and bails out with an error in
>> that case. However, it is still possible to supply a ba
On Wed, Aug 19, 2015 at 10:23:21AM +0300, Pavel Fedin wrote:
> This series introduces support for GICv3 by KVM. Software emulation is
> currently not supported.
>
> v11 => v10
> - Fixed minor issues with checkpatch and comments, reported by Eric Auger
> - Make reusable kvm_gic_supports_attr(), mov
On Wed, Aug 19, 2015 at 10:23:26AM +0300, Pavel Fedin wrote:
> Add gic_version to VirtMachineState, set it to value of the option
> and pass it around where necessary. Instantiate devices and fdt
> nodes according to the choice.
>
> max_cpus for virt machine increased to 126 (calculated from redis
On 25.08.2015 12:25, David kiarie wrote:
On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
wrote:
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
On 08/17/2015 08:58 PM, Eduardo Habkost wrote:
On Thu, Aug 13, 2015 at 11:30:57AM -0400, Richard Smith wrote:
On 08/09/2015 09:48 PM, Ed Swierk wrote:
References to coreboot commits: * Original commit adding code reading
register offsets 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 to
Int
On 25.08.2015 12:41, David kiarie wrote:
On Tue, Aug 25, 2015 at 10:31 AM, Valentine Sinitsyn
[...snip...]
The spec doesn't say anything about this, I checked it. IIRC, I came across
this behavior when submitted COMPLETION_WAIT command with interrupts off and
spin in a while() loop waiting for
Let dataplane allocate different region for the desc/avail/used
ring regions.
Signed-off-by: Pierre Morel
---
hw/virtio/dataplane/vring.c | 54 --
include/hw/virtio/dataplane/vring.h |4 ++-
2 files changed, 47 insertions(+), 11 deletions(-)
diff --
On 24/08/15 14:03, Gavin Shan wrote:
> This allows to include "stdint.h" in virtio header files. Otherwise,
> scripts/update-linux-headers.sh fails when updating headers from
> Linux 4.2.rc8 kernel. include/uapi/linux/virtio_ring.h starts to
> include "stdint.h" from commit d768f32a ("virtio: Fix t
Hello!
> In KVM case instead of assigning GICv2 as default, can we probe the KVM
> for GICv3 presence using KVM_CREATE_DEVICE_TEST and give priority to
> GICv3?
We could, but i think this would hurt usability. I suggest that when the user
chooses a
configuration, he/she expects to get somethin
Hello,
I wrote this mail to the qemu-discuss mailing list, but today I am unsure, if I
chose the right list. So I copy and paste this mail here in hope someone can
respond :-)
I have reproducable problems with some code in qemu-coroutine.c:
void qemu_coroutine_enter(Coroutine *co, void *opaqu
On 24/08/15 14:03, Gavin Shan wrote:
> This supports RTAS calls "ibm,{open,close}-errinjct" to manupliate
> the token, which is passed to RTAS call "ibm,errinjct" to indicate
> the valid context for error injection. Each VM is permitted to have
> only one token at once and we simply have sequential
As far as I can see there's no way to create a snapshot and either
a) inherit the runtime options from the original image
b) specify a new set of options
This comment in external_snapshot_prepare() before calling bdrv_open()
suggests that the problem is known but the discussion was postponed.
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
Guest translation enables nested PCI passthrough
Signed-off-by: David Kiarie
---
hw/i386/Makefile.objs
On 24/08/15 14:03, Gavin Shan wrote:
> This introduces rtas_ldq() to load 64-bits parameter from continuous
> two 4-bytes memory chunk of RTAS parameter buffer, to simplify the
> code.
>
> Signed-off-by: Gavin Shan
> ---
> hw/ppc/spapr_pci.c | 20 ++--
> include/hw/ppc/spapr.
Stumbled over this while throwing away old mail. Andreas, what do you
think?
Ildar Isaev writes:
> 'offset' field in struct Property is calculated as a diff between two
> pointers (hw/core/qdev-properties.c:802)
>
> arrayprop->prop.offset = eltptr - (void *)dev;
>
> If offset is declared as in
On 08/24/2015 11:44 PM, Artyom Tarasenko wrote:
This is very surprising: the patch should have no effect on a sun4u machine.
Er, no, it should. The primary vector by which I expect improvement is via not
encoding dmmu.mmu_primary_context into the TB flags. I.e. ASI_DMMU, which
sun4u certain
On 08/25/2015 06:12 AM, Chen Gang wrote:
From: xili_gchen_5...@hotmail.com
To: r...@twiddle.net; qemu-devel@nongnu.org
CC: w...@tilera.com; cmetc...@ezchip.com; peter.mayd...@linaro.org
Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle a
On 25 August 2015 at 15:17, Markus Armbruster wrote:
> Stumbled over this while throwing away old mail. Andreas, what do you
> think?
Seems right to me -- I suspect the original properties code was
written with the assumption that the property field would be
inside the device struct (and so offs
On 24 August 2015 at 20:36, Richard Henderson wrote:
> Third time's the charm, right?
>
> This time with the arm crash fixed, and two new patches from
> Laurent that came in just as I was preparing this rebase.
>
>
> r~
>
>
> The following changes since commit a30878e708c2149ce07d709a8b62edd944628
On Fri, Aug 14, 2015 at 10:51:59PM +0800, Xiao Guangrong wrote:
> +static void set_file(Object *obj, const char *str, Error **errp)
> +{
> +PCNVDIMMDevice *nvdimm = PC_NVDIMM(obj);
> +
> +if (nvdimm->file) {
> +g_free(nvdimm->file);
> +}
g_free(NULL) is a nop so it's safe to re
Am 25.08.2015 um 16:25 schrieb Richard Henderson:
Er, no, it should. The primary vector by which I expect improvement is via not
encoding dmmu.mmu_primary_context into the TB flags. I.e. ASI_DMMU, which
sun4u certainly uses.
The fact that the patch_also_ fixes a sun4v problem is secondary.
On Aug 25, 2015, at 3:43 AM, Markus Armbruster wrote:
> Programmingkid writes:
>
>> On Aug 24, 2015, at 12:38 PM, Markus Armbruster wrote:
>>
>>> Programmingkid writes:
>>>
On Aug 24, 2015, at 5:45 AM, Markus Armbruster wrote:
> Copying the USB maintainer.
>
> Programm
On Aug 24, 2015, at 6:21 PM, Eric Blake wrote:
> On 08/24/2015 12:53 PM, Programmingkid wrote:
>> Add device ID generation to each device if an ID isn't given.
>>
>> Signed-off-by: John Arbuckle
>>
>> ---
>
>> dev->id = id;
>> +} else { /* create an id for a device if none is prov
Implement the remaining stage 1 TLB invalidate operations
visible from EL3.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1439548879-1972-6-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 76 +
1 fil
emotes/rth/tags/pull-tcg-20150824' into
staging (2015-08-25 13:34:57 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150825
for you to fetch changes up to ff4657fa18b08279ce1f79da35a0e9e0b9574dd5:
target-arm: Im
Implement the missing TLBI operations that exist only
if EL2 is implemented.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1439548879-1972-5-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 22 ++
1 file changed, 22 insertions(+)
d
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.
Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1438281398-
The AFSR registers are implementation dependent auxiliary fault
status registers. We already implemented a RAZ/WI AFSR0_EL1 and
AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1438281398-18746-4-git-send-email-p
The AMAIR registers are for providing auxiliary implementation
defined memory attributes. We already implemented a RAZ/WI
AMAIR_EL1; add the EL2 and EL3 versions for consistency.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1438281398-18746-3-git-send-email-peter.mayd.
Some coprocessor register access functions need to be able
to report "trap to EL3 with an 'uncategorized' syndrome";
add the necessary CPAccessResult enum and handling for it.
I don't currently know of any registers that need to trap
to EL2 with the 'uncategorized' syndrome, but adding the
_EL2 en
Wire up the AArch64 EL2 and EL3 address translation operations
(AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
errors in the ats_write64() function in previously unused code
that would have done the wrong kind of lookup for accesses from
EL3 when SCR.NS==0.
Signed-off-by: Peter Maydel
Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
two which we had implemented the 32-bit Secure equivalents of but
not the 64-bit Secure versions.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1438281398-18746-2-git-send-email-peter.mayd...@linaro.or
Implement the AArch32 ATS1H* operations which perform
Hyp mode stage 1 translations.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1437751263-21913-6-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 22 ++
1 file changed, 22 inserti
Now we have the ability to flush the TLB only for specific MMU indexes,
update the AArch64 TLB maintenance instruction implementations to only
flush the parts of the TLB they need to, rather than doing full flushes.
We take the opportunity to remove some duplicate functions (the per-asid
tlb ops w
From: Alistair Francis
The Xilinx EP108 has four separate OCM banks which are located
adjacent to each other. This patch adds the four banks to
the ZynqMP SoC.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Message-id:
afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.al
From: Alistair Francis
Peter C is leaving Xilinx, so update the maintainer list
to point to Alistair and Edgar from Xilinx and Peter's
personal email address.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Message-id:
54b4c070452bac05aa3a9c1d75899bc097fef831.1436486024.git.ali
Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
* succeed at EL2 or EL3
* normal UNDEF trap from NS EL1
* trap to EL3 from S EL1 (only possible if EL3 is AArch64)
(This change means they're now available in our EL3-supporting
CPUs when
From: Alistair Francis
Add the Xilinx ZynqMP SoC and EP108 machine to the maintainers
file.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Message-id:
fed078103a0b02cfb3adadbe8e80e4420d554505.1436486024.git.alistair.fran...@xilinx.com
Signed-off-by: Peter Maydell
---
MAINTAI
On 25 August 2015 at 00:58, Gavin Shan wrote:
> On Mon, Aug 24, 2015 at 03:08:33PM +0100, Peter Maydell wrote:
>>On 24 August 2015 at 13:03, Gavin Shan wrote:
>>> +cd $to
>>> +name=$(git config --get user.name)
>>> +email=$(git config --get user.email)
>>> +git commit -a -m "$subj
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1439548879-1972-3-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 16 ++
From: Wei Huang
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
Acked-by: Gabriel Somlo
Tested-by: Gabriel Somlo
Tested-by: Leif
From: Wei Huang
This patch generates smbios tables for ARM mach-virt. Also add
CONFIG_SMBIOS=y for ARM default config.
Acked-by: Gabriel Somlo
Tested-by: Gabriel Somlo
Reviewed-by: Laszlo Ersek
Reviewed-by: Shannon Zhao
Tested-by: Leif Lindholm
Signed-off-by: Wei Huang
Message-id: 14394857
On Fri, Aug 14, 2015 at 10:52:00PM +0800, Xiao Guangrong wrote:
> diff --git a/hw/mem/nvdimm/pc-nvdimm.c b/hw/mem/nvdimm/pc-nvdimm.c
> index a53d235..7a270a8 100644
> --- a/hw/mem/nvdimm/pc-nvdimm.c
> +++ b/hw/mem/nvdimm/pc-nvdimm.c
> @@ -24,6 +24,19 @@
>
> #include "hw/mem/pc-nvdimm.h"
>
> +#
For EL2 stage 1 translations, there is no TTBR1. We were already
handling this for 64-bit EL2; add the code to take the 'no TTBR1'
code path for 64-bit EL2 as well.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1437751263-21913-2-git-send-email-peter.mayd...@linaro.org
Implement the AArch64 TLBI operations which take an intermediate
physical address and invalidate stage 2 translations.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Message-id: 1439548879-1972-7-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 55 +
On Aug 25, 2015, at 8:38 AM, Markus Armbruster wrote:
> You're proposing to revise a qdev design decision, namely the purpose of
> IDs. This has been discussed before, and IDs remained unchanged.
> Perhaps it's time to revisit this issue. Cc'ing a few more people.
>
> Relevant prior threads:
>
Guest CPU TLB maintenance operations may be sufficiently
specialized to only need to flush TLB entries corresponding
to a particular MMU index. Implement cputlb functions for
this, to avoid the inefficiency of flushing TLB entries
which we don't need to.
Signed-off-by: Peter Maydell
Reviewed-by:
On 13 August 2015 at 18:09, Wei Huang wrote:
> This patch adds support for SMBIOS 3.0 entry point. When caller invokes
> smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
> smbios_get_tables() will return the entry point table in right format.
> -/* SMBIOS entry point (anchor
ommit 34a4450434f1a5daee06fca223afcbb9c8f1ee24:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into
staging (2015-08-25 13:34:57 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150825-1
for you to fetc
On Aug 25, 2015, at 8:42 AM, Markus Armbruster wrote:
> My other reply is about design issues. This one is about the actual
> code. Until we get rough consensus on the former, the latter doesn't
> really matter, but here goes anyway.
>
> Eric Blake writes:
>
>> On 08/24/2015 12:53 PM, Progra
On Tue, Aug 25, 2015 at 04:17:42PM +0100, Peter Maydell wrote:
> On 13 August 2015 at 18:09, Wei Huang wrote:
> > This patch adds support for SMBIOS 3.0 entry point. When caller invokes
> > smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
> > smbios_get_tables() will return th
On 25 August 2015 at 16:25, Programmingkid wrote:
> On Aug 25, 2015, at 8:42 AM, Markus Armbruster wrote:
>> Eric Blake writes:
>>
>>> On 08/24/2015 12:53 PM, Programmingkid wrote:
+/* USB's max number of devices is 127. This number is 3 digits long. */
+#define MAX_NUM_DIGITS_FOR_USB_I
On Fri, Aug 14, 2015 at 10:52:00PM +0800, Xiao Guangrong wrote:
> NVDIMM reserves all the free range above 4G to do:
> - Persistent Memory (PMEM) mapping
> - implement NVDIMM ACPI device _DSM method
>
> Signed-off-by: Xiao Guangrong
> ---
> hw/i386/pc.c | 12 ++--
> hw/mem/
I have created a wiki page for virtio-vsock.
It links to my git repos and the draft virtio specification:
http://qemu-project.org/Features/VirtioVsock
I'll expand and update it over the coming days and weeks.
Please let me know if you'd like to see specific information on there
(e.g. step-by-ste
On Aug 25, 2015, at 11:33 AM, Peter Maydell wrote:
> On 25 August 2015 at 16:25, Programmingkid wrote:
>> On Aug 25, 2015, at 8:42 AM, Markus Armbruster wrote:
>>> Eric Blake writes:
>>>
On 08/24/2015 12:53 PM, Programmingkid wrote:
> +/* USB's max number of devices is 127. This numbe
On 08/25/2015 10:29 AM, Leif Lindholm wrote:
> On Tue, Aug 25, 2015 at 04:17:42PM +0100, Peter Maydell wrote:
>> On 13 August 2015 at 18:09, Wei Huang wrote:
>>> This patch adds support for SMBIOS 3.0 entry point. When caller invokes
>>> smbios_set_defaults(), it can specify entry point as 2.1 or
On 25 August 2015 at 16:59, Wei Huang wrote:
> On 08/25/2015 10:29 AM, Leif Lindholm wrote:
>> Wei - is there actually any particular point in renaming this
>> structure? In all versions of the specification before 3.0, this was
>> only known as the "smbios entry point". Only with the introduction
On Fri, Aug 14, 2015 at 10:52:01PM +0800, Xiao Guangrong wrote:
> The parameter @file is used as backed memory for NVDIMM which is
> divided into two parts if @dataconfig is true:
s/dataconfig/configdata/
> @@ -76,13 +109,87 @@ static void pc_nvdimm_init(Object *obj)
>
From: "Jason J. Herne"
A new QOM style device is provided to back guest storage keys. A special
version for KVM is created, which handles the storage key access via
KVM_S390_GET_SKEYS and KVM_S390_SET_SKEYS ioctl.
Reviewed-by: David Hildenbrand
Signed-off-by: Jason J. Herne
Signed-off-by: Corn
From: "Jason J. Herne"
Provide an info skeys hmp sub-command to allow the end user to dump a storage
key for a given address. This is useful for guest operating system developers.
Reviewed-by: Thomas Huth
Reviewed-by: David Hildenbrand
Signed-off-by: Jason J. Herne
Signed-off-by: Cornelia Hu
Here's the second edition of the storage key migration patches.
Changes from v1:
- have the dump-skeys qmp command use qemu_fopen() and friends
- handle failures of the skeys-obtaining commands by filling the
stream with zeroes and setting an error flag
Would like to send a pull request soonish
Reviewed-by: Jason J. Herne
Signed-off-by: Cornelia Huck
Acked-by: Christian Borntraeger
---
hw/s390x/s390-virtio-ccw.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 4c51d1a..71df282 100644
From: "Jason J. Herne"
This code disables storage key migration when an older machine type is
specified.
Reviewed-by: David Hildenbrand
Signed-off-by: Jason J. Herne
Signed-off-by: Cornelia Huck
---
hw/s390x/s390-skeys.c | 33 ++---
hw/s390x/s390-virtio-
From: "Jason J. Herne"
s390 guest initialization is modified to make use of new s390-storage-keys
device. Old code that globally allocated storage key array is removed.
The new device enables storage key access for kvm guests.
Cache storage key QOM objects in frequently used helper functions to
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