On 04/10/2018 18:08, Wei Huang wrote:
> This patch adds migration test support for aarch64. The test code, which
> implements the same functionality as x86, is booted as a kernel in qemu.
> Here are the design choices we make for aarch64:
>
> * We choose this -kernel approach because aarch64 Q
On Sun, Oct 07, 2018 at 19:09:01 -0700, Richard Henderson wrote:
> On 10/6/18 2:45 PM, Emilio G. Cota wrote:
> > Currently we evict an entry to the victim TLB when it doesn't match
> > the current address. But it could be that there's no match because
> > the current entry is invalid. Do not evict
On 2018-10-08 16:20, Tony Krowiak wrote:
> On 09/27/2018 08:52 AM, Cornelia Huck wrote:
>> On Thu, 27 Sep 2018 14:29:01 +0200
>> Thomas Huth wrote:
>>
>>> On 2018-09-27 00:54, Tony Krowiak wrote:
From: Tony Krowiak
Introduces the base object model for virtualizing AP devices.
From: Dongjiu Geng
The parameter of kvm_arm_init_cpreg_list() is ARMCPU instead of
CPUState, so correct the note to make it match the code.
Signed-off-by: Dongjiu Geng
Message-id: 1538069046-5757-1-git-send-email-gengdong...@huawei.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
-
Emilio G. Cota writes:
> On Mon, Oct 08, 2018 at 14:57:18 +0100, Alex Bennée wrote:
>> Emilio G. Cota writes:
>> > The readers that do not hold tlb_lock must use atomic reads when
>> > reading .addr_write, since this field can be updated by other threads;
>> > the conversion to atomic reads is
From: Richard Henderson
Check for EL3 before testing CPTR_EL3.EZ. Return 0 when the exception
should be routed via AdvSIMDFPAccessTrap. Mirror the structure of
CheckSVEEnabled more closely.
Fixes: 5be5e8eda78
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Hend
Emilio G. Cota writes:
> On Mon, Oct 08, 2018 at 11:28:38 +0100, Alex Bennée wrote:
>> Emilio G. Cota writes:
>> > Again, for performance you'd avoid the tracepoint (i.e. calling
>> > a helper to call another function) and embed directly the
>> > callback from TCG. Same thing applies to TB's.
From: Richard Henderson
We are going to want to determine whether sve is enabled
for EL other than current.
Tested-by: Laurent Desnogues
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
--
Add the v8M stack checks for:
* LDRD (immediate)
* STRD (immediate)
Loads and stores are more complicated than ADD/SUB/MOV, because we
must ensure that memory accesses below the stack limit are not
performed, so we can't simply do the check when we actually update
SP.
For these instructions, if
On Mon, 8 Oct 2018 16:22:27 +0200
David Hildenbrand wrote:
> On 08/10/2018 16:20, Tony Krowiak wrote:
> > On 09/27/2018 08:52 AM, Cornelia Huck wrote:
> >> On Thu, 27 Sep 2018 14:29:01 +0200
> >> Thomas Huth wrote:
> >>
> >>> On 2018-09-27 00:54, Tony Krowiak wrote:
> From: Tony Krowi
Add v8M stack checks for the 16-bit Thumb push/pop
encodings: STMDB, STMFD, LDM, LDMIA, LDMFD.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20181002163556.10279-12-peter.mayd...@linaro.org
---
target/arm/translate.c | 16 ++
On 3 October 2018 at 16:07, Edgar E. Iglesias wrote:
> In QEMU we'd like to have a virtual developer board with the Versal SoC
> and a selected set of peripherals under the control of QEMU.
> We'd like to gradually extend this board as QEMU gains more support
> for Versal hardware components. QEMU
> From: Dimitrije Nikolic
>
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
>
> Signed-off-by: Aleksandar Markovic
This patch is incomplete. The pool P.LS.E0 has three subpools, and, for each of
them,
correspondin
Coverity complains (CID 1395628) that the multiply in the calculation
of the framebuffer base is performed as 32x32 but then used in a
context that takes a 64-bit hwaddr. This can't actually ever
overflow the 32-bit result, because of the constraints placed on
the s->config values in bcm2835_fb_val
On 08/10/2018 16:20, Tony Krowiak wrote:
> On 09/27/2018 08:52 AM, Cornelia Huck wrote:
>> On Thu, 27 Sep 2018 14:29:01 +0200
>> Thomas Huth wrote:
>>
>>> On 2018-09-27 00:54, Tony Krowiak wrote:
From: Tony Krowiak
Introduces the base object model for virtualizing AP devices.
On Mon, 8 Oct 2018 14:41:50 +0200
David Hildenbrand wrote:
> On 08/10/2018 14:19, Igor Mammedov wrote:
> > On Mon, 8 Oct 2018 13:47:53 +0200
> > David Hildenbrand wrote:
> >
> >>> That way using [2] and [1 - modulo it should match only concrete type]
> >>> machine would be able to override ho
Add the v8M stack checks for the VLDM/VSTM
(aka VPUSH/VPOP) instructions. This code is currently
unreachable because we haven't yet implemented M profile
floating point support, but since the change is simple,
we add it now because otherwise we're likely to forget to
do it later.
Signed-off-by: Pe
> From: Stefan Markovic
>
> Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
>
> Signed-off-by: Aleksandar Markovic
I think check_dspr3() should be check_dsp_r3(), but
On Mon, Oct 08, 2018 at 14:57:18 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
> > The readers that do not hold tlb_lock must use atomic reads when
> > reading .addr_write, since this field can be updated by other threads;
> > the conversion to atomic reads is done in the next patch.
>
> We
Pavel Dovgalyuk writes:
> I guess this one is too tcg-dependent.
> It count TB's, but breaking code into TBs may depend on many things,
> like breakpoints, record/replay, ...
>
> I mean that this measuring approach may be used only in some specific
> cases, and not ok as an example.
You are ri
Updating the NS stack pointer via MSR to SP_NS should include
a check whether the new SP value is below the stack limit.
No other kinds of update to the various stack pointer and
limit registers via MSR should perform a check.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Revi
Check the v8M stack limits when pushing the frame for a
non-secure function call via BLXNS.
In order to be able to generate the exception we need to
promote raise_exception() from being local to op_helper.c
so we can call it from helper.c.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathi
From: Richard Henderson
Given that the only field defined for this new register may only
be 0, we don't actually need to change anything except the name.
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-2-richard.hender.
On Sun, Oct 07, 2018 at 21:48:34 -0400, Emilio G. Cota wrote:
> - 70/40% use rate for growing/shrinking the TLB does not
> seem a great choice, if one wants to avoid a pathological
> case that can induce constant resizing. Imagine we got
> exactly 70% use rate, and all TLB misses were compuls
Add checks for breaches of the v8M stack limit when the
stack pointer is decremented to push the exception frame
for exception entry.
Note that the exception-entry case is unique in that the
stack pointer is updated to be the limit value if the limit
is hit (per rule R_ZLZG).
Signed-off-by: Peter
> From: Stefan Markovic
>
> Add DSP R3 ASE related bit definition for insn_flags and hflags.
>
> Signed-off-by: Aleksandar Markovic
This should be integrated with other pending insn_flags cleanups.
hflags need cleaning too, but this is not planned this year. Any such
cleanup should be beyond
A cut-and-paste error meant we were reading r4 from the v8M
callee-saves exception stack frame twice. This is harmless
since it just meant we did two memory accesses to the same
location, but it's unnecessary. Delete it.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-b
From: Richard Henderson
This implements the feature for softmmu, and moves the
main loop out of a macro and into a function.
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-15-richard.hender...@linaro.org
Signed-off-by:
From: Richard Henderson
This fixes the endianness problem for softmmu, and moves the
main loop out of a macro and into an inlined function.
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-10-richard.hender...@linaro.org
In commit c79c0a314c43b78 we enabled emulation of external aborts
when the guest attempts to access a physical address with no
mapped device. In commit 4672cbd7bed88dc6 we suppress this for
most legacy boards to prevent breakage of previously working
guests, but we didn't suppress it in the 'virt'
Add the v8M stack checks for:
* LDM (T2 encoding)
* STM (T2 encoding)
This includes the 32-bit encodings of the instructions listed
in v8M ARM ARM rule R_YVWT as
* LDM, LDMIA, LDMFD
* LDMDB, LDMEA
* POP (multiple registers)
* PUSH (muliple registers)
* STM, STMIA, STMEA
* STMDB, STMFD
We
From: Richard Henderson
There is quite a lot of code required to compute cpu_mem_index,
or even put together the full TCGMemOpIdx. This can easily be
done at translation time.
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20181005175350.
From: Richard Henderson
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Tested-by: Laurent Desnog
In v7m_exception_taken() we were incorrectly using a
"LR bit EXCRET.ES is 1" check when it should be 0
(compare the pseudocode ExceptionTaken() function).
This meant we didn't stack the callee-saved registers
when tailchaining from a NonSecure to a Secure exception.
Cc: qemu-sta...@nongnu.org
Sign
Add some comments to the Thumb decoder indicating what bits
of the instruction have been decoded at various points in
the code.
This is not an exhaustive set of comments; we're gradually
adding comments as we work with particular bits of the code.
Signed-off-by: Peter Maydell
Reviewed-by: Philip
Define EXCP_STKOF, and arrange for it to cause us to take
a UsageFault with CFSR.STKOF set.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20181002163556.10279-3-peter.mayd...@linaro.org
---
target/arm/cpu.h| 2 ++
target/arm/hel
From: Richard Henderson
This fixes the endianness problem for softmmu, and moves
the main loop out of a macro and into an inlined function.
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-14-richard.hender...@linaro.org
Add v8M stack checks for the instructions in the T32
"load/store single" encoding class: these are the
"immediate pre-indexed" and "immediate, post-indexed"
LDR and STR instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 2018
From: Richard Henderson
We can choose the endianness at translation time, rather than
re-computing it at execution time.
Tested-by: Laurent Desnogues
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-11-richard.hender...@linaro.org
Signed-of
From: Richard Henderson
SVE vector length can change when changing EL, or when writing
to one of the ZCR_ELn registers.
For correctness, our implementation requires that predicate bits
that are inaccessible are never set. Which means noticing length
changes and zeroing the appropriate register
On 5 October 2018 at 19:01, Richard Henderson
wrote:
> The following changes since commit ae7a4c0a4604bcfed40170db6cca576c44d872a2:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181004' into
> staging (2018-10-05 16:05:06 +0100)
>
> are available in the Git repository at:
>
>
On 4/10/2018 6:52 PM, Kevin Wolf wrote:
> Am 21.08.2018 um 11:46 hat Anton Nefedov geschrieben:
>> This will help to identify how many of the user-issued discard operations
>> (accounted on a device level) have actually suceeded down on the host file
>> (even though the numbers will not be exactl
Add code to insert calls to a helper function to do the stack
limit checking when we handle these forms of instruction
that write to SP:
* ADD (SP plus immediate)
* ADD (SP plus register)
* SUB (SP minus immediate)
* SUB (SP minus register)
* MOV (register)
Signed-off-by: Peter Maydell
Revie
The Arm v8M architecture includes hardware stack limit checking.
When certain instructions update the stack pointer, if the new
value of SP is below the limit set in the associated limit register
then an exception is taken. Add a TB flag that tracks whether
the limit-checking code needs to be emitt
From: Richard Henderson
Use the same *_tlb primitives as we use for ld1.
For linux-user, this hoists the set of helper_retaddr. For softmmu,
hoists the computation of the current mmu_idx outside the loop,
fixes the endianness problem, and moves the main loop out of a
macro and into an inlined f
We're going to want v7m_using_psp() in op_helper.c in the
next patch, so move it from helper.c to internals.h.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20181002163556.10279-4-peter.mayd...@linaro.org
---
target/arm/internals.h
From: Richard Henderson
We can choose the endianness at translation time, rather than
re-computing it at execution time.
Tested-by: Laurent Desnogues
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-12-richard.hender...@linaro.org
Signed-of
From: Richard Henderson
Use the existing helpers to determine if (1) the fpu is enabled,
(2) sve state is enabled, and (3) the current sve vector length.
Tested-by: Laurent Desnogues
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-6-richard.hender.
From: Richard Henderson
Uses tlb_vaddr_to_host for correct operation with softmmu.
Optimize for accesses within a single page or pair of pages.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-8-richard.hender...@linaro.org
Signed-off-by: Peter Mayde
From: Richard Henderson
This fixes the endianness problem for softmmu, and moves
the main loop out of a macro and into an inlined function.
Reviewed-by: Peter Maydell
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
Message-id: 20181005175350.30752-13-richard.hender...@linaro.org
On Mon, Oct 08, 2018 at 11:28:38 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
> > Again, for performance you'd avoid the tracepoint (i.e. calling
> > a helper to call another function) and embed directly the
> > callback from TCG. Same thing applies to TB's.
>
> OK I see what you mean. I th
/pull-fpu-20181005' into
staging (2018-10-08 12:44:35 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20181008
for you to fetch changes up to 74e2e59b8d0a68be0956310fc349179c89fd7be0:
hw/display/bcm2835_fb: Silenc
Emilio G. Cota writes:
> Currently we rely on atomic operations for cross-CPU invalidations.
> There are two cases that these atomics miss: cross-CPU invalidations
> can race with either (1) vCPU threads flushing their TLB, which
> happens via memset, or (2) vCPUs calling tlb_reset_dirty on the
Kashyap Chamarthy writes:
> On Mon, Oct 01, 2018 at 11:28:17AM +0200, Thomas Huth wrote:
>> On 2018-09-25 18:02, Kashyap Chamarthy wrote:
>
> [...]
>
>> > +++ b/qapi/misc.json
>> > @@ -1104,7 +1104,11 @@
>> > ##
>> > # @cpu-add:
>> > #
>> > -# Adds CPU with specified ID
>> > +# Adds CPU with s
Marc-André Lureau writes:
> Hi
>
> On Sat, Sep 1, 2018 at 4:06 PM Marc-André Lureau
> wrote:
>>
>> On Sat, Sep 1, 2018 at 12:59 PM, Markus Armbruster wrote:
>> > Marc-André Lureau writes:
>> >
>> >> Let qmp_dispatch() copy the 'id' field. That way any qmp client will
>> >> conform to the speci
Marc-André Lureau writes:
> Hi
> On Thu, Aug 30, 2018 at 6:03 PM Markus Armbruster wrote:
>>
>> Marc-André Lureau writes:
>>
>> > Simplify the code around qmp_dispatch():
>> > - rely on qmp_dispatch/check_obj() for message checking
>> > - have a single send_response() point
>> > - constify send
20.09.2018 22:40, Eric Blake wrote:
> [reviving an old patch]
>
> On 1/16/18 6:54 AM, Vladimir Sementsov-Ogievskiy wrote:
>> Signed-off-by: Vladimir Sementsov-Ogievskiy
>> ---
>> qapi/block-core.json | 38
>> ++
>> include/block/dirty-bitmap.h | 2 +
On 3 October 2018 at 16:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add a model of Xilinx Versal SoC.
>
> Signed-off-by: Edgar E. Iglesias
> ---
> default-configs/aarch64-softmmu.mak | 1 +
> hw/arm/Makefile.objs| 1 +
> hw/arm/xlnx-versal.c|
when '-no-reboot' is set, it is interesting if the guest was originally
shutdown or reset, so save and return that info
Signed-off-by: Dominik Csapak
---
qapi/run-state.json | 5 -
vl.c| 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/qapi/run-state.js
On 3 October 2018 at 16:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add the ARM Cortex-A72.
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target/arm/cpu64.c | 59
> ++
> 1 file changed, 59 insertions(+)
>
> diff --git a/target
I guess this one is too tcg-dependent.
It count TB's, but breaking code into TBs may depend on many things,
like breakpoints, record/replay, ...
I mean that this measuring approach may be used only in some specific
cases, and not ok as an example.
Pavel Dovgalyuk
> -Original Message-
> F
Paolo Bonzini writes:
> Commit 31d2dda ("build-system: remove per-test GCOV reporting", 2018-06-20)
> removed users of the variables, since those uses can be replaced by a simple
> overall report produced by gcovr. However, the variables were never removed.
> Do it now.
>
> Signed-off-by: Paol
On 08/10/2018 14:19, Igor Mammedov wrote:
> On Mon, 8 Oct 2018 13:47:53 +0200
> David Hildenbrand wrote:
>
>>> That way using [2] and [1 - modulo it should match only concrete type]
>>> machine would be able to override hotplug handlers for TYPE_VIRTIO_PMEM_PCI
>>> and explicitly call machine + p
The spapr-rng device is suboptimal when compared to virtio-rng, so
users might want to disable it in their builds. Thus let's introduce
a proper CONFIG switch to allow us to compile QEMU without this device.
The function spapr_rng_populate_dt is required for linking, so move it
to a different locat
Hi Alex,
On 08/10/2018 12:28, Alex Bennée wrote:
>
> Emilio G. Cota writes:
>
>> On Fri, Oct 05, 2018 at 16:48:49 +0100, Alex Bennée wrote:
>> (snip)
>>> ==Known Limitations==
>>>
>>> Currently there is only one hook allowed per trace event. We could
>>> make this more flexible or simply just e
On 3 October 2018 at 16:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> When QEMU provides the equivalent of the EL3 firmware, we
> need to enable HVCs in scr_el3 when turning on CPUs that
> target EL2.
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target/arm/arm-powerctl.c | 11 +++
Alex Bennée writes:
> Now we have counts for each trace point we can expose them in the
> monitor when the user queries what trace points are available.
>
> Signed-off-by: Alex Bennée
> ---
> monitor.c | 5 +++--
> qapi/trace.json | 3 ++-
> trace/qmp.c | 1 +
> 3 files changed, 6 ins
On 3 October 2018 at 16:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for selecting the Memory Region that the GEM
> will do DMA to.
>
> Signed-off-by: Edgar E. Iglesias
> ---
> hw/net/cadence_gem.c | 63
>
> inclu
On 6 October 2018 at 00:14, Philippe Mathieu-Daudé wrote:
> Hi Edgar,
>
> On 03/10/2018 17:07, Edgar E. Iglesias wrote:
>> From: "Edgar E. Iglesias"
>>
>> Add support for selecting the Memory Region that the GEM
>> will do DMA to.
>> @@ -1500,6 +1506,13 @@ static void gem_realize(DeviceState *de
On 3 October 2018 at 16:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for selecting the Memory Region that the GEM
> will do DMA to.
>
> Signed-off-by: Edgar E. Iglesias
> ---
> @@ -1500,6 +1506,13 @@ static void gem_realize(DeviceState *dev, Error **errp)
> Cad
On Mon, 8 Oct 2018 13:47:53 +0200
David Hildenbrand wrote:
> > That way using [2] and [1 - modulo it should match only concrete type]
> > machine would be able to override hotplug handlers for TYPE_VIRTIO_PMEM_PCI
> > and explicitly call machine + pci hotplug handlers in necessary order.
> >
> >
> That way using [2] and [1 - modulo it should match only concrete type]
> machine would be able to override hotplug handlers for TYPE_VIRTIO_PMEM_PCI
> and explicitly call machine + pci hotplug handlers in necessary order.
>
> flow would look like:
> [acpi|shcp|native pci-e eject]->
>
On 7 October 2018 at 19:05, Samuel Thibault
wrote:
> The following changes since commit 3c2d3042849686969add641bd38b08b9877b9e8f:
>
> Merge remote-tracking branch
> 'remotes/mcayland/tags/qemu-openbios.for-upstream-20181005' into staging
> (2018-10-05 17:55:22 +0100)
>
> are available in the G
Hyper-V PV IPI enlightenment was merged to KVM (kvm/queue currently).
Support the feature enablement in Qemu.
Vitaly Kuznetsov (2):
linux-headers: update to pre-4.20 (kvm/queue)
i386/kvm: add support for Hyper-V IPI send
linux-headers/linux/kvm.h | 7 +--
target/i386/cpu.c |
This brings us three new defines: KVM_CAP_ARM_INJECT_SERROR_ESR,
KVM_CAP_MSR_PLATFORM_INFO and KVM_CAP_HYPERV_SEND_IPI.
Signed-off-by: Vitaly Kuznetsov
---
linux-headers/linux/kvm.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/linux-headers/linux/kvm.h b/linux-heade
Hyper-V PV IPI support is merged to KVM, enable the feature in Qemu. When
enabled, this allows Windows guests to send IPIs to other vCPUs with a
single hypercall even when there are >64 vCPUs in the request.
Signed-off-by: Vitaly Kuznetsov
---
target/i386/cpu.c | 1 +
target/i386/cpu.h
On 08/10/2018 09:09, Pavel Dovgalyuk wrote:
> Paolo,
>
>> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
>> On 11/09/2018 08:00, Pavel Dovgalyuk wrote:
>>> Thanks, that works. Here is the updated diff (stubs were added).
>>> Will you apply it?
>>
>> Yes, thanks for the quick test!
>
> Thanks fo
On 2018-10-08 02:57, David Gibson wrote:
> On Fri, Oct 05, 2018 at 08:12:12AM +0200, Thomas Huth wrote:
>> On 2018-10-05 06:25, David Gibson wrote:
>>> On Thu, Oct 04, 2018 at 12:07:01PM +0200, Thomas Huth wrote:
The spapr-rng device is suboptimal when compared to virtio-rng, so
users mig
* Li Qiang (liq...@163.com) wrote:
> When migrate_add_blocker failed, the invtsc_mig_blocker is not
> appended so no need to remove. This can save several instructions.
>
> Signed-off-by: Li Qiang
> ---
> target/i386/kvm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a
Thanks for your help, turns out that the hotlpug is set by piix4 after
the devices are realized.
On Mon, Oct 8, 2018 at 11:28 AM Igor Mammedov wrote:
>
> On Sun, 7 Oct 2018 12:52:11 +0300
> Sameeh Jubran wrote:
>
> > This is the command line. All of the devices are wired to pci.0, there is
> > no
Emilio G. Cota writes:
> On Fri, Oct 05, 2018 at 16:48:49 +0100, Alex Bennée wrote:
> (snip)
>> ==Known Limitations==
>>
>> Currently there is only one hook allowed per trace event. We could
>> make this more flexible or simply just error out if two plugins try
>> and hook to the same point. Wh
On 5 October 2018 at 18:53, Richard Henderson
wrote:
> For v3, the only change is to patch 4, which is also the only
> patch without a reviewed-by tag.
>
> I now check for aa64 state before checking for sve length, and
> added a comment about why it is important to play with sve when
> transitioni
On 5 October 2018 at 13:28, Marc-André Lureau
wrote:
> The following changes since commit b8e5671a8cd196e7262802ca895bf87d50416989:
>
> Merge remote-tracking branch 'remotes/elmarco/tags/chardev-pull-request'
> into staging (2018-10-03 14:07:49 +0100)
>
> are available in the Git repository at:
On Fri, 5 Oct 2018 17:00:01 +0200
Thomas Huth wrote:
> Debug macros that are disabled by default should be avoided (since the
> code bit-rots quite easily). Thus turn these debug prints into proper
> qemu_log_mask(CPU_LOG_xxx, ...) statements instead. The DPRINTF statements
> in do_[ext|io|mchk]
Emilio G. Cota writes:
> On Fri, Oct 05, 2018 at 16:48:53 +0100, Alex Bennée wrote:
>> Our performance isn't so critical that we can't spare a simple flag
>> check when we exec a TB considering everything else we check in the
>> outer loop.
>
> [I know this is just done to illustrate how functi
05.10.2018 22:34, Max Reitz wrote:
On 02.10.18 15:01, Vladimir Sementsov-Ogievskiy wrote:
28.09.2018 19:31, Max Reitz wrote:
On 23.08.18 17:46, Vladimir Sementsov-Ogievskiy wrote:
Add a new command, returning block nodes (and their users) graph.
Signed-off-by: Vladimir Sementsov-Ogievskiy
--
On 8 October 2018 at 03:16, Li Qiang wrote:
> Cc: qemu-triv...@nongnu.org
> Signed-off-by: Li Qiang
> ---
> util/aio-posix.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/util/aio-posix.c b/util/aio-posix.c
> index 621b302..51c41ed 100644
> --- a/util/aio-posix.c
> +++
On 5 October 2018 at 19:09, Kevin Wolf wrote:
> And if we disable it wholesale, then nobody has any incentive to fix any
> bug that the test case could have uncovered.
Yes, that's fair. I'm sorry; I was a bit grumpy when I wrote
that email because my test runs had been bumping into it all day.
>
Am 06.10.2018 um 20:38 hat Stefan Weil geschrieben:
> Use %zu instead of %zd for unsigned numbers.
>
> This fixes two error messages from the LSTM static code analyzer:
>
> This argument should be of type 'ssize_t' but is of type 'unsigned long'
>
> Signed-off-by: Stefan Weil
Thanks, applied t
On 8 October 2018 at 07:14, Thomas Huth wrote:
> On 2018-10-05 18:32, Peter Maydell wrote:
>> On 5 October 2018 at 10:42, Thomas Huth wrote:
>>> Each device that is instantiatable by the users should be marked with
>>> a category.
>>
>> Presumably we could assert() this somewhere (at which
>> poi
On 5 October 2018 at 12:11, Gerd Hoffmann wrote:
> The following changes since commit dafd95053611aa14dda40266857608d12ddce658:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2018-10-02 18:27:18 +0100)
>
> are available in the git repository at:
>
> git:/
On 05/10/2018 17:00, Thomas Huth wrote:
> Debug macros that are disabled by default should be avoided (since the
> code bit-rots quite easily). Thus turn these debug prints into proper
> qemu_log_mask(CPU_LOG_xxx, ...) statements instead. The DPRINTF statements
> in do_[ext|io|mchk]_interrupt can e
On Sun, 7 Oct 2018 12:52:11 +0300
Sameeh Jubran wrote:
> This is the command line. All of the devices are wired to pci.0, there is
> no pci bridge.
>
> According to this, Integrated Endpoints are not hot-pluggable. However I
> can still use device_del to delete a device and device_add to add e1
On 10/8/18 5:28 AM, Jason Wang wrote:
On 2018年10月04日 19:43, Dominik Csapak wrote:
this patch series aims to execute a script when qemu exits
so that one can do cleanups when using --daemonize without
having to use the qmp monitor
Hi:
Can you give a example of why it must be done through thi
Hello Paolo, Lei, Gerd and all,
Recently I encounter a strange issue about bootindex.
I have two disk named "disk1.test" and "disk1".
When using disk1.test alone, the login picture is: (hostname is localhost)
[image: image.png]
When using disk1 alone, the login picture is:(hostname is nimlite
On Tue, Oct 02, 2018 at 01:13:10PM +0400, Marc-André Lureau wrote:
> Hi Peter
>
> On Sat, Sep 29, 2018 at 8:05 AM Peter Xu wrote:
> >
> > On Fri, Sep 28, 2018 at 04:06:30PM +0400, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Wed, Sep 5, 2018 at 10:24 AM Peter Xu wrote:
> > > >
> > > > Curren
Great to hear that.
To get these patches merged you need to prepare a patch(es)
and send them for review first. See https://spdk.io/development/ for
information how to do that.
Pawel
> -Original Message-
> From: SPDK [mailto:spdk-boun...@lists.01.org] On Behalf Of Nikos Dragazis
> Sent:
Paolo,
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> On 11/09/2018 08:00, Pavel Dovgalyuk wrote:
> > Thanks, that works. Here is the updated diff (stubs were added).
> > Will you apply it?
>
> Yes, thanks for the quick test!
Thanks for applying RR patches, but I think you forgot about thi
Le 08/10/2018 à 06:27, Cortland Tölva a écrit :
> From: Cortland Setlow Tölva
>
> This patch series enables programs running under QEMU Linux user mode
> emulation to implement user-space USB drivers via the USBFS ioctl()s.
> Support is limited to control, bulk, and possibly interrupt transfers.
There are two callers for vtd_sync_shadow_page_table_range(): one
provided a valid context entry and one not. Move that fetching
operation into the caller vtd_sync_shadow_page_table() where we need to
fetch the context entry.
Meanwhile, remove the error_report_once() directly since we're already
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