Kevin Wolf writes:
> Am 18.06.2019 um 11:01 hat Daniel P. Berrangé geschrieben:
>> On Mon, Jun 17, 2019 at 08:49:03PM +0200, Markus Armbruster wrote:
>> > From: Kevin Wolf
>> >
>> > The -mon pretty=on|off switch of the -mon option applies only to QMP
>> > monitors. It's silently ignored for HMP
On Tue, Jun 18, 2019 at 05:59:56PM +0200, Igor Mammedov wrote:
>
>On Mon, 13 May 2019 14:19:04 +0800
>Wei Yang wrote:
>
>> Now MADT is highly depend in architecture and machine type and leaves
>> duplicated code in different architecture. The series here tries to
>> generalize
>> it.
>>
>> MADT
On Wed, Jun 19, 2019 at 6:21 AM Alistair Francis
wrote:
>
> If the user hasn't specified a firmware to load (with -bios) or
> specified no bios (with -bios none) then load OpenSBI by default. This
> allows users to boot a RISC-V kernel with just -kernel.
>
> Signed-off-by: Alistair Francis
> ---
On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis
wrote:
>
> Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
>
> Signed-off-by: Alistair Francis
> ---
> .gitmodules | 3 +++
> Makefile| 3 ++-
> configure
On 18/06/2019 06:00, Richard Henderson wrote:
> Ping. Otherwise I'll include it in my next tcg pull.
>
> r~
I can give this another spin on my test images on a G4 over the next few days.
I've
also added Howard on CC as he reported some issues with the previous iteration
at
https://lists.gnu.o
Add all SSE2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 160 ---
1 file changed, 153 insertions(+), 7 deletions(-)
diff --git a/x86.risu b/x86.risu
index cc40bbc..b3e4c88 100644
--- a/x86.risu
+++ b/x86
The risugen_x86.pm module contains most of the code specific to Intel
i386 and x86_64 architectures. This commit also adds --x86_64 option,
which enables emission of 64-bit (rather than 32-bit) assembly.
Signed-off-by: Jan Bobek
---
risugen| 6 +-
risugen_x86.pm | 455 +
Accept all instructions whose bit length is divisible by 8. Note that
the maximum instruction length (as specified in the config file) is 32
bits, hence this change permits instructions which are 8 bits or 24
bits long (16-bit instructions have already been considered valid).
Note that while valid
Hi all,
this is v1 of my changes to risugen in order to support generating x86
test images. It's still work-in-progress (thus marked RFC; notably,
there is no support for AVX yet), but I would like to get this out
there to get some early feedback on my approach.
Initially, I thought adding suppor
Add three common utility functions:
- insnv allows emitting variable-length instructions in little-endian
or big-endian byte order; it subsumes functionality of former
insn16() and insn32() functions.
- randint_constr allows generating random integers according to
several constraints passed
The module risugen_x86_asm.pm exports several constants and the
function write_insn, which work in tandem to allow emission of x86
instructions in more clear and structured manner.
Signed-off-by: Jan Bobek
---
risugen_x86_asm.pm | 186 +
1 file changed
Add an x86 configuration file with all SSE instructions.
Signed-off-by: Jan Bobek
---
x86.risu | 99
1 file changed, 99 insertions(+)
create mode 100644 x86.risu
diff --git a/x86.risu b/x86.risu
new file mode 100644
index 000..cc40bb
The helper module risugen_x86_emit.pm exports a single function
"parse_emitblock", which serves to capture and return instruction
constraints described by "emit" blocks in an x86 configuration file.
Signed-off-by: Jan Bobek
---
risugen | 2 +-
risugen_x86_emit.pm | 85 ++
Signed-off-by: Alistair Francis
---
MAINTAINERS| 6 ++
hw/arm/Kconfig | 3 +++
hw/arm/Makefile.objs | 1 +
hw/arm/netduinoplus2.c | 58 ++
4 files changed, 68 insertions(+)
create mode 100644 hw/arm/netduinoplus2.c
dif
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
MAINTAINERS| 8 ++
hw/arm/Kconfig | 3 +
hw/arm/Makefile.objs | 1 +
hw/arm/stm32f405_soc.c | 301 +
include/hw/arm/stm32f405_soc.h |
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
default-configs/arm-softmmu.mak| 1 +
hw/arm/Kconfig | 9 ++
hw/misc/Kconfig| 3 +
hw/misc/Makefile.objs | 1 +
hw/misc/stm32f4xx_syscfg.c | 168 +++
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
hw/arm/Kconfig | 1 +
hw/misc/Kconfig | 3 +
hw/misc/Makefile.objs| 1 +
hw/misc/stm32f4xx_exti.c | 187 +++
hw/misc/trace-events
Allow the kernel's entry point information to be returned when loading a
kernel.
Signed-off-by: Alistair Francis
---
hw/arm/armv7m.c | 4 +++-
include/hw/arm/boot.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index b9efad6bac..
Now that the Arm-M4 CPU has been added to QEMU we can add the Netduino
Plus 2 machine. This is very similar to the STM32F205 and Netduino 2 SoC
and machine.
v3:
- Remove custom reset handler
- Add init-entry and init-sp properties
- Rebase on master (including Kconfig changes)
v2:
- Reorder p
Add M mode initial entry PC and SP properties.
Signed-off-by: Alistair Francis
---
target/arm/cpu.c | 47 +++
target/arm/cpu.h | 3 +++
2 files changed, 50 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 376db154f0..1d83972ab1 10
>>> On 6/18/2019 at 6:11 PM, John Snow wrote:
>
> On 6/18/19 7:37 PM, Bruce Rogers wrote:
>> Hi,
>>
>> (Resent with correct address for John)
>> I build recent upstream qemu in the openSUSE Build Service, and for
>> the Factory repository there, python-sphinx was recently updated to
>> version
On Fri, Jun 14, 2019 at 10:24 AM Alex Bennée wrote:
>
> From: "Emilio G. Cota"
>
> Add the API first to ease review.
>
> Signed-off-by: Emilio G. Cota
> Signed-off-by: Alex Bennée
>
> ---
> v3
> - merge in changes to plugin install/reset/uninstall
> - split api file
> ---
> include/qemu/qe
Minor nits.
On Fri, Jun 14, 2019 at 11:41 AM Alex Bennée wrote:
>
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
> ---
> bsd-user/syscall.c | 9 +
> linux-user/syscall.c | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
Hi,
On Fri, Jun 14, 2019 at 10:21 AM Alex Bennée wrote:
>
> This is mostly extracted from Emilio's more verbose commit comments
> with some additional verbiage from me.
>
> Signed-off-by: Alex Bennée
> ---
> docs/devel/index.rst | 1 +
> docs/devel/plugins.rst | 99 ++
Ping for timely review.
On 2019/6/12 16:40, Like Xu wrote:
Multi-chip packaging technology allows integration of multi-cores in one die
and multi-dies in one single package, for example Intel CLX-AP or AMD EPYC.
This patch series extend the CPU topology to the socket/dies/core/thread model,
all
On Mon, Jun 17, 2019 at 01:55:36PM +0200, Greg Kurz wrote:
> Checking that we're not using the in-kernel XICS is ok with the "xics"
> interrupt controller mode, but it is definitely not enough with the
> other modes since the guest could be using XIVE.
>
> Ensure XIVE is not in use when emulated X
On Tue, 18 Jun 2019 at 16:55, Cédric Le Goater wrote:
>
> From: Adriana Kobylak
>
> The Swift board is an OpenPOWER system hosting POWER processors.
> Add support for their BMC including the I2C devices as found on HW.
>
> Signed-off-by: Adriana Kobylak
> Reviewed-by: Cédric Le Goater
Reviewed
On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater wrote:
>
> From: Christian Svensson
>
> If the host decrements the counter register that results in a negative
> delta. This is then passed to muldiv64 which only handles unsigned
> numbers resulting in bogus results.
>
> This fix ensures the delta b
On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater wrote:
>
> From: Andrew Jeffery
>
> From the datasheet:
>
> This register stores the current status of counter #N. When timer
> enable bit TMC30[N * b] is disabled, the reload register will be
> loaded into this counter. When timer bit TMC30[N
On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater wrote:
>
> The Aspeed SoCs have two MACs. Extend the Aspeed model to support a
> second NIC.
>
> Signed-off-by: Cédric Le Goater
> ---
> include/hw/arm/aspeed_soc.h | 3 ++-
> hw/arm/aspeed_soc.c | 33 +++--
> 2
On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater wrote:
>
> The current models of the Aspeed SoCs only have one CPU but future
> ones will support SMP. Introduce a new num_cpus field at the SoC class
> level to define the number of available CPUs per SoC and also
> introduce a 'num-cpus' property to
On Tue, 18 Jun 2019 at 16:55, Cédric Le Goater wrote:
>
> From: Andrew Jeffery
>
> The legacy interface only supported up to 32 IRQs, which became
> restrictive around the AST2400 generation. QEMU support for the SoCs
> started with the AST2400 along with an effort to reimplement and
> upstream d
On Tue, Jun 18, 2019 at 04:52:09PM +, Cosmin Marin wrote:
>
>
> On 18/06/2019, 15:51, "Peter Xu" wrote:
>
> On Tue, Jun 18, 2019 at 12:25:43PM +, Cosmin Marin wrote:
> > Hi Peter,
> >
> > thanks for reviewing the patch. Indeed, I agree that it's
> almo
On 6/17/2019 11:39 AM, Xiaoyao Li wrote:
On 6/16/2019 11:35 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load I
On Sun, May 5, 2019 at 8:34 AM Peter Maydell wrote:
>
> On Sat, 4 May 2019 at 06:26, Alistair Francis wrote:
> > Ah, it seems like -device loader doesn't work, it looks like not
> > setting the thumb register causes this core dump:
> >
> > qemu: fatal: Lockup: can't escalate 3 to HardFault (curre
Hello,
Thanks for reporting a bug.
Can you please include details to reproduce the problems that you are
seeing? This includes images and command line arguments.
Do you also mind including the diff of what fixes the problem for you?
Alistair
** Changed in: qemu
Status: New => Incomplete
This is an RFC as it will break ALL current users! See below for details.
This series consolidates the current RISC-V kernel loading
impelementation while also adding support for the -bios option and more
advanced kernel image types.
After consolidating the kernel loading we can extend the boot l
Extend the RISC-V kernel loader to support uImage and Image files.
A Linux kernel can now be booted with:
qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel Image
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 19 ++-
1 file changed, 14 insertions(+), 5 delet
If the user hasn't specified a firmware to load (with -bios) or
specified no bios (with -bios none) then load OpenSBI by default. This
allows users to boot a RISC-V kernel with just -kernel.
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 28
hw/riscv/s
Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:
qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 41 +++
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c | 69 +
hw/riscv/sifive_e.c | 17 ++
hw/riscv/sifi
On Tue, Jun 18, 2019 at 4:13 PM Aleksandar Markovic
wrote:
> I am waiting on him to send a new version of the series. Meanwhile you can
> send strace patch to the list, and I can even incude it in my series after
> and together with Aleksandar's patch, if you don't object.
I submitted it the us
On Tue, Jun 18, 2019 at 5:09 PM wrote:
> === OUTPUT BEGIN ===
> ERROR: storage class should be at the beginning of the declaration
> #25: FILE: linux-user/strace.c:979:
> +UNUSED static struct flags statx_flags[] = {
It is complaining about UNUSED, which is a macro that expands to
attribute unuse
On Tue, 2019-06-18 at 11:21 +0200, Cédric Le Goater wrote:
> On 18/06/2019 10:51, Rashmica Gupta wrote:
> > Signed-off-by: Rashmica Gupta
> > ---
> > hw/arm/aspeed_soc.c | 17 +
> > include/hw/arm/aspeed_soc.h | 3 +++
> > 2 files changed, 20 insertions(+)
> >
> > diff -
On 6/18/19 7:37 PM, Bruce Rogers wrote:
> Hi,
>
> (Resent with correct address for John)
> I build recent upstream qemu in the openSUSE Build Service, and for
> the Factory repository there, python-sphinx was recently updated to
> version 2.1.1. This caused the build to fail as follows:
> /home
Patchew URL: https://patchew.org/QEMU/20190618235313.13223-1-j...@sifive.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] linux-user: Add strace support for statx.
Type: series
Message-id: 20190618235313.13223-1
All of the flags need to be conditional as old systems don't have statx
support. Otherwise it works the same as other stat family syscalls.
This requires the pending patch to add statx support.
Tested on Ubuntu 16.04 (no host statx) and Ubuntu 19.04 (with host statx)
using a riscv32-linux toolcha
Hi,
(Resent with correct address for John)
I build recent upstream qemu in the openSUSE Build Service, and for
the Factory repository there, python-sphinx was recently updated to
version 2.1.1. This caused the build to fail as follows:
/home/abuild/rpmbuild/BUILD/qemu-4.0.50/docs/interop/bitmaps.
On Wednesday, June 19, 2019, Jim Wilson wrote:
> On 6/7/19 3:35 AM, Aleksandar Markovic wrote:
>
>> Implement support for translation of system call statx().
>>
>
> I also need these patches for 32-bit RISC-V linux user mode support.
>
> glibc ld.so calls statx if fstatat is not supported. Appar
On Sat, Jun 15, 2019 at 05:05:05PM -0300, Eduardo Habkost wrote:
> The current default value for hv-spinlocks is 0x (meaning
> "never retry"). However, the value is stored as a signed
> integer, making the getter of the hv-spinlocks QOM property
> return -1 instead of 0x.
>
> Fix
On Tue, Jun 18, 2019 at 11:07:06AM +, Roman Kagan wrote:
> X86CPU.hv-spinlocks is a uint32 property that has a special setter
> validating the value to be no less than 0xFFF and no bigger than
> UINT_MAX. The latter check is redundant; as for the former, there
> appears to be no reason to proh
Hi,
I build recent upstream qemu in the openSUSE Build Service, and for
the Factory repository there, python-sphinx was recently updated to
version 2.1.1. This caused the build to fail as follows:
/home/abuild/rpmbuild/BUILD/qemu-4.0.50/docs/interop/bitmaps.rst:202:Could not
lex literal_block as
On 6/17/2019 10:27 AM, Paolo Bonzini wrote:
On 17/06/19 13:34, Liran Alon wrote:
Putting this all together, in case kernel doesn’t support extracting
nested-state, there is no decent way to know if guest is running
nested-virtualization. Which means that in theory we always need to
fail migratio
32-bit RISC-V uses _llseek instead of lseek as syscall number 62.
Update syscall list from open-embedded build, primarily because
32-bit RISC-V requires statx support.
Tested with cross gcc testsuite runs for rv32 and rv64, with the
pending statx patch also applied.
Signed-off-by: Jim Wilson
---
On Mon, Jun 10, 2019 at 11:30 PM Gerd Hoffmann wrote:
>
> On Fri, Jun 07, 2019 at 05:03:42PM -0700, Palmer Dabbelt wrote:
> > On Thu, 06 Jun 2019 16:22:47 PDT (-0700), alistai...@gmail.com wrote:
> > > Hello,
> > >
> > > As a test of the waters, how would the QEMU community feel about
> > > includ
On 6/17/2019 10:56 AM, Liran Alon wrote:
Kernel commit 8fcc4b5923af ("kvm: nVMX: Introduce KVM_CAP_NESTED_STATE")
introduced new IOCTLs to extract and restore vCPU state related to
Intel VMX & AMD SVM.
Utilize these IOCTLs to add support for migration of VMs which are
running nested hypervisors.
On Fri, Jun 7, 2019 at 5:03 PM Palmer Dabbelt wrote:
>
> On Thu, 06 Jun 2019 16:22:47 PDT (-0700), alistai...@gmail.com wrote:
> > Hello,
> >
> > As a test of the waters, how would the QEMU community feel about
> > including the RISC-V OpenSBI project as a ROM submodule?
> >
> > The idea would be
On 6/17/2019 10:56 AM, Liran Alon wrote:
This effectively reverts d98f26073beb ("target/i386: kvm: add VMX migration
blocker").
This can now be done because previous commits added support for Intel VMX
migration.
AMD SVM migration is still blocked. This is because kernel
KVM_CAP_{GET,SET}_NEST
On 6/17/2019 10:56 AM, Liran Alon wrote:
Simiar to how kvm_init_vcpu() calls kvm_arch_init_vcpu() to perform
arch-dependent initialisation, introduce kvm_arch_destroy_vcpu()
to be called from kvm_destroy_vcpu() to perform arch-dependent
destruction.
This was added because some architectures (Suc
On 6/17/2019 10:56 AM, Liran Alon wrote:
Improve the KVM_{GET,SET}_NESTED_STATE structs by detailing the format
of VMX nested state data in a struct.
In order to avoid changing the ioctl values of
KVM_{GET,SET}_NESTED_STATE, there is a need to preserve
sizeof(struct kvm_nested_state). This is do
On 6/17/2019 10:56 AM, Liran Alon wrote:
Commit d98f26073beb ("target/i386: kvm: add VMX migration blocker")
added a migration blocker for vCPU exposed with Intel VMX.
However, migration should also be blocked for vCPU exposed with
AMD SVM.
Both cases should be blocked because QEMU should extrac
On 6/7/19 3:35 AM, Aleksandar Markovic wrote:
Implement support for translation of system call statx().
I also need these patches for 32-bit RISC-V linux user mode support.
glibc ld.so calls statx if fstatat is not supported. Apparently new
linux architecture ports aren't allowed to define _
On 6/18/19 4:02 PM, Max Reitz wrote:
> Tests should place their files into the test directory. This includes
> Unix sockets. 205 currently fails to do so, which prevents it from
> being run concurrently.
>
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/205 | 2 +-
> 1 file changed, 1 in
Tests should place their files into the test directory. This includes
Unix sockets. 205 currently fails to do so, which prevents it from
being run concurrently.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/205 | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qemu-io
Le 18/06/2019 à 21:39, Richard Henderson a écrit :
> On 6/18/19 11:44 AM, Laurent Vivier wrote:
>> Le 26/05/2019 à 09:50, Lucien Murray-Pitts a écrit :
>>> A regression that was introduced, with the refactor to TranslatorOps,
>>> drops two lines that update the PC when single-stepping is being perf
On 6/18/19 11:44 AM, Laurent Vivier wrote:
> Le 26/05/2019 à 09:50, Lucien Murray-Pitts a écrit :
>> A regression that was introduced, with the refactor to TranslatorOps,
>> drops two lines that update the PC when single-stepping is being performed.
>> ( short commit 11ab74b )
>>
>> This patch reso
Am 18.06.2019 um 16:49 hat Juan Quintela geschrieben:
> * Kevin is experimenthing with an external qemu-storage daemon
> * qemu-storage daemon vs process for each image
> * compromise: less isolation but easier to do
> * i.e. just doing the full subsystem instead of each device
This is something
Le 26/05/2019 à 09:50, Lucien Murray-Pitts a écrit :
> A regression that was introduced, with the refactor to TranslatorOps,
> drops two lines that update the PC when single-stepping is being performed.
> ( short commit 11ab74b )
>
> This patch resolves that issue.
Fixes: 11ab74b01e0a ("target/m6
We're seeing constant failures on aarch64 and arm targets on CI
on tests that have a kernel writing to a serial device used as console,
and a socket file connected to it.
After investigation, it was noticed that when interacting with some
devices, by means of the sockets around serial devices used
Patchew URL:
https://patchew.org/QEMU/20190618143923.53838-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH RESEND v21 00/21] Add RX archtecture support
Type: series
Message-id: 2019061
On 17/06/19 06:10, wangjie (P) wrote:
> Hi, I found there is a bug in pr-helper:
>
> We run pr-helper process in root, and drop all capabilities expect
> CAP_SYS_RAWIO.
>
> But the sock file which connect from qemu is owned by qemu group,
> when pr-helper exit,
>
> it will call “c
From: Andrew Jeffery
The legacy interface only supported up to 32 IRQs, which became
restrictive around the AST2400 generation. QEMU support for the SoCs
started with the AST2400 along with an effort to reimplement and
upstream drivers for Linux, so up until this point the consumers of the
QEMU A
From: Eddie James
The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations
between the SOC (acting as a BMC) and a host processor in a server.
The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so
enable it for all of those. Add trace events on the important registe
From: Adriana Kobylak
The Swift board is an OpenPOWER system hosting POWER processors.
Add support for their BMC including the I2C devices as found on HW.
Signed-off-by: Adriana Kobylak
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 50 +
1
From: Christian Svensson
This patch adds the missing checksum calculation on normal DMA transfer.
According to the datasheet this is how the SMC should behave.
Verified on AST1250 that the hardware matches the behaviour.
Signed-off-by: Christian Svensson
Reviewed-by: Joel Stanley
Signed-off-b
From: Joel Stanley
The Linux kernel driver was updated in commit 4451d3f59f2a
("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an
issue observed on hardware:
> RELOAD register is loaded into COUNT register when the aspeed timer
> is enabled, which means the next event may be
When doing calibration, the SPI clock rate in the CE0 Control Register
and the read delay cycles in the Read Timing Compensation Register are
set using bit[11:4] of the DMA Control Register.
Signed-off-by: Cédric Le Goater
Acked-by: Joel Stanley
---
hw/ssi/aspeed_smc.c | 64
The Aspeed SoCs have two MACs. Extend the Aspeed model to support a
second NIC.
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 ++-
hw/arm/aspeed_soc.c | 33 +++--
2 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/include/h
The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/ssi/aspeed_smc.h | 3 +++
hw/arm/aspeed_soc.c
The RAM memory region is defined after the SoC is realized when the
SDMC controller has checked that the defined RAM size for the machine
is correct. This is problematic for controller models requiring a link
on the RAM region, for DMA support in the SMC controller for instance.
Introduce a contai
This will simplify the definition of new SoCs, like the AST2600 which
should use a slightly different address space and have a different set
of controllers.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Joel Stanley
---
include/hw/arm/aspeed_soc.h | 4 +-
h
Emulate read errors in the DMA Checksum Register for high frequencies
and optimistic settings of the Read Timing Compensation Register. This
will help in tuning the SPI timing calibration algorithm.
The values below are those to expect from the first flash device of
the FMC controller of a palmett
From: Andrew Jeffery
If the match value exceeds reload then we don't want to include it in
calculations for the next event.
Signed-off-by: Andrew Jeffery
Signed-off-by: Cédric Le Goater
---
hw/timer/aspeed_timer.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --gi
It has never been used as far as I can tell from the git history.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
---
hw/arm/aspeed.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 96de4f5c2a87..5d73267da16f 100644
--- a/hw/arm/aspeed.c
++
From: Joel Stanley
All systems have an RTC.
The IRQ is hooked up but the model does not use it at this stage. There
is no guest code that uses it, so this limitation is acceptable.
Signed-off-by: Joel Stanley
Reviewed-by: Peter Maydell
---
include/hw/arm/aspeed_soc.h | 2 ++
hw/arm/aspeed_s
From: Andrew Jeffery
>From the datasheet:
This register stores the current status of counter #N. When timer
enable bit TMC30[N * b] is disabled, the reload register will be
loaded into this counter. When timer bit TMC30[N * b] is set, the
counter will start to decrement. CPU can update t
From: Christian Svensson
If the host decrements the counter register that results in a negative
delta. This is then passed to muldiv64 which only handles unsigned
numbers resulting in bogus results.
This fix ensures the delta being operated on is positive.
Test case: kexec a kernel using aspeed
Hello,
This series improves the current models of the Aspeed machines in QEMU
and adds new ones. It also prepares ground for the future Aspeed SoC.
You will find patches for :
- per SoC mappings of the memory space and the interrupt number space
- support for multiple CPUs (improved)
- support
From: Andrew Jeffery
First up: This is not the way the hardware behaves.
However, it helps resolve real-world problems with short periods being
used under Linux. Commit 4451d3f59f2a ("clocksource/drivers/fttmr010:
Fix set_next_event handler") in Linux fixed the timer driver to
correctly schedule
On Tue, 18 Jun 2019 at 16:59, Kevin Wolf wrote:
>
> The following changes since commit cdfaa2720f4a09e5254868bd1f6e33f3e9eae76f:
>
> Merge remote-tracking branch
> 'remotes/armbru/tags/pull-monitor-2019-06-17-v2' into staging (2019-06-18
> 10:47:00 +0100)
>
> are available in the Git repositor
From: Joel Stanley
The RTC is modeled to provide time and date functionality. It is
initialised at zero to match the hardware.
There is no modelling of the alarm functionality, which includes the IRQ
line. As there is no guest code to exercise this function that is
acceptable for now.
Signed-of
The current models of the Aspeed SoCs only have one CPU but future
ones will support SMP. Introduce a new num_cpus field at the SoC class
level to define the number of available CPUs per SoC and also
introduce a 'num-cpus' property to activate the CPUs configured for
the machine.
The max_cpus limi
On 18/06/2019, 15:51, "Peter Xu" wrote:
On Tue, Jun 18, 2019 at 12:25:43PM +, Cosmin Marin wrote:
> Hi Peter,
>
> thanks for reviewing the patch. Indeed, I agree that it's almost
impossible to determine which solution it's better from the scalability
perspective. How
This will simplify the definition of new SoCs, like the AST2600 which
should use a different CPU and a different IRQ number layout.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Joel Stanley
---
include/hw/arm/aspeed_soc.h | 36 +++
hw/arm
On Tue, 18 Jun 2019 23:39:08 +0900
Yoshinori Sato wrote:
> v21 changes
> Add cpu-param.h
> Remove CPU_COMMON
> rx_load_image move to rx-virt.
>
> Signed-off-by: Yoshinori Sato
>
> Message-Id: <20190616142836.10614-4-ys...@users.sourceforge.jp>
> Reviewed-by: Richard Henderson
> Message-Id: <2
The FMC controller on the Aspeed SoCs support DMA to access the flash
modules. It can operate in a normal mode, to copy to or from the flash
module mapping window, or in a checksum calculation mode, to evaluate
the best clock settings for reads.
The model introduces two custom address spaces for D
Patchew URL:
https://patchew.org/QEMU/20190618143923.53838-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH RESEND v21 00/21] Add RX archtecture support
Type: series
Message-id: 2019061
Alex,
I have another KVM/qemu related CPU question. I am hoping you will be so
kind as to answer again. I have a Dell Poweredge T430 server running a
single Intel Xeon E5-2603 v3 CPU with 6 cores. I have 6 VMs running CentOS
7 via KVM. I am noticing some terrible host CPU performance when a VM run
On 17/06/19 17:36, Xiaoyao Li wrote:
> MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only
> enumerates the feature split lock detection (via bit 5) by now.
>
> The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30].
>
> The latest kernel patches about them can
On 18/06/19 17:42, Dr. David Alan Gilbert wrote:
>>> Have you checked that builds OK on a non-Linux system?
>> Hmm that’s a good point. No. :P
> Worth a check if you can find one lying around :-)
It does not, but it's a macro so it's enough to enclose the uses in
#ifdef CONFIG_LINUX or CONFIG_KVM.
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