On 2024/06/23 6:54, Dmitry Osipenko wrote:
Hello,
This series enables Vulkan Venus context support on virtio-gpu.
Thanks again for keeping working on this. This series became quite a
mature. I still have comments for two patches, but they are trivial ones
so I hope it won't take much time to
On 2024/06/23 6:55, Dmitry Osipenko wrote:
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable virglrenderer 0.10 interface. Only enabled when available and
via the blob config. E.g. -device virtio-vga-gl,blob=true
Signed-off-by: Antonio Cagg
On 2024/06/23 6:55, Dmitry Osipenko wrote:
From: Robert Beckett
Support displaying blob resources by handling SET_SCANOUT_BLOB
command.
Signed-by: Antonio Caggiano
Signed-off-by: Robert Beckett
Signed-off-by: Huang Rui
Reviewed-by: Antonio Caggiano
Signed-off-by: Dmitry Osipenko
---
hw/
This patch fixes two points reported in coverity scan report [1]. Check
the MMIO access address with (addr + size), not just with the start offset
addr to make sure that the requested memory access not to exceed the
actual register region. We also updated (uint8_t *) to (uint32_t *) to
represent
util/cpuinfo-aarch64: Add OpenBSD support
Signed-off-by: Brad Smith
---
util/cpuinfo-aarch64.c | 32
1 file changed, 32 insertions(+)
diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c
index 4c8a005715..8a8c0a30a8 100644
--- a/util/cpuinfo-aarch64.c
++
util: fix building on OpenBSD/powerpc
Signed-off-by: Brad Smith
---
util/cpuinfo-ppc.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index b2d8893a06..d459c9c87e 100644
--- a/util/cpuinfo-ppc.c
+++ b/util/cpuinfo
Hello,
This series enables Vulkan Venus context support on virtio-gpu.
All virglrender and almost all Linux kernel prerequisite changes
needed by Venus are already in upstream. For kernel there is a pending
KVM patchset that fixes mapping of compound pages needed for DRM drivers
using TTM [1], ot
Replace printf's used for tracking of in-flight fence inc/dec events
with tracing, for consistency with the rest of virtio-gpu code that
uses tracing.
Suggested-by: Marc-André Lureau
Signed-off-by: Dmitry Osipenko
---
hw/display/trace-events | 2 ++
hw/display/virtio-gpu-virgl.c | 2 +-
h
From: Robert Beckett
Support displaying blob resources by handling SET_SCANOUT_BLOB
command.
Signed-by: Antonio Caggiano
Signed-off-by: Robert Beckett
Signed-off-by: Huang Rui
Reviewed-by: Antonio Caggiano
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 109
From: Pierre-Eric Pelloux-Prayer
virtio_gpu_virgl_get_num_capsets will return "num_capsets", but we can't
assume that capset_index 1 is always VIRGL2 once we'll support more capsets,
like Venus and DRM capsets. Register capsets dynamically to avoid that problem.
Reviewed-by: Manos Pitsidianakis
From: Huang Rui
Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
feature flags. Expose this feature and support creating virglrenderer
context with flags using context_id if libvirglrenderer is new enough.
Originally-by: Antonio Caggiano
Signed-off-by: Huang Rui
Reviewed-by:
New virglrerenderer features were stabilized with release of v1.0.0.
Presence of symbols in virglrenderer.h doesn't guarantee ABI compatibility
with pre-release development versions of libvirglerender. Use virglrenderer
version to decide reliably which virgl features are available.
Reviewed-by: Al
From: Huang Rui
In a preparation to adding host blobs support to virtio-gpu, add virgl
resource management that allows to retrieve resource based on its ID
and virgl resource wrapper on top of simple resource that will be contain
fields specific to virgl.
Signed-off-by: Huang Rui
Reviewed-by: A
Move fence_poll timer to VirtIOGPUGL for consistency with cmdq_resume_bh
that are used only by GL device.
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 8 +---
include/hw/virtio/virtio-gpu.h | 3 ++-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/disp
virtio_gpu_virgl_init() may fail, leading to a further Qemu crash
because Qemu assumes it never fails. Check virtio_gpu_virgl_init()
return code and don't execute virtio commands on error. Failed
virtio_gpu_virgl_init() will result in a timed out virtio commands
for a guest OS.
Signed-off-by: Dmit
Check whether command processing has been finished; otherwise, stop
processing commands and retry the command again next time. This allows
us to support asynchronous execution of non-fenced commands needed for
unmapping host blobs safely.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
Even though GL GPU doesn't support hotplugging today, free virgl
resources when GL device is unrealized. For consistency.
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-gl.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/v
From: Antonio Caggiano
Request Venus when initializing VirGL and if venus=true flag is set for
virtio-gpu-gl device.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-gl.c | 2 ++
hw/display/virtio-gpu-virgl.c | 22 +++
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable virglrenderer 0.10 interface. Only enabled when available and
via the blob config. E.g. -device virtio-vga-gl,blob=true
Signed-off-by: Antonio Caggiano
Signed-off-by: Xenia Ragiadakou
Signed
The udmabuf usage is mandatory when virgl is disabled and blobs feature
enabled in the Qemu machine configuration. If virgl and blobs are enabled,
then udmabuf requirement is optional. Since udmabuf isn't widely supported
by a popular Linux distros today, let's relax the udmabuf requirement for
blo
Move print_stats timer to VirtIOGPUGL for consistency with
cmdq_resume_bh and fence_poll that are used only by GL device.
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 10 ++
include/hw/virtio/virtio-gpu.h | 2 +-
2 files changed, 7 insertions(+), 5 deletions(-)
d
Instead of passing a bool and select a value within dcbz_common() let
the callers pass in the right value to avoid this conditional
statement. On PPC dcbz is often used to zero memory and some code uses
it a lot. This change improves the run time of a test case that copies
memory with a dcbz call i
On Tue, Jun 18, 2024 at 4:16 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/17/24 11:57, Ajeet Singh wrote:
> > From: Stacey Son
> >
> > Defined address spaces for FreeBSD/arm64 and added function for
> > getting stack pointer from CPU and setting a return value.
> >
> > Signe
On Mon, Jun 17, 2024 at 10:24 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/17/24 11:57, Ajeet Singh wrote:
> > +/*
> > + * The carry bit is cleared for no error; set for error.
> > + * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
>
On Mon, Jun 17, 2024 at 10:17 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/17/24 11:57, Ajeet Singh wrote:
> > From: Stacey Son
> >
> > Addded function to initialize ARM CPU
> > and to check if it supports 64 bit mode
> >
> > Signed-off-by: Ajeet Singh
> > Signed-off-by: St
On 6/21/24 23:15, Paolo Bonzini wrote:
This reverts commit b18236897ca15c3db1506d8edb9a191dfe51429c.
The x86-64 instruction set can now be tuned down to x86-64 v1
or i386 Pentium Pro.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 +
util/bufferiszero.c |
When a usb device is disconnected the transfer service functions bails
before appropraite transfer error flags are set.
This patch sets the appropriate condition code OHCI_CC_DEVICENOTRESPONDING
when a device is disconnected and consequently has no response on the USB bus.
Fixes: https://gitlab.co
From: David Hubbard
This changes the way the ohci emulation handles a Transfer Descriptor
with "Buffer End" set to "Current Buffer Pointer" - 1, specifically
in the case of a zero-length packet.
The OHCI spec 4.3.1.2 Table 4-2 specifies td.cbp to be zero for a
zero-length packet. Peter Maydell
The 'char' component:
* includes the no-longer-present qemu-char.c, which has been
long since split into the chardev/ backend code
* also includes the hw/char devices
Split it into two components:
* char is the hw/char devices
* chardev is the chardev backends
with regexes matching our curr
From: Sebastian Huber
Fix the system bus interrupt line to CPU core assignment.
Fixes: ddcf58e044ce0 ("hw/arm/xilinx_zynq: Support up to two CPU cores")
Signed-off-by: Sebastian Huber
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240610052906.4432-1-sebastian.hu...@embedded-brains.de
Signe
Update the 'monitor' component:
* qapi/ and monitor/ are now subdirectories
* add job-qmp.c
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240604145934.1230583-5-peter.mayd...@linaro.org
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertio
re available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240622
for you to fetch changes up to 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a:
hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine (2024-06-21
We're going to make the second UART not always a secure-only device.
Rename the constants VIRT_UART and VIRT_SECURE_UART to VIRT_UART0
and VIRT_UART1 accordingly.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240610162343.2131524-3-peter.mayd...@linaro.org
---
i
host/include/*/host/crypto/ are relatively new headers; add them
to the crypto component.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240604145934.1230583-4-peter.mayd...@linaro.org
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+)
From: "Edgar E. Iglesias"
Julien reported that he has seen strange behaviour when running
Xen on QEMU using GICv2. When Xen migrates a guest's vCPU from
one pCPU to another while the vCPU is handling an interrupt, the
guest is unable to properly deactivate interrupts.
Looking at it a little clos
For some use-cases, it is helpful to have more than one UART
available to the guest. If the second UART slot is not already used
for a TrustZone Secure-World-only UART, create it as a NonSecure UART
only when the user provides a serial backend (e.g. via a second
-serial command line option).
Thi
From: Xiong Yining
Enable CPU cluster support on SbsaQemu platform, so that users can
specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And
this topology can be passed to the firmware through /cpus/topology
Device Tree.
Signed-off-by: Xiong Yining
Reviewed-by: Marcin Juszkiewicz
If there is more than one UART in the DTB, then there is no guarantee
on which order a guest is supposed to initialise them. The standard
solution to this is "serialN" entries in the "/aliases" node of the
dtb which give the nodename of the UARTs.
At the moment we only have two UARTs in the DTB w
From: Marcin Juszkiewicz
Updated firmware for QEMU CI is already in merge queue so we can move
platform to be future proof.
All supported cpus work fine with 1GHz timer frequency when firmware is
fresh enough.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Message-id: 2024053109
From: Zheyu Ma
The Exynos4210 RNG module requires 32-bit (4-byte) accesses to its registers.
According to the User Manual Section 25.3[1], the registers for RNG operations
are 32-bit. This change ensures that the memory region operations for the
RNG module enforce the correct access sizes, preven
Since commit 83aa1baa069c we have been running the build for Coverity
Scan as a Gitlab CI job, rather than the old setup where it was run
on a local developer's machine. This is working well, but the
absolute paths of files are different for the Gitlab CI job, which
means that the regexes we use t
From: Zheyu Ma
This commit modifies the dwc2_hsotg_read() and dwc2_hsotg_write() functions
to handle invalid address access gracefully. Instead of using
g_assert_not_reached(), which causes the program to abort, the functions
now log an error message and return a default value for reads or do
not
From: Zheyu Ma
This commit updates the a9_gtimer_get_current_cpu() function to handle
cases where QTest is enabled. When QTest is used, it returns 0 instead
of dereferencing the current_cpu, which can be NULL. This prevents the
program from crashing during QTest runs.
Reproducer:
cat << EOF | qe
From: Zhenyu Zhang
Multiple warning messages and corresponding backtraces are observed when Linux
guest is booted on the host with Fujitsu CPUs. One of them is shown as below.
[0.032443] [ cut here ]
[0.032446] uart-pl011 900.pl011: ARCH_DMA_MINALIGN smaller t
Add libqmp to the testlibs component.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240604145934.1230583-6-peter.mayd...@linaro.org
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/
From: Shiva sagar Myana
Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to
become wrongly sorted when executing g_slist_sort. Fix this by always
returning -1 or 1 from g_cmp_ids based on the ID comparison instead.
Also, if two message IDs are the same, sort them by using
Expose the clock period via the QOM 'qtest-clock-period' property so it
can be used in QTests. This property is only accessible in QTests (not
via HMP).
Signed-off-by: Inès Varhol
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
docs/devel/clocks.rst | 6 ++
hw/core/clock.c
For USART, GPIO and SYSCFG devices, check that clock frequency before
and after enabling the peripheral clock in RCC is correct.
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
---
tests/qtest/stm32l4x5.h | 42 +
tests/qtest/stm32l4x5_gpio-test.c
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
corresponding clock from STM32L4x5 RCC.
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/misc/stm32l4x5_syscfg.h | 1 +
hw/arm/stm32l4x5_soc.c | 2 ++
hw
Among implemented STM32L4x5 devices, USART, GPIO and SYSCFG
have a clock source, but none has a corresponding test in QEMU.
This patch makes sure that all 3 devices create a clock correctly,
adds a QOM property to access clocks' periods from QTests,
and adds QTests checking that clock enable in RC
John Snow writes:
> On Fri, Jun 21, 2024 at 8:23 AM Markus Armbruster wrote:
[...]
>> My reason for four spaces is reducing churn. To see by how much, I
>> redid your change. I found a few more notes that don't start with a
>> capital letter, or don't end with a period.
>>
>
> ^ Guess I'll r
John Snow writes:
> On Fri, Jun 21, 2024 at 2:38 AM Markus Armbruster wrote:
[...]
>> I'd like you to express more clearly that you're talking about an
>> alternative you rejected. Perhaps like this:
>>
>> block-level constructs such as code blocks, lists, and other such
>> markup.
>>
>>
Patrick Leis writes:
> Corey and Peter,
>
> My team builds lots of configurations for Qemu boards, and one pain point
> has been that the qom path for a device depends on the device insertion
> order, child[0], child[1] and the like.
Yes.
Discussed in my "Dynamic & heterogeneous machines, initi
Hello Jonathan,
Thank you for your response.
On Sat, Jun 22, 2024 at 1:10 AM Jonathan Cameron
wrote:
>
> On Wed, 19 Jun 2024 13:54:59 +0900
> Hyeongtak Ji wrote:
>
> Hi, some description would be good of how you caught these
> (I'm guessing a close read).
Just to confirm, are you suggesting th
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