lizing the IOMMU.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
tests/qtest/libqos/riscv-iommu.h | 30
tests/qtest/riscv-iommu-test.c | 125 +++
2 files changed, 155 insertions(+)
diff --git a/tests/qtest/li
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 90
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by
40903201633.93182-1-dbarb...@ventanamicro.com/
[1]
https://lore.kernel.org/qemu-devel/CAFEAcA_8A=8q8afspwy177x6q3rlos-kohwyudhtbpojnjl...@mail.gmail.com/
[2]
https://lore.kernel.org/qemu-devel/cafeaca8rdfyacfkdjga72wa4et9nfrwroifdbtydbxy6g6u...@mail.gmail.com/
Daniel Henrique Barboza (4):
pci-id
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair
Reviewed-by: Jason Chien
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
---
include/exec/memattrs.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 14cdd8d582..e27c18f3dc 100644
--- a/include/exec/memattrs.h
+++ b
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by
: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
hw/riscv/Kconfig|4 +
hw/riscv/meson.build|1 +
hw/riscv/riscv-iommu-bits.h | 18 +
hw/riscv/riscv-iommu.c | 2018 +++
hw/riscv/riscv-iommu.h
ecome a linux-header we
would import instead of keeping our own. The Linux implementation isn't
upstream yet so for now we'll have to manage riscv-iommu-bits.h.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Jason Chi
nd
g-stage elements, although we don't support it yet. We'll introduce them
next.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
hw/riscv/riscv-iommu.c | 204 -
hw
basic tests: a PCI sanity check and a reset state register
test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2,
"Reset behavior".
More tests will be added later.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
tests
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw
ffman, and they were kind enough to give us a PCI ID for the
RISC-V IOMMU PCI reference device.
Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.
[1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
Cc: Gerd Hoffmann
Signed-off-by: Daniel Henrique Barboza
Revi
On 10/1/24 8:28 PM, Tomasz Jeznach wrote:
On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza
wrote:
On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
wrote:
On 8/20/24 12:16 PM, Jason Chien wrote:
Hi Daniel
On 10/1/24 7:24 PM, Tomasz Jeznach wrote:
On Tue, Sep 24, 2024 at 3:18 PM Alistair Francis wrote:
+
+/* IOMMU index for transactions without process_id specified. */
+#define RISCV_IOMMU_NOPROCID 0
+
+static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_type)
+{
+swi
On 10/1/24 7:14 PM, Tomasz Jeznach wrote:
On Sun, Sep 29, 2024 at 8:46 AM Peter Maydell wrote:
On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
wrote:
On 9/28/24 5:22 PM, Peter Maydell wrote:
On Tue, 24 Sept 2024 at 23:19, Alistair Francis wrote:
+/* Register helper
Paolo,
Usually we amend the existing patch with a new version instead of sending
a new patch to amend a previous patch that got comments.
I suggest you merge this change with your first patch here:
https://patchew.org/QEMU/20240717153040.11073-1-paolo.sav...@embecosm.com/20240717153040.11073-2-
On 9/30/24 9:10 AM, Ilya Leoshkevich wrote:
On Sat, 2024-09-28 at 17:40 -0300, Daniel Henrique Barboza wrote:
On 9/28/24 8:34 AM, Peter Maydell wrote:
On Tue, 24 Sept 2024 at 23:18, Alistair Francis
wrote:
The following changes since commit
01dc65a3bc262ab1bec8fe89775e9bbfa627becb
On 9/30/24 7:48 AM, Peter Maydell wrote:
On Sun, 29 Sept 2024 at 21:53, Daniel Henrique Barboza
wrote:
On 9/29/24 12:38 PM, Peter Maydell wrote:
On Sat, 28 Sept 2024 at 21:40, Daniel Henrique Barboza
wrote:
On 9/28/24 8:34 AM, Peter Maydell wrote:
The assertion failure is
ERROR
On 9/29/24 12:38 PM, Peter Maydell wrote:
On Sat, 28 Sept 2024 at 21:40, Daniel Henrique Barboza
wrote:
On 9/28/24 8:34 AM, Peter Maydell wrote:
The assertion failure is
ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset: assertion
failed (cap & RISCV_IOMMU_CAP_VERSION ==
the next patches.
Co-developed-by: Sebastien Boeuf
Signed-off-by: Sebastien Boeuf
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Message-ID: <20240903201633.93182-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
meson
On 9/28/24 8:34 AM, Peter Maydell wrote:
On Tue, 24 Sept 2024 at 23:18, Alistair Francis wrote:
The following changes since commit 01dc65a3bc262ab1bec8fe89775e9bbfa627becb:
Merge tag 'pull-target-arm-20240919' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-19
On 9/19/24 2:50 AM, LIU Zhiwei wrote:
make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
TuxRunBaselineTest:test_riscv64_rv32
Signed-off-by: LIU Zhiwei
Suggested-by: Daniel Henrique Barboza
---
Reviewed-by: Daniel Henrique Barboza
tests/avocado/tuxrun_baselines.py
where addw instruction doesn't exist in
RV32 CPU.
Signed-off-by: LIU Zhiwei
Suggested-by: Daniel Henrique Barboza
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 12 +++-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --gi
On 9/26/24 4:59 AM, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
Reviewed-by: Daniel Henrique Barboza
MAINTAINERS | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ffacd60f40..0a191a03db 100644
--- a/MAINTAINERS
due to DT validation failures.
Signed-off-by: Andrew Jones
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cef41c150aaf..4fd9c0edf038 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt
On 9/19/24 9:22 AM, Daniel P. Berrangé wrote:
On Thu, Sep 19, 2024 at 08:20:56AM -0300, Daniel Henrique Barboza wrote:
Add a QMP command that shows all specific properties of the current
accelerator in use.
Why do we need to expose /everything/ ?
I wouldn't mind pick and c
iscv-aia was set to the default or uset-set value.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 970a7ab2f1..32f3dd6a43 100644
bool is set we'll default
to riscv-aia-auto, if the host supports it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 77 ++
1 file changed, 77 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-c
We want to use the new boolean properties instead: riscv-aia-emul,
riscv-aia-hwaccel and riscv-aia-auto.
Mark the string prop 'riscv-aia' for deprecation.
Signed-off-by: Daniel Henrique Barboza
---
docs/about/deprecated.rst | 8
target/riscv/kvm/kvm-cpu.c | 1 +
2 files
KVM AIA: failed to set KVM AIA mode
We can use a single warning message:
qemu-system-riscv64: warning: KVM AIA: failed to set KVM AIA mode 'auto', using
default host mode 'emul'
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 22 +++---
l and auto).
We're also deprecating the existing 'riscv-aia' string option.
The idea is to use the new properties to enable AIA support in libvirt.
Patches based on riscv-to-apply.next.
Daniel Henrique Barboza (4):
target/riscv/kvm: set 'aia_mode' to default in error pa
On 9/21/24 12:56 PM, 0x48 Swung wrote:
Signed-off-by: Huang Shiyuan mailto:swung0...@outlook.com>>
This is the tag. Is this fine or do I need to do something else? Thanks for the
help from everybody in this list!
Thanks! This is enough. Zhiwei can add the tag in the patch in v5.
Daniel
On 9/12/24 5:48 AM, Clément Léger wrote:
This variable is used to determine if the Smdbltrp extension is enabled.
Signed-off-by: Clément Léger
---
Similar with patch 1, I would also merge this with patch 07 since the bool is
being used there. Thanks,
Daniel
target/riscv/cpu_cfg.h | 1
On 9/12/24 5:48 AM, Clément Léger wrote:
This variable is used to determine if the Ssdbltrp extension is enabled.
Signed-off-by: Clément Léger
---
I would merge this to patch 2 since the bool is being used there. Thanks,
Daniel
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 inserti
Hi Zhiwei,
On 9/11/24 10:26 AM, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each group while
reserving the other re
x-frames": 64, "device": "", "xen-version": 0, "mem-smram[0]":
"", "notify-window": 0, "dirty-ring-size": 0, "kvm-shadow-mem": -1, "type":
"kvm-accel", "notify-vmexit": "run"
On 9/16/24 12:51 PM, Ajeet Singh wrote:
Key Changes Compared to Version 6:
Included "signal-common.h" in target_arch_cpu.h
Thanks. This version is successfully compiling in a FreeBSD x86 host.
Daniel
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd
Hi,
Please CC the RISC-V maintainer (Alistair, that I just CCed in this reply) in
all RISC-V
related patches. It would be nice to also CC qemu-ri...@nongnu.org to get more
visibility
from the RISC-V developers too.
This series won't build in a FreeBSD x86_64 host:
In file included from ../bs
On 9/16/24 3:12 AM, Thomas Huth wrote:
On 15/09/2024 21.58, Daniel Henrique Barboza wrote:
Hi Peter, Alistair,
On 9/14/24 6:15 AM, Alistair Francis wrote:
On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell wrote:
On Thu, 12 Sept 2024 at 06:30, Alistair Francis wrote:
The following changes
Hi Peter, Alistair,
On 9/14/24 6:15 AM, Alistair Francis wrote:
On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell wrote:
On Thu, 12 Sept 2024 at 06:30, Alistair Francis wrote:
The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
Merge tag 'pull-testing-gdbstub-oct-1
On 9/12/24 2:29 AM, Alistair Francis wrote:
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240907031927.1
On 9/12/24 2:29 AM, Alistair Francis wrote:
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers
\
+g_assert_not_reached();
\
} \
\
if (unlikely((exp < 0) || (exp > max_exp))) { \
Otherwise,
Reviewed-by: Daniel Henrique Barboza
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b0a0676beba..b167b37e0ab 100
On 9/10/24 7:15 PM, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/spapr_events.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index cb05874..38ac1cb7866
On 9/10/24 7:16 PM, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/monitor.c | 1 -
target/riscv/insn_trans/trans_rvv.c.inc | 2 --
2 files changed, 3 deletions(-)
diff --git a/target/riscv/monitor.c b
o the guest with
the SIFIVE_UART_TXFIFO_FULL status.
This should avoid dropped characters and more realisticly model the
hardware.
1: https://gitlab.com/qemu-project/qemu/-/issues/2114
Signed-off-by: Alistair Francis
Tested-by: Thomas Huth
Reviewed-by: Daniel Henrique Barboza
---
include/hw
On 9/9/24 12:17 AM, Andrew.Yuan wrote:
The code 'ops = ACCEL_OPS_CLASS(module_object_class_by_name(ops_name));' is
unnecessary;
And, the following code :
1.has the same functionality;
2.includes error checking;
Signed-off-by: Andrew.Yuan
---
accel/accel-system.c | 2 +-
1 file changed,
On 9/3/24 3:17 AM, Fea.Wang wrote:
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLV
On 9/2/24 7:34 AM, Maria Klauchek wrote:
FCSR is a part of F extension. Print it to log if FPU option is enabled.
Signed-off-by: Maria Klauchek
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b
On 9/3/24 5:31 PM, Richard Henderson wrote:
On 9/3/24 13:16, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair
Reviewed-by: Jason Chien
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
---
include/exec/memattrs.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 14cdd8d582..e27c18f3dc 100644
--- a/include/exec/memattrs.h
+++ b
nd
g-stage elements, although we don't support it yet. We'll introduce them
next.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
hw/riscv/riscv-iommu.c | 205 -
hw
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by
ecome a linux-header we
would import instead of keeping our own. The Linux implementation isn't
upstream yet so for now we'll have to manage riscv-iommu-bits.h.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Jason Chi
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 90
ffman, and they were kind enough to give us a PCI ID for the
RISC-V IOMMU PCI reference device.
Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.
[1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
Cc: Gerd Hoffmann
Signed-off-by: Daniel Henrique Barboza
Revi
lizing the IOMMU.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
tests/qtest/libqos/riscv-iommu.h | 30
tests/qtest/riscv-iommu-test.c | 127 +++
2 files changed, 157 insertions(+)
diff --git a/tests/qtest/li
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw
basic tests: a PCI sanity check and a reset state register
test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2,
"Reset behavior".
More tests will be added later.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
tests
1009852-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (4):
pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
test/qtest: add riscv-iommu-pci tests
qtest/riscv-iommu-test: add init queues test
docs/specs: add riscv-iommu
Tomasz Jeznach (8):
exec/memtxattr: add process id
: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
hw/riscv/Kconfig|4 +
hw/riscv/meson.build|1 +
hw/riscv/riscv-iommu-bits.h | 18 +
hw/riscv/riscv-iommu.c | 2050 +++
hw/riscv/riscv-iommu.h
On 8/1/24 12:43 PM, Daniel Henrique Barboza wrote:
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
---
docs/specs/index.rst | 1 +
docs/specs
On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
wrote:
On 8/20/24 12:16 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as
On 8/26/24 11:44 PM, Tomasz Jeznach wrote:
On Fri, Aug 23, 2024 at 10:18 AM Daniel Henrique Barboza
wrote:
On 8/20/24 12:27 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can
phic -M virt -cpu
rv64,zfinx=true,f=false,zfa=false,d=false
(OpenSBI boots ...)
[1] https://gitlab.com/qemu-project/qemu/-/issues/2486
Cc: Frank Chang
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2486
Fixes: 047da861f9 ("target/riscv: Introduce extension implied rule helpers")
S
elete it. Anybody needing to know the API and
protocol for the guest to communicate with the hypervisor
to created nested VMs should refer to the authoratitative
documentation in the kernel docs.
Signed-off-by: Peter Maydell
---
Reviewed-by: Daniel Henrique Barboza
I'm going through
eviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a90808a3bace..07a7af59b6d9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -115,7 +115,7 @@ const RISCV
/pull/9748
Signed-off-by: Alistair Francis
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a90808a3ba..7e13fb2c0f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -
On 8/20/24 12:27 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are
On 8/20/24 12:16 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv
On 8/5/24 6:04 PM, Gregor Haas wrote:
This patch series adds support for specifying OpenSBI domains on the QEMU
command line. A simple example of what this looks like is below, including
mapping the board's UART into the secondary domain:
qemu-system-riscv64 -machine virt -bios fw_jump.bin -c
iners, identifies all domains and
memregions, and parses them into the relevant device tree structures.
[1]
https://github.com/riscv-software-src/opensbi/blob/master/docs/domain_support.md
Signed-off-by: Gregor Haas
---
Reviewed-by: Daniel Henrique Barboza
MAINTA
one to the result. Do the same for the group bit setting.
Signed-off-by: Andrew Jones
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/kvm/kvm-cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index
On 8/17/24 8:34 AM, Andrew Jones wrote:
On Thu, Aug 01, 2024 at 12:43:24PM GMT, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com
tps://lore.kernel.org/all/20240816124957.130017-2-ajo...@ventanamicro.com/ # 1
Signed-off-by: Andrew Jones
---
Reviewed-by: Daniel Henrique Barboza
This is indeed a 9.1 fix. Thanks Drew for sending it.
We can discuss whether we should wrap this around the 'strict-dt' flag or not,
but
to do that.
Instead let's just use qemu_chr_fe_write_all() so at least we don't drop
charecters.
1: https://gitlab.com/qemu-project/qemu/-/issues/2114
Signed-off-by: Alistair Francis
---
Reviewed-by: Daniel Henrique Barboza
hw/char/riscv_htif.c | 12 ++--
1 file changed,
Ccing Anup
On 8/8/24 5:20 AM, Yong-Xuan Wang wrote:
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit
On 7/31/24 3:30 AM, Markus Armbruster wrote:
I apologize for the delay.
Daniel Henrique Barboza writes:
We're not honouring KVM options that are provided by any -accel option
aside from the first. In this example:
qemu-system-riscv64 -accel kvm,riscv-aia=emul (...) \
-acce
On 8/6/24 5:46 AM, Andrew Jones wrote:
On Tue, Jul 23, 2024 at 04:30:10PM GMT, Atish Patra wrote:
Counter delegation/configuration extension requires the following
extensions to be enabled.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSR
On 8/4/24 8:04 PM, Alistair Francis wrote:
On Fri, Aug 2, 2024 at 1:45 AM Daniel Henrique Barboza
wrote:
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One
: sbi: fwft: fix incorrect size passed to sbi_zalloc()
> lib: sbi: dbtr: fix potential NULL pointer dereferences
> include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
> lib: sbi_hsm: Save/restore menvcfg only when it exists
Signed-off-by: Daniel Henrique Barboza
---
.../ope
ng the bug fix
freeze.
Alistair, the patch was created with --no-binary as you suggested in the
last OpenSBI update I sent. Please fetch both binaries from:
https://gitlab.com/danielhb/qemu/-/commits/opensbi1.5.1
Daniel Henrique Barboza (1):
roms/opensbi: Update to v1.5.1
.../opensbi-riscv
On 7/26/24 3:43 PM, Gregor Haas wrote:
OpenSBI has support for domains, which are partitions of CPUs and memory into
isolated compartments. Domains can be specified in the device tree according to
a standardized format [1], which OpenSBI parses at boot time to initialize all
system domains. Th
basic tests: a PCI sanity check and a reset state register
test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2,
"Reset behavior".
More tests will be added later.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
tests
: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/Kconfig|4 +
hw/riscv/meson.build|1 +
hw/riscv/riscv-iommu-bits.h | 14 +
hw/riscv/riscv-iommu.c | 2017 +++
hw/riscv/riscv-iommu.h | 148 +++
hw/riscv/trace
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by
nd
g-stage elements, although we don't support it yet. We'll introduce them
next.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
hw/riscv/riscv-iommu.c | 199 -
hw
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 80
lizing the IOMMU.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
---
tests/qtest/libqos/riscv-iommu.h | 29 +++
tests/qtest/riscv-iommu-test.c | 141 +++
2 files changed, 170 insertions(+)
diff --git a/tests/qtest/li
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
---
hw/riscv/riscv
ecome a linux-header we
would import instead of keeping our own. The Linux implementation isn't
upstream yet so for now we'll have to manage riscv-iommu-bits.h.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Jason Chien
---
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw
Reviewed-by: Jason Chien
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
---
include/exec/memattrs.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 14cdd8d582..e27c18f3dc 100644
--- a/include/exec/memattrs.h
+++ b
all MSIX vector usage based on the current CIV, FIV,
PMIV and PIV values
- patch 12 (former 13):
- added more details on what to expect when adding a riscv-iommu-pci
device in the 'virt' machine
- v5 link:
https://lore.kernel.org/qemu-riscv/20240708173501.426225-1-dbarb...@v
ffman, and they were kind enough to give us a PCI ID for the
RISC-V IOMMU PCI reference device.
Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.
[1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
Cc: Gerd Hoffmann
Signed-off-by: Daniel Henrique Barboza
Revi
On 7/19/24 6:34 AM, Alistair Francis wrote:
On Tue, Jul 9, 2024 at 3:37 AM Daniel Henrique Barboza
wrote:
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
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