Jonathan Cameron wrote:
> On Tue, 27 Aug 2024 09:40:05 -0700
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > When inserting multiple dynamic capacity event records grouped via More
> > flag,
> > we should only trigger interrupt after the last record is inserted into the
> > event log. A
Peter Maydell wrote:
> Ping! This looks like it should be an easy one-liner fix
> for a Coverity-detected read-from-bogus-memory bug --
> could one of the CXL folks have a look at it and send
> a patch, please ?
Done. Jonathan could you double check I only compile tested.
I think you are correct
Link:
https://lore.kernel.org/all/cafeaca-u4sytgwtksb__y+_+0o2-wwarntm3x8wnhvl1wfh...@mail.gmail.com/
Fixes: 6bda41a69bdc ("hw/cxl: Add clear poison mailbox command support.")
Cc: Jonathan Cameron
Signed-off-by: Ira Weiny
---
Compile tested only. Jonathan please double check me.
---
Markus Armbruster wrote:
> fan writes:
>
> > On Wed, Apr 24, 2024 at 03:09:52PM +0200, Markus Armbruster wrote:
> >> nifan@gmail.com writes:
> >>
> >> > From: Fan Ni
> >> >
> >> > Since fabric manager emulation is not supported yet, the change
> >> > implements
> >> > the functions to add/
Shiyang Ruan wrote:
>
>
> 在 2024/4/24 5:04, Ira Weiny 写道:
> > Alison Schofield wrote:
> >> On Wed, Apr 17, 2024 at 03:50:52PM +0800, Shiyang Ruan wrote:
> >
> > [snip]
> >
> >>> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core
Markus Armbruster wrote:
> nifan@gmail.com writes:
>
> > From: Fan Ni
> >
> > Since fabric manager emulation is not supported yet, the change implements
> > the functions to add/release dynamic capacity extents as QMP interfaces.
>
> Will fabric manager emulation obsolete these commands?
I
Alison Schofield wrote:
> On Wed, Apr 17, 2024 at 03:50:52PM +0800, Shiyang Ruan wrote:
[snip]
> > diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
> > index e5f13260fc52..cdfce932d5b1 100644
> > --- a/drivers/cxl/core/trace.h
> > +++ b/drivers/cxl/core/trace.h
> > @@ -253,7 +253,
Shiyang Ruan wrote:
> Currently driver only traces cxl events, poison creation (for both vmem
> and pmem type) on cxl memdev is silent. OS needs to be notified then it
> could handle poison pages in time. Per CXL spec, the device error event
> could be signaled through FW-First and OS-First metho
Media Event Record")
> Cc:
> Cc: Dan Williams
> Cc: Davidlohr Bueso
> Cc: Jonathan Cameron
> Cc: Ira Weiny
Apologies I thought I saw this go in before. But perhaps it was a
different mask.
Reviewed-by: Ira Weiny
> Signed-off-by: Shiyang Ruan
> ---
> d
so be an unsigned 64-bit type,
> even if the input to the macro is a smaller type, and so the shifts
> will be in range.
>
> Fixes: 845d80a8c7b187 ("qemu/bswap: Add const_le64()")
> Signed-off-by: Peter Maydell
Thanks!
Reviewed-by: Ira Weiny
nifan.cxl@ wrote:
> From: Fan Ni
>
>
> The patch series are based on Jonathan's branch cxl-2023-09-26.
Finally getting around to trying this new series and the patch series does not
seem to apply on top of this branch?
Just to verify is this the top commit this work was based on?
d4edf131b
7;t have let more gpl-2-only code into the
> > codebase without a rationale...)
I'm curious about this statement. Does the qemu project not want gpl v2
only code? I agree with Jonathan that this is the intention of Ben's
initial submission; so from that PoV.
Acked-by: Ira Weiny
G
Fan Ni wrote:
> On Thu, May 11, 2023 at 05:56:40PM +, Fan Ni wrote:
>
> FYI.
>
> I have updated the patch series and sent out again.
>
> I suggested anyone who are interested in DCD and using this patch series to
> use the new series. Quite a few things has been fixed.
>
> https://lore.kern
nifan@ wrote:
> From: Fan Ni
>
> The patch series provides dynamic capacity device (DCD) emulation in Qemu.
> More specifically, it provides the following functionalities:
> 1. Extended type3 memory device to support DC regions and extents.
> 2. Implemented DCD related mailbox command support in
nifan@ wrote:
> From: Fan Ni
>
> The patch series provides dynamic capacity device (DCD) emulation in Qemu.
I don't the patches on the list.
https://lore.kernel.org/all/sg2pr06mb33976bb3f9c47cbe08f02d09b2...@sg2pr06mb3397.apcprd06.prod.outlook.com/
Did they get sent?
Ira
> More specifically,
ni...@outlook.com wrote:
> The 06/08/2023 08:43, Ira Weiny wrote:
> > Shesha Bhushan Sreenivasamurthy wrote:
[snip]
>
> Hi Ira & Shesha,
> FYI. I reabased my patch series on top of the above branch and created a new
> branch here:
>
> https://github.com/moking/q
Shesha Bhushan Sreenivasamurthy wrote:
> Hi Fan,
>I am implementing DCD FMAPI commands and planning to start pushing changes
> to the below branch. That requires the contributions you have made. Can your
> changes be pushed to the below branch ?
>
> https://gitlab.com/jic23/qemu/-/tree/cxl-2
Fan Ni wrote:
> Since the early draft of DCD support in kernel is out
> (https://lore.kernel.org/linux-cxl/20230417164126.GA1904906@bgt-140510-bm03/T/#t),
> this patch series provide dcd emulation in qemu so people who are interested
> can have an early try. It is noted that the patch series may ne
Fan Ni wrote:
> The 05/22/2023 16:09, Jonathan Cameron wrote:
> > From: Ira Weiny
> >
> > CXL testing is benefited from an artificial event log injection
> > mechanism.
> >
> > Add an event log infrastructure to insert, get, and clear events from
>
Jonathan Cameron wrote:
> On Thu, 18 May 2023 13:19:12 -0700
> Ira Weiny wrote:
>
> > Jonathan Cameron wrote:
> > > On Wed, 17 May 2023 19:45:54 -0700
> > > Ira Weiny wrote:
> > >
> > > > Magic numbers can be confusing.
> > > &g
"transaction-type": 192,
> > > "channel": 3,
> > > "rank": 17,
> > > "nibble-mask": 37421234,
> > > "bank-group": 7,
> > > "bank": 11,
>
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Reviewed-by: Fan Ni
Minor nit below. Otherwise looks good.
Reviewed-by: Ira Weiny
> diff --git a/hw/mem/cxl_type3.c b/h
Jonathan Cameron wrote:
> On Wed, 17 May 2023 19:45:54 -0700
> Ira Weiny wrote:
>
> > Magic numbers can be confusing.
> >
> > Use the range size define for CXL.cachemem rather than a magic number.
> > Update/add spec references.
> >
> > Signed-o
ned-off-by: Ira Weiny
---
The device ID and class code are completely made up by me. As discussed
in the last community call perhaps these could be declared in some more
official capacity?
---
docs/system/devices/cxl.rst | 11 +++
hw/mem/cxl_type3.c
The presence of the Back-Invalidate (BI) decoder capability structure
indicates a CXL downstream port, root port, or device supports the BI
messages.
Add the BI capability structure to the accelerator device.
Not-Yet-Signed-off-by: Ira Weiny
---
hw/cxl/cxl-component-utils.c | 5 +
hw
vices to
support UIO for testing.
Not-Yet-Signed-off-by: Ira Weiny
---
hw/cxl/cxl-component-utils.c | 6 ++
include/hw/cxl/cxl_component.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index a9efa252b4ae..252b2beb2110 1
Magic numbers can be confusing.
Use the range size define for CXL.cachemem rather than a magic number.
Update/add spec references.
Signed-off-by: Ira Weiny
---
include/hw/cxl/cxl_component.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/hw/cxl
fined by a device type. Any capability which is not specified by the
type is left NULL'ed out which complies with the packed nature of the
register array.
Update all spec references to 3.0.
No functional changes should be seen with this patch.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-co
memdev=cxl-ac-mem5,id=cxl-dev5,sn=0xCAFE0005
...
NOTE: I'm leaving off Michael Tsirkin for now because this is really
rough and I'm mainly sending it out because it was talked about in the
CXL community call on 5/16.
Not-Yet-Signed-off-by: Ira Weiny
---
Ira Weiny (5):
hw/cxl: Use
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
One coding style change at the bottom and I'm still hung up on that loop
logic...
>
> Signed-off-by: Jonathan Cameron
> ---
> v4:
> - Fix off
n your machine.
>
> Note that the poison list supported is kept short enough to avoid the
> complexity of state machine that is needed to handle the MORE flag.
>
Reviewed-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
> ---
> v4:
> - Widen the mask on Poison source (lower bits of the address)
>to allow for Vendor Defined. Change will make it easier to potentially
>add a means to inject such poison in the future. Today it has no
>impact.
[...]
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
> v2:
> - Endian fix
> ---
> hw/cxl/cxl-mailbox-utils.c | 79 +
>
s of the kernel code.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Ira Weiny
Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
>
> Ker
ce the usefulness of this more basic generation of the events.
Seems very reasonable to me.
One spelling issue below. With that.
Reviewed-by: Ira Weiny
>
> Signed-off-by: Jonathan Cameron
> ---
> hw/mem/cxl_type3.c | 61 +
> hw/mem/cxl
;
> +cxlds = &ct3d->cxl_dstate;
> +
> +rc = ct3d_qmp_cxl_event_log_enc(log);
> +if (rc < 0) {
> +error_setg(errp, "Unhandled error log type");
> +return;
> +}
> +enc_log = rc;
> +
> +memset(&d
mment as 1/6 but still.
Reviewed-by: Ira Weiny
>
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 62 ++---
> include/hw/cxl/cxl_device.h | 2 +-
> 2 files changed, 32 insertions(+), 32 deletions(-)
>
k this is a good clarification.
Reviewed-by: Ira Weiny
>
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 28
> include/hw/cxl/cxl_device.h | 28
> 2 files changed, 28 insertions(+), 28 deletions(-)
>
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 77 +
> hw/mem/cxl_type3.c
Jonathan Cameron wrote:
> Very simple implementation to allow testing of corresponding
> kernel code. Note that for now we track each 64 byte section
> independently. Whilst a valid implementation choice, it may
> make sense to fuse entries so as to prove out more complex
> corners of the kernel c
Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
>
> Ker
Jonathan Cameron wrote:
> On Wed, 25 Jan 2023 21:37:27 -0800
> Ira Weiny wrote:
>
> > CXL 3.0 8.2.9.4.2 Set Timestamp and 8.2.9.4.1 Get Timestamp define the
> > way for software to set and get the time stamp of a device. Events
> > should use a time stamp consis
overs the protocol
> related errors reported via PCIE AER - Ira Weiny has posted support for
> Event log based injection and I will post an update of Poison list injection
> shortly. My proposal is to upstream this one first, followed by Ira's Event
> Log series, then finally the Poi
w/cxl/events: Wire up get/clear event mailbox commands")
Reported-by: Jonathan Cameron
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-device-utils.c | 15 +++
hw/cxl/cxl-events.c | 4 +++-
hw/cxl/cxl-mailbox-utils.c | 11 +--
hw/mem/cxl_type3.c | 1 -
incl
https://lore.kernel.org/all/20221221-ira-cxl-events-2022-11-17-v2-0-2ce2ecc06...@intel.com/
To: Jonathan Cameron
Cc: Michael Tsirkin
Cc: Ben Widawsky
Cc: Peter Maydell
Cc:
Cc:
Signed-off-by: Ira Weiny
---
Ira Weiny (2):
hw/cxl: Fix event log time stamp fields
hw/cxl: Remove check for g
g_new0() will terminate the application if it fails. Remove the check.
Fixes: fb64c5661d5f ("hw/cxl/events: Wire up get/clear event mailbox commands")
Reported-by: Jonathan Cameron
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-events.c | 6 --
1 file changed, 6 deletions(-)
diff --gi
On Wed, Jan 11, 2023 at 02:24:37PM +, Jonathan Cameron wrote:
> Noticed as this prevents iASL disasembling the DSDT table.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Ira Weiny
> ---
> hw/i386/acpi-build.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --gi
On Wed, Jan 11, 2023 at 02:24:35PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> Current code sets to STORAGE_EXPRESS and then overrides it.
>
> Signed-off-by: Gregory Price
> Reviewed-by: Davidlohr Bueso
Reviewed-by: Ira Weiny
> Signed-off-by: Jonathan Cam
On Wed, Jan 11, 2023 at 02:24:34PM +, Jonathan Cameron wrote:
> Fix capitalization difference between struct name and typedef.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Ira Weiny
> ---
> hw/pci-bridge/cxl_downstream.c | 2 +-
> 1 file changed, 1 insert
On Wed, Jan 11, 2023 at 02:24:33PM +, Jonathan Cameron wrote:
> msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Ira Weiny
> ---
> hw/mem/cxl_type3.c | 12 ++--
> 1 file changed, 1
On Tue, Jan 03, 2023 at 06:07:19PM +, Jonathan Cameron wrote:
> On Wed, 21 Dec 2022 20:24:38 -0800
> Ira Weiny wrote:
>
> > To facilitate testing provide a QMP command to inject a general media
> > event. The event can be added to the log specified.
> >
&
To facilitate testing provide a QMP command to inject a general media
event. The event can be added to the log specified.
Signed-off-by: Ira Weiny
---
Changes from RFC:
Add all fields for this event
irq happens automatically when log transitions from 0 to 1
---
hw/mem
00 descriptor=127 type=3 transactiontype=192
\
channel=3 rank=-1 device=5 componentid='Iras mem'" |
$qmpcmd
View events on the guest:
$ cat /sys/kernel/tracing/trace
To: Jonathan Cameron
Cc: Michael Tsirkin
Cc: Ben Widawsky
Cc: Ira Weiny
Cc: qemu-devel@nongnu
3.0 the version of the device status register block needs
to be 2. Change the macro to allow for setting the version.
Signed-off-by: Ira Weiny
---
Changes from RFC:
New patch to cover this register which was not being used
before.
---
hw/cxl/cxl-device-utils.c | 50
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
commands. Enable those commands to control interrupts for each of the
event log types.
Skip the standard input mailbox length on the Set command due to DCD
being optional. Perform the checks separately.
Signed-off-by: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Reviewed-by: Jonathan Cameron
Reviewed-by: Peter Maydell
Signed-off-by: Ira Weiny
---
Changes from RFC:
Peter
Change order of the definitions, 64-32-16
---
include/qemu/bswap.h | 10
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Reviewed-by: Jonathan Cameron
Signed-off-by: Ira Weiny
---
include/qemu/uuid.h | 12
1 file c
infrastructure.
Signed-off-by: Ira Weiny
---
Change from RFC:
Process multiple records per Get/Set per the spec
Rework all the calls to be within events.c
Add locking around the event logs to ensure that the log
integrity is maintained
---
hw/cxl/cxl-events.c
The cel_uuid was programatically generated previously because there was
no static initializer for network order UUIDs.
Use the new network order initializer for cel_uuid. Adjust
cxl_initialize_mailbox() because it can't fail now.
Update specification reference.
Signed-off-by: Ira
ze part of the function name.
Signed-off-by: Ira Weiny
---
include/qemu/bswap.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index e1eca22f2548..8af4d4a75eb6 100644
--- a/include/qemu/bswap.h
+++ b/include/qe
On Mon, Dec 19, 2022 at 10:07:23AM +, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:41 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > To facilitate testing of guest software add mock events and code to
> > support iterating through th
On Thu, Dec 15, 2022 at 05:16:33PM +, Jonathan Cameron wrote:
> On Wed, 14 Dec 2022 12:54:11 -0800
> Ira Weiny wrote:
>
> > The Flex Bus Port DVSEC was missing on type 3 devices which was blocking
> > RAS checks.[1]
> >
> > Add the Flex Bus Port DVSEC
: Jonathan Cameron
Cc: Ben Widawsky
Cc: qemu-devel@nongnu.org
Cc: linux-...@vger.kernel.org
Signed-off-by: Ira Weiny
---
Changes in v2:
Jonathan
type 3 device does not support CACHE
: Jonathan Cameron
Cc: Ben Widawsky
Cc: qemu-devel@nongnu.org
Cc: linux-...@vger.kernel.org
Signed-off-by: Ira Weiny
---
hw/mem/cxl_type3.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 0317bd96a6fb..27f6ac0cb3c1 100644
--- a/hw/mem
On Mon, Nov 07, 2022 at 10:09:23AM -0800, Davidlohr Bueso wrote:
> Found while reading the doc.
>
> Signed-off-by: Davidlohr Bueso
Reviewed-by: Ira Weiny
> ---
> docs/system/devices/cxl.rst | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
>
use I never ran with the
CONFIG_DEBUG_OBJECTS_WORK option.
While we could have a declaration macro. I think the best solution is to
separate the task from the internal implementation; see patch below. I was
never fully happy with the idea of having the work struct in the user visible
task object a
On Tue, Oct 11, 2022 at 11:07:59AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:41 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > To facilitate testing of guest software add mock events and code to
> > support iterating through th
On Tue, Oct 11, 2022 at 10:13:17AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:40 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > UUID's are defined as network byte order fields. No static initializer
> > was available f
On Tue, Oct 11, 2022 at 10:03:00AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:39 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > Gcc requires constant versions of cpu_to_le* calls.
> >
> > Add a 64 bit version.
> &
On Tue, Oct 11, 2022 at 04:45:57PM +0100, Peter Maydell wrote:
> On Tue, 11 Oct 2022 at 16:22, Richard Henderson
> wrote:
> > On 10/11/22 02:48, Peter Maydell wrote:
> > > This is kind of a weird API, because:
> > > * it only exists for little-endian, not big-endian
> > > * we use it in exactl
On Tue, Oct 11, 2022 at 10:40:06AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:38 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > CXL Event records inform the OS of various CXL device events. Thus far CXL
> > memory devices
On Mon, Oct 10, 2022 at 03:29:38PM -0700, Ira wrote:
> From: Ira Weiny
>
> CXL Event records inform the OS of various CXL device events. Thus far CXL
> memory devices are emulated and therefore don't naturally have events which
> will occur.
>
> Add mock events and
From: Ira Weiny
CXL Event records inform the OS of various CXL device events. Thus far CXL
memory devices are emulated and therefore don't naturally have events which
will occur.
Add mock events and a HMP trigger mechanism to facilitate guest OS testing of
event support.
This support req
From: Ira Weiny
Replace the stubbed out CXL Get/Clear Event mailbox commands with
commands which return the mock event information.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-device-utils.c | 1 +
hw/cxl/cxl-mailbox-utils.c | 103 +++--
2 files changed, 101
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Signed-off-by: Ira Weiny
---
include/qemu/uuid.h | 12
1 file changed, 12
From: Ira Weiny
To facilitate testing of guest software add mock events and code to
support iterating through the event logs.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-events.c | 248
hw/cxl/meson.build | 1 +
include/hw/cxl/cxl_device.h
From: Ira Weiny
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
commands. Enable those commands to control interrupts for each of the
event log types.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-mailbox-utils.c | 129 ++--
include/hw/cxl
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Signed-off-by: Ira Weiny
---
include/qemu/bswap.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index 346d05f2aab3..08e607821102 100644
From: Ira Weiny
To facilitate testing of event interrupt support add a QMP HMP command
to reset the event logs and issue interrupts when the guest has enabled
those interrupts.
Signed-off-by: Ira Weiny
---
hmp-commands.hx | 14 +++
hw/cxl/cxl-events.c | 82
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