> When I developped the FPU emulation I compared the result of QEMU and a real
> hardware using
> https://github.com/vivier/m68k-testfloat and
> https://github.com/vivier/m68k-softfloat
It looks like the second of those has similar issues with m68k denorms?
> That does look like a correct change. I'll fold it in.
> Please let us know if you encounter anything else.
Thanks so much. With these fixes, all of my long double math library
tests in picolibc are passing now (once I fixed a bunch of additional
m68k-denorm related math library bugs). That
x8000 0x
I think the enclosed additional patch fixes this. I've still got 75 fmal
failures on this target, but the obvious 'multiply is broken' problem
appears fixed.
From b722c92f8329f56f5243496eca3779f1156aff4f Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Sun, 20 Aug 2023 18:20
I'm doing some testing of an fmal implementation and discovered some
"odd" results on m68k where the emulated 80-bit FPU is generating
results that don't match how GCC computes things. Assuming gcc is
correct, this means there are some subtle bugs in how qemu is handling
denorms for this
Add helpers for reading/writing the 68881 FPSR register so that
changes in floating point exception state can be seen by the
application.
Call these helpers in pre_load/post_load hooks to synchronize
exception state.
Signed-off-by: Keith Packard
---
target/m68k/cpu.c| 12
> Good catch. Mostly ok.
Thanks much for looking at this.
> No need for inline markers.
Thanks.
> In general it is bad form to call HELPER(foo) directly. In this case
> it doesn't hurt, but better form to reverse the implementations.
Good point. I had copied this from the arm vfp code
Add helpers for reading/writing the 68881 FPSR register so that
changes in floating point exception state can be seen by the
application.
Signed-off-by: Keith Packard
---
target/m68k/cpu.h| 2 ++
target/m68k/fpu_helper.c | 72
target/m68k
The first two patches mirror similar patches I recently sent for nios2.
1. Use correct parameter for EXIT (d1 instead of d0)
2. Fix use of deposit64 in LSEEK (argument order was incorrect)
The second patch has also been submitted by Peter Maydell, it's
included here because it was required to
Instead of using d0 (the semihost function number), use d1 (the
provide exit status).
Signed-off-by: Keith Packard
---
target/m68k/m68k-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c
index 88ad9ba814..12235759c7
for non-CodeFire processors by matching BKPT #0
instructions. When semihosting is disabled, convert those
back to illegal op exceptions.
Signed-off-by: Keith Packard
---
target/m68k/cpu.h | 1 +
target/m68k/op_helper.c | 16
target/m68k/translate.c | 4
3 files change
The arguments for deposit64 are (value, start, length, fieldval); this
appears to have thought they were (value, fieldval, start,
length). Reorder the parameters to match the actual function.
Signed-off-by: Keith Packard
---
target/m68k/m68k-semi.c | 2 +-
1 file changed, 1 insertion(+), 1
> Yeah, the closest to a "standard" we have for nios2 is that
> I asked the Codesourcery folks to document it in the libgloss
> sources and put the URL to it in a comment at the top of
> nios2-semi.c, given that there's no official spec and the
> original and main guest-side user is libgloss.
>
Instead of using R_ARG0 (the semihost function number), use R_ARG1
(the provided exit status).
Signed-off-by: Keith Packard
---
target/nios2/nios2-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c
index
> says that for HOSTED_EXIT the exit code is in r5,
> not in a parameter block pointed to by r5. That
> would imply that the correct change is to use
> R_ARG1 rather than R_ARG0 here.
Ah, thanks -- I hadn't managed to find the actual standard yet. I'll
resubmit with that fixed.
--
-keith
The arguments for deposit64 are (value, start, length, fieldval); this
appears to have thought they were (value, fieldval, start,
length). Reorder the parameters to match the actual function.
Signed-off-by: Keith Packard
---
target/nios2/nios2-semi.c | 2 +-
1 file changed, 1 insertion(+), 1
Instead of using the function number (which is always zero), fetch the
application-provided exit code argument and pass that to the two exit
functions.
Signed-off-by: Keith Packard
---
target/nios2/nios2-semi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target
bugs in other cases.
Signed-off-by: Keith Packard
---
semihosting/syscalls.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c
index 508a0ad88c..78ba97d7ab 100644
--- a/semihosting/syscalls.c
+++ b/semihosting
Richard Henderson writes:
> Reported-by: Keith Packard
> Signed-off-by: Richard Henderson
Looks good to me, and it passes my very simple test when run on s390.
Tested-by: Keith Packard
--
-keith
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Richard Henderson writes:
> The signed information is still there, merged with the typecode:
>
> #define dh_typecode_void 0
> #define dh_typecode_noreturn 0
> #define dh_typecode_i32 2
> #define dh_typecode_s32 3
> #define dh_typecode_i64 4
> #define dh_typecode_s64 5
> #define dh_typecode_ptr 6
This issue was originally discovered when running snek on s390x under
qemu 6.2:
https://github.com/keith-packard/snek/issues/58
Signed-off-by: Keith Packard
---
include/exec/helper-head.h | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/in
Alex Bennée writes:
> +asprintf(_info, "heap: %p -> %p\n", info.heap_base,
> info.heap_limit);
> +__semi_call(SYS_WRITE0, (uintptr_t) heap_info);
> +if (info.heap_base != brk) {
That requires qemu to know a lot about the run-time environment, which
it rarely does in my experience
Alex Bennée writes:
> Note: we aren't currently testing riscv32 due to missing toolchain for
> check-tcg tests.
That's surprising -- the usual risc-v toolchain supports both 64- and
32- bit targets.
Othewise, this patch is
Reviewed-by: Keith Packard
--
-keith
signature.asc
Descr
Alistair Francis writes:
> I have started on the effort, but I have not finished yet. Adding
> riscv_cpu_is_32bit() was the first step there and I have some more
> patches locally but I don't have anything working yet.
That's awesome. I think waiting until we see what APIs you're developing
for
Peter Maydell writes:
> ILP32 for AArch64 is a zombie target -- it is kinda-sorta
> supported in some toolchains but has no support in eg
> the Linux syscall ABI. The semihosting ABI does not implement
> any kind of ILP32 variant -- you can have A32/T32 (AArch32)
> semihosting, where register
Peter Maydell writes:
> For semihosting for Arm what matters is "what state is the core
> in at the point where it makes the semihosting SVC/HLT/etc insn?".
Ok, that means we *aren't* talking about -mabi=ilp32, which is good --
in my current picolibc implementation, the semihosting code uses a
Peter Maydell writes:
> Also, you don't seem to have the correct "is the CPU in
> 32-bit or 64-bit mode" test here: you cannot rely on target_ulong
> being the right size, you must make a runtime check.
Do you mean whether a dual aarch64/arm core is in arm or aarch64 mode,
or whether an aarch64
Alex Bennée writes:
> I'm not sure this every worked properly and it's certainly not
> exercised by check-tcg or Peter's semihosting tests. Hoist it into
> it's own helper function and attempt to validate the results in the
> linux-user semihosting test at the least.
The patch is mostly code
qemu is run with the '-s' flag (create a
gdb protocol socket), but without the '-S' flag (delay until 'c'
command is received).
Signed-off-by: Keith Packard
---
gdbstub.c | 51 +--
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git
Alex Bennée writes:
> It would be better to wrap the test in a function (static bool
> is_connected()?) so the semantic meaning is clear in the code and we can
> fix things in one place if needed.
That makes good sense to me.
> How exactly did you create the segfault? Just starting with -s and
Alistair Francis writes:
> Whoops, I thought I had already reviewed this commit.
You had provided quite extensive review with lots of useful comments,
but never added the magic tag for this commit :-)
--
-keith
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Description: PGP signature
From: Kito Cheng
This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.
Verified GCC testsuite with newlib/semihosting.
Signed-off-by: Kito Cheng
Reviewed-by: Keith Packard
Message-Id: <20201214200713.3886611-7-
GET_ARG and stores data back into the argument
block.
Signed-off-by: Keith Packard
Reviewed-by: Alistair Francis
v2:
Add common_semi_rambase hook to get memory address for
SYS_HEAPINFO call.
Message-Id: <20201214200713.3886611-4-kei...@keithp.com>
-
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard
Message
-by: Keith Packard
Reviewed-by: Alistair Francis
Message-Id: <20201214200713.3886611-3-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 16 ++--
hw/semihosting/common-semi.h | 36 +++
linux-user/aarch64/cpu_loop.c | 3 ++-
linux-us
This series adds support for RISC-V Semihosting, version 0.2 as
specified here:
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
This specification references the ARM semihosting release 2.0 as
specified here:
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-9-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/semihosting/common-
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-8-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 16
include/qemu/timer.h | 2 ++
util/qemu-timer-common.c | 4
3
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-10-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-
riable,
CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM
softmmu and linux-user default configs. The contents of the source
files has not been changed in this patch.
Signed-off-by: Keith Packard
Reviewed-by: Alistair Francis
v2
Place common-semi.c name in arm_ss, just
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-6-
if a gdb
connection is currently acive. For the second question, I don't have a
clear idea; mixing gdb and native calls seems problematic for stateful
operations like file open/close.
Signed-off-by: Keith Packard
---
gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index b0648c3812..abc15bf219 100644
--- a/hw/semihosting
riable,
CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM
softmmu and linux-user default configs. The contents of the source
files has not been changed in this patch.
Signed-off-by: Keith Packard
Reviewed-by: Alistair Francis
v2
Place common-semi.c name in arm_ss, just
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index b1368d945c
-by: Keith Packard
Reviewed-by: Alistair Francis
---
hw/semihosting/common-semi.c | 16 ++--
hw/semihosting/common-semi.h | 36 +++
linux-user/aarch64/cpu_loop.c | 3 ++-
linux-user/arm/cpu_loop.c | 3 ++-
target/arm/cpu.h | 8
From: Kito Cheng
This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.
Verified GCC testsuite with newlib/semihosting.
Signed-off-by: Kito Cheng
Reviewed-by: Keith Packard
---
linux-user/riscv/cpu_loop.c | 5
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 16
include/qemu/timer.h | 2 ++
util/qemu-timer-common.c | 4
3 files changed, 22 insertions(+)
diff --git a/hw/semihosting
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard
---
GET_ARG and stores data back into the argument
block.
Signed-off-by: Keith Packard
Reviewed-by: Alistair Francis
v2:
Add common_semi_rambase hook to get memory address for
SYS_HEAPINFO call.
---
hw/semihosting/common-semi.c | 351
. Change internal semihosting interfaces
4. Fix SYS_HEAPINFO crash on ARM
5-6. Add RISC-V semihosting implementation
7-9. Add missing semihosting operations from release 2.0
Signed-off-by: Keith Packard
Alex Bennée writes:
> Hmm scratch that... it fails in a number of linux-user only builds with:
>
> /usr/bin/ld:
> libqemu-aarch64_be-linux-user.fa.p/linux-user_aarch64_cpu_loop.c.o: in
> function `cpu_loop':
> /builds/stsquad/qemu/build/../linux-user/aarch64/cpu_loop.c:133: undefined
>
at applies cleanly
on top of the rest of my series, so I think we can just leave it like
that unless someone wants it presented differently. Not sure why I
thought this was working before; I clearly missed the most important
bit.
Reviewed-by: Keith Packard
I've got a github repo with these bits in
Kito Cheng writes:
> Hi Keith:
>
> Thanks for the patch, I've verified with newlib semihosting support
> which is contributed by Craig Blackmore from embecosm,
> and I would like to add semihosting to user mode, do you mind add this
> patch into this patch series?
I tried to add that already,
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard
---
hw/semihost
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 16
include/qemu/timer.h | 2 ++
util/qemu-timer-common.c | 4
3 files changed, 22 insertions(+)
diff --git a/hw/semihosting
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index 9a04d98e4e..fda0e714ef 100644
--- a/hw/semihosting
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index c84b0d906b
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
GET_ARG and stores data back into the argument
block.
Signed-off-by: Keith Packard
Reviewed-by: Alistair Francis
v2:
Add common_semi_rambase hook to get memory address for
SYS_HEAPINFO call.
---
hw/semihosting/common-semi.c | 350
riable,
CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM
softmmu and linux-user default configs. The contents of the source
files has not been changed in this patch.
Signed-off-by: Keith Packard
Reviewed-by: Alistair Francis
v2
Place common-semi.c name in arm_ss, just
. Change internal semihosting interfaces
4. Fix SYS_HEAPINFO crash on ARM
5. Add RISC-V semihosting implementation
6-8. Add missing semihosting operations from release 2.0
Signed-off-by: Keith Packard
-by: Keith Packard
Reviewed-by: Alistair Francis
---
hw/semihosting/common-semi.c | 16 ++--
hw/semihosting/common-semi.h | 36 +++
linux-user/aarch64/cpu_loop.c | 3 ++-
linux-user/arm/cpu_loop.c | 3 ++-
target/arm/cpu.h | 8
Alistair Francis writes:
> I'm not sure common is the right name here, as it is really just ARM
> and RISC-V, but I don't have a better name to use.
We've already seen some interest for other architectures; Benjamin
Herrenschmidt was looking at using this for PPC, for instance. He got
stuck at
to
send out a new version here. Sorry!
From a6cb1a52a6c2404a9bdc22bb5e00bccb65ab0730 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 26 Oct 2020 12:20:01 -0700
Subject: [PATCH 4/4] riscv: Add semihosting support [v12]
Adapt the arm semihosting support code for RISCV. This implementat
Alistair Francis writes:
> Reviewed-by: Alistair Francis
Thanks much. I think we'll need some help getting the next two patches
reviewed; that touches ARM code. The last patch is also RISC-V only.
--
-keith
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Description: PGP signature
the referenced commit was applied.
Signed-off-by: Keith Packard
---
hw/semihosting/config.c | 21 ++-
hw/semihosting/console.c | 58 ++-
include/hw/semihosting/semihost.h | 4 +--
softmmu/vl.c | 5 +--
4 files changed
Alex Bennée writes:
> specific_ss.add(when: 'CONFIG_ARM_STYLE_SEMIHOSTING',
> if_true: files ('common-semi.c'))
I've sent another version of the series using this plan. It does look a
bit nicer as the only changes required when adding support to another
target is to place
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
-by: Keith Packard
---
hw/semihosting/common-semi.c | 16 ++--
hw/semihosting/common-semi.h | 36 +++
linux-user/aarch64/cpu_loop.c | 3 ++-
linux-user/arm/cpu_loop.c | 3 ++-
target/arm/cpu.h | 8
target/arm/helper.c
(as it does on AARCH64)
#define SET_ARG(n, val)
This mirrors GET_ARG and stores data back into the argument
block.
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 326 ++-
1 file changed, 164 insertions(+), 162 deletions
This series adapts the existing ARM semihosting code to be
target-independent, and then uses that to provide semihosting support
for RISC-V targets.
riable,
CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM
softmmu and linux-user default configs. The contents of the source
files has not been changed in this patch.
Signed-off-by: Keith Packard
v2
Place common-semi.c name in arm_ss, just as arm-semi.c was
v3
Alex Bennée writes:
> I don't think we want arm specific adds in the common code. I think what
> Peter was suggesting is a new config symbol that only ARM and RISC
> define, e.g something like:
>
> specific_ss.add(when: 'CONFIG_ARM_STYLE_SEMIHOSTING',
> if_true: files
Peter Maydell writes:
>> arm_ss.add(when: 'CONFIG_TCG', if_true: files ('common-semi.c'))
>> riscv_ss.add(files('common-semi.c'))
>>
>> This appears to work in my testing (building arm, risc-v and x86_64
>> configs).
>
> I'm not a kconfig expert but it might be preferable to have
Peter Maydell writes:
>> +specific_ss.add(when: 'CONFIG_TCG', if_true: files ('common-semi.c'))
>
> I think this adds this file to the compilation for all TCG targets;
> you only want it for targets which have Arm-semihosting-ABI compatible
> semihosting. (Various other targets either don't have
(as it does on AARCH64)
#define SET_ARG(n, val)
This mirrors GET_ARG and stores data back into the argument
block.
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 326 ++-
1 file changed, 164 insertions(+), 162 deletions
change, but the contents
of the two files are unchanged.
Signed-off-by: Keith Packard
---
target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0
hw/semihosting/meson.build| 2 ++
linux-user/arm/meson.build| 3 ---
linux-user/me
-by: Keith Packard
---
hw/semihosting/common-semi.c | 16 ++--
hw/semihosting/common-semi.h | 36 +++
linux-user/aarch64/cpu_loop.c | 3 ++-
linux-user/arm/cpu_loop.c | 3 ++-
target/arm/cpu.h | 8
target/arm/helper.c
This series first adapts the existing ARM semihosting code to be
architecture-neutral, then adds RISC-V semihosting support using that.
Patch 1/4 moves the ARM semihosting support code to common directories and
adapts the build system to match.
Patch 2/4 changes the public API to this code to
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
Richard Henderson writes:
> On 10/23/20 2:49 PM, Keith Packard via wrote:
>> static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
>> {
>> -generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
>> +uint32_t pre= opcode_at(>base, ctx->base.pc_n
Richard Henderson writes:
> This is no different to EXCP_DEBUG, really, which is also internal to qemu but
> user-visible in the same way. Just adjust the logging in
> riscv_cpu_do_interrupt.
I think that's already handled by the early return in
riscv_cpu_do_interrupt after handling the
Alistair Francis writes:
> The sifive_u and sifive_e model real hardware (the names are confusing
> I agree) so I would rather not add a virtual device.
That seems reasonable; semihosting will be a much better solution for
the long term anyways. I posted this because we've been maintaining it
Alistair Francis writes:
Thanks much for taking time to review this patch in detail. I've left
the indicated changes in a new version of my riscv-semihost branch here:
https://github.com/keith-packard/qemu/tree/riscv-semihost
I'll post a new version once we've wound up discussion
Alistair Francis writes:
> I also don't see this in the FU540 memory map.
Same as for the FE310 -- this is a QEMU-only device. In addition,
OpenSBI expects to use this when built for QEMU.
--
-keith
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Alistair Francis writes:
> I don't see this mentioned in the FE310 data sheet. Is it included in
> the hardware?
This is strictly a virtual device used to support 'power off' when
running under QEMU. We need either this or semihosting support for doing
automated testing. Our tests currently use
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
The SiFive test device provides a mechanism for terminating the qemu
instance from the emulated system. This patch adds that device to the
sifive_u target, including constructing a suitable FDT node.
Signed-off-by: Keith Packard
---
hw/riscv/sifive_u.c | 15 +++
include/hw
The SiFive test device provides a mechanism for terminating the qemu
instance from the emulated system. This patch adds that device to the
sifive_e target.
Signed-off-by: Keith Packard
---
hw/riscv/sifive_e.c | 4
include/hw/riscv/sifive_e.h | 1 +
2 files changed, 5 insertions
The SiFive test device, which is already available in the qemu tree,
allows the system under emulation to shut down qemu. This is currently
used by OpenSBI to terminate QEMU at powerdown time. These two patches
add this device to the two sifive models.
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception
Max Filippov writes:
> Most of them are due to unsupported/differently implemented
> syscalls.
Yeah, I think that was the basis of my confusion -- qemu-arm is not a
bare metal environment, and my work is focused on enabling application
development in that environment.
--
-keith
rm was designed to run user-mode Linux
applications on top of another Linux system (given that it's called
'arm-linux-user' in the qemu configuration code). That's why I hadn't
even tried using it for this work.
> Sure, but "machine-that-works-for-keith-packard" isn't really
>
Peter Maydell writes:
> So, I'm really dubious about adding more "virtual"
> not-real-hardware boards. We have "virt" because we
> absolutely have to have it for KVM purposes; but otherwise
> "emulate real hardware" gives us a concrete specification
> of what we're trying to do and tends to lead
'virtm' is a hardware target that is designed to be used for compiler
and library testing on Cortex-M processors. It supports all cortex-m
processors and includes sufficient memory to run even large test
cases.
Signed-off-by: Keith Packard
---
MAINTAINERS | 9 +++-
hw/arm
4824c418020c Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 21 Oct 2019 01:12:13 -0700
Subject: [PATCH] riscv: Add semihosting support [v5]
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented
epository.
https://github.com/keith-packard/riscv-semihosting-spec/
The goal is to enable RISC-V semihosting implementations that share most
of the underlying details with existing ARM semihosting implemenations.
--
-keith
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Palmer Dabbelt writes:
> This isn't working for me. When I apply it on top of my for-master (which is
> very close to master), I get
> warning: while parsing target description (at line 1): Could not load XML
> document "riscv-64bit-fpu.xml"
If you're building from an existing
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